CN109256335B - Method for forming pattern of semiconductor structure - Google Patents

Method for forming pattern of semiconductor structure Download PDF

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CN109256335B
CN109256335B CN201710571872.7A CN201710571872A CN109256335B CN 109256335 B CN109256335 B CN 109256335B CN 201710571872 A CN201710571872 A CN 201710571872A CN 109256335 B CN109256335 B CN 109256335B
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layer
etching
photoresist
material layer
gas
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CN109256335A (en
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不公告发明人
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Changxin Memory Technologies Inc
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Changxin Memory Technologies Inc
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31105—Etching inorganic layers
    • H01L21/31111—Etching inorganic layers by chemical means
    • H01L21/31116—Etching inorganic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31127—Etching organic layers
    • H01L21/31133—Etching organic layers by chemical means
    • H01L21/31138—Etching organic layers by chemical means by dry-etching
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32133—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only
    • H01L21/32135—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by chemical means only by vapour etching only

Abstract

The invention provides a method for forming a pattern of a semiconductor structure, which comprises the following steps: providing a substrate, sequentially forming a target material layer, a first anti-reflection material layer, a second anti-reflection material layer and a photoresist layer on the substrate, patterning the photoresist layer to form a preset pattern, taking the photoresist layer with the preset pattern as a mask, etching the second anti-reflection material layer by adopting first etching gas, wherein the first etching gas comprises photoresist etching slowing gas, so that the etching selection ratio of the second anti-reflection material layer to the photoresist layer is more than 3:1, taking the second anti-reflection layer as the mask, etching the first anti-reflection material layer by adopting second etching gas, and etching the target material layer by taking the first anti-reflection layer as the mask to form the target layer with the preset pattern. Through the scheme, the semiconductor structure forming method can reduce the depth-to-width ratio of the photoresist layer, effectively reduce the divergence degree, increase the exposure accuracy and prevent the pattern damage phenomenon caused by photoresist residue.

Description

Method for forming pattern of semiconductor structure
Technical Field
The invention belongs to the technical field of semiconductor manufacturing, and particularly relates to a pattern forming method of a semiconductor structure.
Background
In semiconductor manufacturing, a photoresist layer (PR) and an intermediate mask layer are often used to copy a desired pattern into a device to form a desired semiconductor structure. In practice, to increase the lithography effectiveness, various anti-reflective coatings are usually applied under the photoresist layer, such as a bottom anti-reflective coating (BARC), and the BARC layer under the photoresist layer (photoresist layer) can reduce the reflection of light from the lower surface of the photoresist during exposure so that most of the energy of the exposure is absorbed by the photoresist, and a more preferred material for achieving uniform exposure of the photoresist is a Si-based anti-reflective coating, or Si-ARC.
At present, with the narrowing of the line width, the photoresist thickness is limited due to the limitation of high-precision cd (critical dimension) control and the photoresist exposure developing capability, and the photoresist cannot be used as an effective sacrificial layer, so that by utilizing the material selection ratio characteristic of Si-ARC to BARC, the photoresist is firstly used as the sacrificial layer, the Si-ARC is etched, then the Si-ARC is used as the sacrificial layer to etch the BARC, and finally the BARC with high thickness can be manufactured, and then the target material is etched.
Therefore, it is necessary to provide a method for forming a semiconductor structure by etching to solve the problems of photoresist collapse and CD accuracy caused by a too thick photoresist layer.
Disclosure of Invention
In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a method for forming a pattern of a semiconductor structure, which is used to solve the problems of photoresist collapse and CD accuracy caused by too thick photoresist layer in the prior art.
To achieve the above and other related objects, the present invention provides a method for forming a semiconductor structure, comprising:
1) providing a substrate;
2) sequentially forming a target material layer, a first anti-reflection material layer, a second anti-reflection material layer and a photoresist layer on the substrate;
3) patterning the photoresist layer to form a photoresist layer with a preset pattern;
4) taking the photoresist layer with the preset pattern as a mask, and performing first etching on the second antireflection material layer by adopting first etching gas to form a second antireflection layer with a corresponding preset pattern, wherein the first etching gas comprises photoresist etching slowing gas, so that the etching selection ratio of the first etching gas to the second antireflection material layer and the photoresist layer is greater than 3: 1;
5) taking the photoresist as a sacrificial layer and the second anti-reflection layer as a mask, and performing second etching on the first anti-reflection material layer by adopting second etching gas to form a first anti-reflection layer with a corresponding preset pattern; and
6) and carrying out third etching on the target material layer by taking the second anti-reflection layer as a sacrificial layer and the first anti-reflection layer as a mask so as to form a target layer with a corresponding preset pattern.
As a preferable aspect of the present invention, in step 4), the photoresist etching slowing gas included in the first etching gas is hydrogen.
As a preferable aspect of the present invention, the first etching gas further includes carbon tetrafluoride, and a content of the hydrogen gas is 40% to 60% of the first etching gas.
In a preferable embodiment of the present invention, in step 5), the second etching gas includes a lateral shielding gas for the etched material layer.
In a preferred embodiment of the present invention, the lateral shielding gas is carbon monoxide.
As a preferable aspect of the present invention, the second etching gas further includes oxygen, wherein the content of the carbon monoxide accounts for 70% to 90% of the second etching gas.
As a preferable aspect of the present invention, in step 2), the second antireflection material layer is a silicon-containing antireflection coating layer.
As a preferable scheme of the present invention, in step 2), the height of the photoresist layer is 1 to 3 times of the height of the second antireflective material layer, the height of the first antireflective material layer is 4 to 6 times of the height of the second antireflective material layer, and in step 4), after the first etching process is performed, the height of the remaining photoresist layer is not less than 1.2 times of the height of the second antireflective material layer.
As a preferable aspect of the present invention, the step 1) further includes a step of forming an etch stop layer on the substrate.
As a preferable scheme of the present invention, between step 3) and step 4), a step of performing a residue treatment on the photoresist layer with the preset pattern by using dry etching is further included, so as to remove the residue at the bottom of the photoresist layer with the preset pattern.
As a preferable embodiment of the present invention, the reaction gas for dry etching includes chlorine, argon, hydrogen bromide gas, and oxygen.
As described above, the method for forming a semiconductor structure of the present invention has the following advantages:
1) according to the forming method of the semiconductor structure, when the line width is reduced, the depth-to-width ratio of the photoresist layer can be reduced, so that the phenomenon of photoresist collapse (Toppling) is reduced, and the problem of bottom residues is reduced;
2) according to the forming method of the semiconductor structure, when light passes through the photoresist layer, the path traveled by the light is blocked by the photoresist molecules and is diffused, the thickness of the photoresist layer can be reduced, the diffusion degree can be effectively reduced, and the exposure accuracy is improved;
3) the forming method of the semiconductor structure can increase the effective residual thickness of the photoresist in the etching process by taking the photoresist layer as the mask, thereby preventing the pattern damage phenomenon caused by too little effective photoresist residue;
4) the forming method of the semiconductor structure provided by the invention can effectively carry out lateral protection on the layer of the etched material in the process of etching the anti-emitting layer.
Drawings
Fig. 1 is a flow chart illustrating steps of a method for forming a semiconductor structure according to the present invention.
Fig. 2 to 10 are schematic views showing structures formed in the steps of the semiconductor structure forming method according to the present invention, wherein,
FIG. 2 is a schematic structural diagram of step 1) in the formation of a semiconductor structure according to the present invention;
FIGS. 3(a) and 3(b) are schematic structural diagrams of step 2) in the formation of the semiconductor structure provided by the present invention;
FIG. 4 is a schematic structural diagram of step 3) in the formation of the semiconductor structure provided by the present invention;
FIG. 5 is a schematic structural diagram of step 4) in the formation of a semiconductor structure according to the present invention;
FIG. 6 is a schematic structural diagram of step 5) in the formation of a semiconductor structure according to the present invention;
fig. 7 and fig. 8 are schematic structural diagrams of step 6) in the formation of the semiconductor structure provided by the present invention.
FIG. 9(a) is a schematic diagram of a photolithography process in a high photoresist layer thickness in the prior art.
FIG. 9(b) is a schematic diagram of a lithographic path in a low photoresist layer thickness in accordance with the present invention.
Fig. 10(a) shows the etch rate of photoresist, silicon dioxide, and polysilicon as a function of hydrogen content.
FIG. 10(b) shows the etch selectivity of a silicon-containing antireflective layer to a photoresist layer as a function of hydrogen content.
Figure 11 is a top view of the device structure after excessive damage to the photoresist layer.
FIG. 12 is a schematic diagram of a structure causing lateral etching of a layer of material being etched during an etching process.
FIG. 13 is a schematic view of a bottom-formed photoresist residue after patterning a photoresist layer.
Description of the element reference numerals
11 substrate
12 layer of target material
121 target layer with preset pattern
13 first layer of antireflection material
131 first antireflection layer
132 remaining first anti-reflection layer
14 second antireflection material layer
141 second anti-reflection layer
142 remaining second anti-reflective layer
15 Photoresist layer
151 photoresist layer with preset pattern
152 remaining photoresist layer
16 etch stop layer
S1-S6
Detailed Description
The embodiments of the present invention are described below with reference to specific embodiments, and other advantages and effects of the present invention will be easily understood by those skilled in the art from the disclosure of the present specification. The invention is capable of other and different embodiments and of being practiced or of being carried out in various ways, and its several details are capable of modification in various respects, all without departing from the spirit and scope of the present invention.
Please refer to fig. 1 to 13. It should be noted that the drawings provided in the present embodiment are only schematic and illustrate the basic idea of the present invention, and although the drawings only show the components related to the present invention and are not drawn according to the number, shape and size of the components in actual implementation, the form, quantity and proportion of the components in actual implementation may be changed arbitrarily, and the layout of the components may be more complicated.
Referring to fig. 1, the present invention provides a method for forming a pattern of a semiconductor structure, comprising the steps of:
1) providing a substrate;
2) sequentially forming a target material layer, a first anti-reflection material layer, a second anti-reflection material layer and a photoresist layer on the substrate;
3) patterning the photoresist layer to form a photoresist layer with a preset pattern;
4) taking the photoresist layer with the preset pattern as a mask, and performing first etching on the second antireflection material layer by adopting first etching gas to form a second antireflection layer with a corresponding preset pattern, wherein the first etching gas comprises photoresist etching slowing gas, so that the etching selection ratio of the first etching gas to the second antireflection material layer and the photoresist layer is greater than 3: 1;
5) taking the photoresist layer as a sacrificial layer and the second anti-reflection layer as a mask, and performing second etching on the first anti-reflection material layer by adopting second etching gas to form a first anti-reflection layer with a corresponding preset pattern; and
6) and carrying out third etching on the target material layer by taking the second anti-reflection layer as a sacrificial layer and the first anti-reflection layer as a mask so as to form a target layer with a corresponding preset pattern.
The method of forming the semiconductor structure of the present invention is described in detail below with reference to the accompanying drawings.
As shown in S1 in fig. 1 and fig. 2, step 1) is performed to provide a substrate 11;
specifically, the base 11 may be a semiconductor structure with any target material layer grown thereon, and in this embodiment, the base is a semiconductor substrate with a functional layer (target material layer), and further, the substrate may be a commonly used semiconductor silicon-based substrate such as a Si substrate, a silicon-on-insulator (SOI), or the like, or a Ge-on-insulator substrate, or a compound semiconductor substrate such as SiGe, GaAs, GaN, InSb, InAs, or the like, and the substrate is selected according to actual circumstances.
As an example, step 1) further includes a step of forming an etch stop layer 16 on the substrate 11, as shown in fig. 3 (b).
Specifically, the etch stop layer 16 may be used as a protective layer for etching a target material, and the material thereof includes, but is not limited to, a silicon nitride material.
As shown in S2 in fig. 1 and fig. 3(a) and 3(b), step 2) is performed to sequentially form a target material layer 12, a first anti-reflective material layer 13, a second anti-reflective material layer 14 and a photoresist layer 15 on the substrate 11, as shown in fig. 3 (a);
as an example, in step 2), the second anti-reflective material layer 14 is a silicon-containing anti-reflective coating layer.
Specifically, in the present embodiment, the first anti-reflective material layer 13 is an anti-reflective coating layer, the second anti-reflective material layer 14 is an anti-reflective coating layer containing silicon, in a photolithography step, one or more anti-reflective coating (ARC) layers are provided under the photoresist layer mask, such as bottom anti-reflective coating (BARC) and/or dielectric anti-reflective coating (DARC), help reduce or eliminate reflections during photoresist exposure, reduce unwanted reflections from underlying structures into a photoresist layer located above an anti-reflective coating (ARC) layer, this avoids the defects caused by the above phenomena, such as sinusoidal "scalloping" on the photoresist sidewalls, etc., the material of the reflective layer may be organic or inorganic based, for example, the inorganic BARC layer may be composed of titanium nitride (TiN) and silicon oxynitride (SiON). In particular, the silicon-containing anti-reflective coating layer may realize a more desirable photolithography process, more effectively realize uniform exposure of a photoresist, and in addition, the silicon content of the layer may be highest at a middle portion in a height direction of the structure layer, and may be gradually decreased from the middle to the top or the bottom.
As an example, in the step 2), the height of the photoresist layer is 1 to 3 times of the height of the second antireflection material layer, and the height of the first antireflection material layer is 4 to 6 times of the height of the second antireflection material layer.
As an example, the height of the first anti-reflection material layer is 80-250 nm, the height of the second anti-reflection material layer is 20-60 nm, and the height of the photoresist layer is 20-200 nm.
Specifically, the height relationship of the material layers is determined according to the actual target material layer and the etching ratio of the material of the etched layer and the material of the mask layer, in this embodiment, especially when the first anti-reflection material layer 13 is a bottom anti-reflection coating layer and the second anti-reflection material layer 14 is a silicon-containing anti-reflection coating layer, the above ratio is selected, which can save cost and obtain a high-quality semiconductor structure, in this embodiment, the height of the photoresist layer 15 is 50nm, the height of the second anti-reflection material layer 14 is 34nm, and the height of the first anti-reflection material layer 13 is 170 nm.
As shown in S3 in fig. 1 and fig. 4, performing step 3), patterning the photoresist layer 15 to form a photoresist layer 151 with a predetermined pattern;
specifically, by exposing and developing to realize the purpose of patterning the photoresist layer 15, light contacts the surface of the photoresist material to change the chemical composition of the photoresist material, and a developer can remove a portion of the photoresist material to obtain a pattern of a semiconductor structure to be formed.
As shown in S4 in fig. 1 and fig. 5, performing step 4), with the photoresist layer 151 with the preset pattern as a mask, etching the second anti-reflection material layer 14 by using a first etching gas to form the second anti-reflection layer 141 with the preset pattern, where the first etching gas includes a photoresist etching slowing gas, so that an etching selectivity ratio of the first etching gas to the second anti-reflection material layer 14 and the photoresist layer 15 is greater than 3: 1;
specifically, the second anti-reflection material layer 14 is etched to copy a required pattern shape onto the second anti-reflection material layer to form the second anti-reflection layer 141 with the preset pattern, which is further used as a sacrificial layer in the whole semiconductor structure forming process, in the etching process, a photoresist etching slowing gas is added, so that the etching rate of the photoresist is reduced, and the etching selectivity ratio of the second anti-reflection material layer 14 to the photoresist layer 15 is greater than 3:1, that is, the etching rate of the second anti-reflection material layer 14 is greater than 3 times, preferably 3 to 6 times, of the etching rate of the photoresist 15, and in this embodiment, the etching rate is selected to be 5 times.
It should be noted that, based on the above design of the etching process and the etching parameters (such as the etching gas), the thickness of the photoresist layer 15 formed in advance in step 2) is greatly reduced, which has many advantages, on one hand, as shown in fig. 9(a) and 9(b), when the thickness of the photoresist layer is reduced, the path traveled by the light is blocked and diffused by the photoresist molecules during the process of passing through the photoresist, and the decrease of the photoresist thickness can effectively reduce the degree of diffusion and increase the exposure accuracy, wherein fig. 9(a) is a schematic diagram of the accuracy of the high photoresist layer thickness in the lithography in the prior art, and fig. 9(b) is an improvement of the low photoresist thickness on the lithography accuracy in the present application; on the other hand, if the photoresist has a higher thickness, the photoresist has a higher aspect ratio in the process of patterning the photoresist, thereby causing the phenomenon of collapse of the photoresist.
As an example, in step 4), the photoresist etching reducing gas included in the first etching gas is hydrogen.
As an example, the first etching gas further includes carbon tetrafluoride, wherein the hydrogen gas accounts for 40% to 60% of the first etching gas.
Specifically, the photoresist etching slowing gas can reduce the etching rate of the photoresist, and specifically, refer to fig. 10(a) and 10(b), where 10(a) shows the change of the etching rate of the photoresist, the silicon dioxide and the polysilicon with the change of the hydrogen content in the hydrogen and carbon tetrafluoride mixed gas, and fig. 10(b) shows the change of the etching rate of the etching gas with the change of the hydrogen content in the hydrogen and carbon tetrafluoride mixed gas (left side coordinate) to the silicon-containing anti-reflection layer and the photoresist layer and the change of the etching selection ratio of the silicon-containing anti-reflection layer and the photoresist layer obtained therefrom (right side coordinate), it can be seen that when the hydrogen content is 40% to 60%, the etching selection ratio of the silicon-containing anti-reflection layer to the photoresist layer is higher, so that the lower thickness of the photoresist layer can be selected and set, among them, the hydrogen content is preferably 45% to 58%, and in the present embodiment, 55% is selected.
As an example, in step 4), after the first etching process is performed, the height of the remaining photoresist layer is not less than 1.2 times the height of the second anti-reflection material layer.
Specifically, in this embodiment, after the etching process in step 4), a portion of the photoresist layer 151 with the predetermined pattern is also consumed, as shown in fig. 5, to form a remaining photoresist layer 152, and before the next step, a step of removing the remaining photoresist layer 152 is further included, specifically, the height of the remaining photoresist layer 152 is not less than 1.2 times the height of the second anti-reflective material layer, so that the device structure is not damaged.
It should be noted that, in the prior art, the etching rate of the photoresist is relatively fast, and thus when the photoresist is used as a mask layer to etch the lower material layer, the consumption is too fast, and if the remaining photoresist layer is smaller than the height of the second anti-reflective material layer, the photoresist is damaged, so that the device structure layer is damaged, as shown in fig. 11, which is a top view of the device structure after the photoresist layer is excessively damaged, and a dashed frame of the device structure shows a damaged portion of the photoresist layer.
As shown in S5 in fig. 1 and fig. 6, performing step 5), using the second anti-reflection layer as a mask, and etching the first anti-reflection material layer by using a second etching gas to form a first anti-reflection layer having the predetermined pattern;
as an example, in step 5), the second etching gas includes a lateral protective gas for the etched material layer.
As an example, the lateral shielding gas is carbon monoxide.
As an example, the second etching gas further includes oxygen, wherein the content of the carbon monoxide accounts for 70% to 90% of the second etching gas.
As an example, in step 5), after the etching process is performed, the height of the remaining second anti-reflection layer 142 is greater than 0.95 times the height of the second anti-reflection layer 141 before etching.
As an example, in step 5), after the etching process is performed, the width of the middle position of the first anti-reflection layer 131 obtained by etching is greater than 0.95 times of the width of the second anti-reflection layer 142 left after etching corresponding to the upper and lower positions of the first anti-reflection layer.
Specifically, the first anti-reflective material layer 13 is etched to copy a desired pattern shape onto the first anti-reflective material layer to form the first anti-reflective layer 131 with the predetermined pattern, which further serves as a sacrificial layer in the whole semiconductor structure forming process, during the etching process, a lateral protective gas of an etched material is added to prevent the lateral etching of the etched material layer caused by the etching due to a chemical reaction, in the prior art, a schematic diagram of the lateral etching caused by the etching of the etched material layer, such as the first anti-reflective material layer 13 (e.g., a bottom anti-reflective coating layer), is shown in fig. 12, but the present invention adds a protective gas to prevent the above phenomenon.
Specifically, in this embodiment, the lateral protective gas may be carbon monoxide, the etching mixed gas includes carbon monoxide and oxygen, and when the content of carbon monoxide is 70% to 90%, the etching protective effect is the best, preferably 75% to 85%, and in this embodiment, is selected to be 80%. At this time, as shown in fig. 12, based on the selection of the above etching process conditions, the height (X) of the second anti-reflection layer 142 remaining in the present embodimentremain) Greater than 0.95 times the height (X) of the second anti-reflection layer 141 before etching, and the width (W) of the middle position of the first anti-reflection layer 131 obtained by etchingmiddle) Is greater thanWidth (W) of the second anti-reflection layer 142 left after etching corresponding to the upper and lower sides thereoftop) 0.95 times of.
As an example, between step 3) and step 4), a step of performing a residue treatment on the photoresist layer 151 with the preset pattern by using dry etching is further included to remove the residue at the bottom of the photoresist layer with the preset pattern.
By way of example, the reaction gas for the dry etching includes chlorine, argon, hydrogen bromide gas and oxygen, the etching time is 10-15 s, the power of the power source connected to the upper electrode in the dry etching process is 200-300W, and the power of the power source connected to the lower electrode is 50-100W.
For example, the reaction gas contains chlorine gas in an amount of 50 to 80sccm, argon gas in an amount of 100 to 150sccm, hydrogen bromide gas in an amount of 20 to 30sccm, and oxygen gas in an amount of 20 to 30 sccm.
In particular, during the photolithographic patterning of the photoresist layer 15, photoresist residue may remain at the bottom of the patterned photoresist, as shown in figure 13, the existence of the photoresist residue will affect the shape and size of the final semiconductor structure in the subsequent etching process, in this embodiment, dry etching is used, and low power plasma (200-300W, Top ICP13.56MHz) and (50-100W, bottom CCP 13.56MHz) are used to remove the bottom residue, wherein ICP refers to inductively coupled plasma, CCP refers to capacitively coupled plasma, cost is saved, good residue removal effect is achieved, in this embodiment, the dose of chlorine is 60sccm, the dose of argon is 120sccm, the dose of hydrogen bromide gas is 25sccm, the dose of oxygen is 25sccm, the etching time is 12s, the power of the power source connected to the upper electrode is 220W, and the power of the power source connected to the lower electrode is 60W.
In summary, the present invention provides a method for forming a semiconductor structure, which specifically includes the following steps: 1) providing a substrate; 2) sequentially forming a target material layer, a first anti-reflection material layer, a second anti-reflection material layer and a photoresist layer on the substrate; 3) patterning the photoresist layer to form a photoresist layer with a preset pattern; 4) taking the photoresist layer with the preset pattern as a mask, and etching the second antireflection material layer by adopting first etching gas to form a second antireflection layer with the preset pattern, wherein the first etching gas comprises photoresist etching slowing gas, so that the etching selection ratio of the first etching gas to the second antireflection material layer and the photoresist layer is greater than 3: 1; 5) etching the first anti-reflection material layer by using a second etching gas by taking the second anti-reflection layer as a mask so as to form a first anti-reflection layer with the preset pattern; and 6) etching the target material layer by taking the first anti-reflection layer as a mask so as to form the target layer with the preset pattern. Through the technical scheme, the method for forming the semiconductor structure can reduce the depth-to-width ratio of the photoresist layer when the line width is reduced, thereby reducing the phenomenon of photoresist collapse (Toppling) and reducing the problem of bottom residues; when light passes through the photoresist layer, the path traveled by the light is blocked by the photoresist molecules and is diffused, the forming method can reduce the thickness of the photoresist layer, further effectively reduce the diffusion degree and increase the exposure accuracy; the effective residual thickness of the photoresist can be increased in the process of etching by taking the photoresist layer as a mask, so that the pattern damage phenomenon caused by too little effective photoresist residue can be prevented; in the process of etching the anti-emitting layer, the lateral protection of the layer of the etched material can be effectively carried out. Therefore, the invention effectively overcomes various defects in the prior art and has high industrial utilization value.
The foregoing embodiments are merely illustrative of the principles and utilities of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or change the above-mentioned embodiments without departing from the spirit and scope of the present invention. Accordingly, it is intended that all equivalent modifications or changes which can be made by those skilled in the art without departing from the spirit and technical spirit of the present invention be covered by the claims of the present invention.

Claims (12)

1. A method for forming a pattern of a semiconductor structure, comprising the steps of:
1) providing a substrate;
2) sequentially forming a target material layer, a first anti-reflection material layer, a second anti-reflection material layer and a photoresist layer on the substrate;
3) patterning the photoresist layer to form a photoresist layer with a preset pattern;
4) taking the photoresist layer with the preset pattern as a mask, and performing first etching on the second antireflection material layer by adopting first etching gas to form a second antireflection layer with a corresponding preset pattern, wherein the first etching gas comprises photoresist etching slowing gas, so that the etching selection ratio of the first etching gas to the second antireflection material layer and the photoresist layer is greater than 3: 1;
5) taking the photoresist layer as a sacrificial layer and the second anti-reflection layer as a mask, and performing second etching on the first anti-reflection material layer by adopting second etching gas to form a first anti-reflection layer with a corresponding preset pattern; and
6) and carrying out third etching on the target material layer by taking the second anti-reflection layer as a sacrificial layer and the first anti-reflection layer as a mask so as to form a target layer with a corresponding preset pattern.
2. The method of claim 1, wherein in step 4), the photoresist etch-reducing gas included in the first etching gas is hydrogen.
3. The method of claim 2, wherein the first etching gas further comprises carbon tetrafluoride, and wherein the hydrogen gas is present in an amount of 40% to 60% of the first etching gas.
4. The method as claimed in claim 1, wherein in step 5), the second etching gas comprises a lateral protective gas for the etched material layer.
5. The method as claimed in claim 4, wherein the lateral shielding gas is carbon monoxide.
6. The method of claim 5, wherein the second etching gas further comprises oxygen, and wherein the carbon monoxide is present in an amount of 70% to 90% of the second etching gas.
7. The method as claimed in claim 1, wherein in step 2), the second anti-reflective material layer is a silicon-containing anti-reflective coating layer.
8. The method as claimed in claim 1, wherein the photoresist layer in step 2) has a thickness 1 to 3 times that of the second anti-reflective material layer, and the first anti-reflective material layer has a thickness 4 to 6 times that of the second anti-reflective material layer.
9. The method for forming the pattern of the semiconductor structure according to claim 1, wherein in the step 4), after the first etching process is performed, the thickness of the remaining photoresist layer is not less than 1.2 times the thickness of the second anti-reflective material layer.
10. The method of claim 1, wherein step 1) further comprises forming an etch stop layer on the substrate.
11. The method for forming the pattern of the semiconductor structure according to any one of claims 1 to 10, further comprising a step of performing a residue treatment on the photoresist layer with the predetermined pattern by dry etching to remove the residue on the bottom of the photoresist layer with the predetermined pattern between the step 3) and the step 4).
12. The method of claim 11, wherein the reactive gas for dry etching comprises chlorine, argon, hydrogen bromide gas and oxygen.
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