CN109254617A - Clock signal generation method and device - Google Patents
Clock signal generation method and device Download PDFInfo
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- G—PHYSICS
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- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/04—Generating or distributing clock signals or signals derived directly therefrom
- G06F1/06—Clock generators producing several clock signals
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F21/00—Security arrangements for protecting computers, components thereof, programs or data against unauthorised activity
- G06F21/50—Monitoring users, programs or devices to maintain the integrity of platforms, e.g. of processors, firmware or operating systems
- G06F21/57—Certifying or maintaining trusted computer platforms, e.g. secure boots or power-downs, version controls, system software checks, secure updates or assessing vulnerabilities
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Abstract
This application provides a kind of clock signal generation method and devices, belong to electronic technology field.The described method includes: generating multiple clock signals, each clock signal has different frequencies；Generate random number；According to the random number, clock selection signal and clock gating signal are generated, the clock selection signal in the multiple clock signal for carrying out signal behavior, and the clock gating signal is for controlling clock gating circuit；The selection target clock signal from the multiple clock signal, and export to the clock gating circuit, the target clock signal is clock signal corresponding with the clock selection signal；It controls the clock gating circuit according to the clock gating signal to handle the target clock signal, and the clock signal that exports that treated.The application reduces costs, and enhances versatility, timing closure difficulty when reducing by protective module using clock signal.
Description
Technical field
This application involves electronic technology field, in particular to a kind of clock signal generation method and device.
Background technique
With the development of information technology and the raising of attack level, the various terminals for carrying secret or authorization protection information
Equipment is faced with increasingly severe danger.For example, side-channel attack (the Side Channel gradually come into the open
Attack, SCA) technology.SCA refers to time power consumption, power consumption or the electromagnetic radiation for encryption equipment in the process of running
Etc the leakage of side channel information and to the method attacked of encryption equipment.In order to cope with more and more professional attack, people
Prevention-Security has been done when designing system on chip (System on a Chip, SOC).As shown in Figure 1, typical SOC system
System composition includes: clock source (Clock Source), processor (Central Processing Unit, CPU), storage system
(Memory System), cryptographic system (Crypto System), video system (Video System) and audio system
(Audio System), when the SOC system is attacked, processor and cryptographic system are main targets of attack, and safety
Defend object to be protected.
Fig. 2 is a kind of design method schematic diagram of the secure clock of existing attack protection provided by the embodiments of the present application.Ginseng
See that Fig. 2, oscillator (Oscillator, OSC) can shake ring by inside and generate different delays to generate out of phase
Clock.These clocks can by linear feedback shift register (Linear Feedback shift register,
LFSR linear feedback shift) carries out pseudorandom selection, so that the clock of final output reaches certain random effect.Thus this
When clock of the random clock of sample as other modules, so that the difficulty of the power consumption analysis of other modules and emi analysis increases,
And prevent from being analyzed, steal, attack, reach the function of defensive attack.
During realizing the application, the inventor finds that the existing technology has at least the following problems:
(1) prior art generates the clock signal of out of phase, and special concussion ring and special delay circuit is needed to set
Meter, leads to higher cost；
(2) when different technique and different voltage parameters, circuit shown in foregoing invention embodiment is required again
Design, leads to poor universality；
(3) want to reach better random effect, it is necessary to which the clock signal quantity of out of phase is enough, leads to other
When module uses the clock signal of the out of phase, timing closure difficulty can be very big, thus can not be applied to high-frequency work mould
Block.
Summary of the invention
In order to solve problems in the prior art, the embodiment of the present application provides a kind of clock signal generation method and dress
It sets.The technical solution is as follows:
In a first aspect, providing a kind of clock signal generation method, which comprises
Multiple clock signals are generated, each clock signal has different frequencies；Generate random number；According to described random
Number, generates clock selection signal and clock gating signal, the clock selection signal be used in the multiple clock signal into
Row signal behavior, the clock gating signal is for controlling clock gating circuit；It is selected from the multiple clock signal
Target clock signal is selected, and is exported to the clock gating circuit, the target clock signal is and the clock selection signal
Corresponding clock signal；The clock gating circuit is controlled according to the clock gating signal to carry out the target clock signal
Processing, and export treated clock signal.
Wherein, a kind of AC energy that clock signal can be generated by oscillator or specific component.Oscillator is one
Direct current energy, can be converted to the AC energy with certain frequency by kind energy conversion device.The specific component can lead to
Overfrequency varying circuit or frequency conversion device export the clock signal progress frequency-conversion processing of external certain frequency and former clock
The different clock signal of signal frequency.Random number can be based on number caused by random algorithm.According to clock selection signal
The device for carrying out signal behavior to multiple clock signals can be data selector (Multiplexer, MUX).MUX can basis
Specified input address code is selected specified one from one group of input signal and is sent to output end.Clock gating circuit refers to
One kind using time pulse signal technology in synchronizing sequential circuit, can reduce the logic circuit of chip power-consumption.The clock
Gating circuit can be such that the frequency of the clock signal reduces by exporting or closing the clock signal passed through, and randomness increases
By force.
The embodiment of the present application is special instead of having with pure digi-tal logic circuit compared with existing clock signal generation method
The oscillator and special delay circuit of different oscillation rings, reduce costs；And the Digital Logical Circuits can be directly multiplexed, nothing
It needs to redesign, enhances versatility；And clock source offer is the clock signal of multiple and different frequencies, it is multiple without generating
The clock signal of out of phase, thus timing closure difficulty when reducing by protective module using clock signal.
It is described according to the random number in a kind of possible design of first aspect, generate clock selection signal, comprising:
The clock selection signal is generated according to the port numbers using the random number as port numbers.
In a kind of possible design of first aspect, the selection target clock signal packet from the multiple clock signal
It includes:
Select the clock signal exported by the port numbers corresponding ports as the mesh from the multiple clock signal
Mark clock signal.
It is described according to the random number in a kind of possible design of first aspect, generate clock gating signal, comprising:
Random number caused by each clock selecting time window and the corresponding weight of random number are weighted, if weighting meter
The result of calculation is 1, then generates Clock gating enable signal, if the result of weighted calculation is 0, generates Clock gating and closes letter
Number.
It is described that the Clock gating electricity is controlled according to the clock gating signal in a kind of possible design of first aspect
If it includes: to believe in present clock selection time window Clock gating generated that road, which carries out processing to the target clock signal,
Number it is Clock gating enable signal, then controls the clock gating circuit and export mesh in present clock selection time window
Mark clock signal；If selecting time window clock gating signal generated for Clock gating shutdown signal in present clock,
Then control the clock gating circuit output low level signal.
Second aspect, provides a kind of clock signal generating apparatus, and described device includes:
Clock source module, for generating multiple clock signals, each clock signal has different frequencies；
Stochastic source module, for generating random number；
Shuffle module, for clock selection signal and clock gating signal being generated, when described according to the random number
Clock selection signal is used for for carrying out signal behavior, the clock gating signal in the multiple clock signal to Clock gating
Circuit is controlled；The selection target clock signal from the multiple clock signal, and export to the clock gating circuit, institute
Stating target clock signal is clock signal corresponding with the clock selection signal；According to clock gating signal control
Clock gating circuit handles the target clock signal, and exports treated clock signal.
In a kind of possible design of second aspect, the shuffle module includes:
Signal generation unit, for generating the clock choosing according to the port numbers using the random number as port numbers
Select signal.
In a kind of possible design of second aspect, the shuffle module further include:
Clock selecting unit, for from the multiple clock signal select by the port numbers corresponding ports export when
Clock signal is as the target clock signal.
In a kind of possible design of second aspect, the shuffle module further include:
Signal generation unit is also used to corresponding to random number caused by each clock selecting time window and random number
Weight is weighted, if the result of weighted calculation is 1, generates Clock gating enable signal, if weighted calculation
As a result it is 0, then generates Clock gating shutdown signal.
In a kind of possible design of second aspect, the shuffle module further include:
Clock control cell, if being clock for selecting time window clock gating signal generated in present clock
Enable signal is gated, then controls the target clock that the clock gating circuit exports in the present clock selection time window and believes
Number；If selecting time window clock gating signal generated for Clock gating shutdown signal in present clock, institute is controlled
State clock gating circuit output low level signal.
Detailed description of the invention
Fig. 1 is a kind of structural schematic diagram of typical SOC system provided by the embodiments of the present application；
Fig. 2 is a kind of design method schematic diagram of the secure clock of existing attack protection provided by the embodiments of the present application；
Fig. 3 is a kind of structural schematic diagram of clock signal generating apparatus provided by the embodiments of the present application；
Fig. 4 is a kind of flow chart of clock signal generation method provided by the embodiments of the present application；
Fig. 5 is the signal schematic representation that a clock signal provided by the embodiments of the present application generates process.
Specific embodiment
To keep the purposes, technical schemes and advantages of the application clearer, below in conjunction with attached drawing to the application embodiment party
Formula is described in further detail.
Fig. 3 is a kind of structural schematic diagram of clock signal generating apparatus provided by the embodiments of the present application.The clock signal produces
Generating apparatus include: stochastic source module (Random Source Module), clock source module (Clock Source Module),
Shuffle module (Random Control Module).Wherein, the of the output end and shuffle module of stochastic source module
One input terminal is connected, and the output end of clock source module is connected with the second input terminal of shuffle module.Wherein, STOCHASTIC CONTROL mould
The first input end of block is used to receive the random number exported from stochastic source module, and the second input terminal of shuffle module is for connecing
Receive the clock signal exported from clock source module.
It is used in addition, the clock signal that the clock signal generating apparatus generates is available to by protective module, it is random to control
The output end of molding block is connected with by the input terminal of protective module.When introducing the clock signal generating apparatus herein, we will be tied
Conjunction is introduced together by protective module.
Each component part of the device is introduced separately below:
Stochastic source module
Stochastic source module has the function of constantly generating random number and export.In actual implementation, which can
To be real physical accidental source, it is also possible to pseudo-random generator.The random number that stochastic source module generates can be by from stochastic source
The output end of module is exported to the input terminal of shuffle module, shuffle module can just receive the random number and to this with
Machine number is handled.
Clock source module
Clock source module has the function of generating clock signal and export.In actual implementation, which can be with
It is oscillator, is also possible to specific component.Wherein, oscillator is a kind of energy conversion device, direct current energy can be converted
For the AC energy with certain frequency.Clock signal is exactly one of AC energy.The specific component can pass through frequency
The clock signal of external certain frequency is carried out frequency-conversion processing by rate varying circuit or frequency conversion device, and is exported and original clock signal
The different clock signal of frequency.
The clock source module can produce multiple clock signals, and each clock signal has different frequencies.The clock source
Multiple clock signals that module generates can be exported from multiple and different ports of the output end of clock source module to shuffle module
Input terminal multiple and different ports.The shuffle module can just receive multiple clock signal and believe multiple clock
The processing such as number selected, deformed.
Shuffle module
Shuffle module, which has, receives the random number that stochastic source module generates and the clock signal that clock source module generates
And to the function that random number, clock signal are handled.
Shuffle module includes but is not limited to three component parts: signal generation unit, clock selecting unit and clock
Control unit.Wherein, the first output end of signal generation unit is connected with the first input end of clock selecting unit, and signal generates
The second output terminal of unit is connected with the first input end of clock control cell, the output end of clock selecting unit and clock control
Second input terminal of unit is connected.And the input terminal of signal generation unit is exactly the first input end of shuffle module, clock
Second input terminal of selecting unit is exactly the second input terminal of shuffle module.
Wherein, the first output end of signal generation unit generates the clock selection signal that unit generates for output signal,
The second output terminal of signal generation unit generates the clock control signal that unit generates for output signal.Clock control cell
First input end is used to receive the clock control signal of signal generation unit output, and the second input terminal of clock control cell is used for
Receive the target clock signal of clock selecting unit output.The first input end of clock selecting unit generates list for receiving signal
The selection of time signal of member output, the second input terminal of clock selecting unit are used to receive multiple clocks of clock source module output
Signal.
Three component parts of shuffle module are introduced respectively below:
(1) signal generation unit, for generating clock selection signal and clock gating signal according to the random number received.
Wherein, clock selection signal is that the random number that will be received is generated as port numbers, and according to the port numbers.Clock
Selection signal is for carrying out signal behavior in the multiple clock signals received.Signal generation unit is by the clock selection signal
It exports from the first output end to clock selecting unit.
Clock gating signal can be divided into Clock gating enable signal and Clock gating closes letter according to the difference of function
Number.Wherein, Clock gating enable signal makes clock gating circuit export the clock signal that the clock gating circuit input terminal inputs,
Clock gating shutdown signal makes clock gating circuit export low level signal.Signal generator module can to receive it is each when
The random number and the corresponding weight of random number of clock selection time window are weighted, if the result of weighted calculation is 1,
Clock gating enable signal is generated, if the result of weighted calculation is 0, generates Clock gating shutdown signal.Signal generates mould
Block exports the clock gating signal to clock control module from second output terminal.
(2) clock selecting unit, for according to clock selection signal from the multiple clock signals received selection target
Clock signal, and export to clock control cell.Wherein, target clock signal is corresponding with the clock selection signal middle-end slogan
The clock signal of port output.In actual implementation, which can be data selector (MUX).MUX is basis
Specified input address code is selected specified one from one group of input signal and is sent to the logic circuit of output end.
(3) clock control cell, for according to clock gating signal control clock gating circuit to target clock signal into
Row processing, and export treated clock signal.
Wherein, clock gating circuit refers to that one kind uses time pulse signal technology in synchronizing sequential circuit, can
Reduce the logic circuit of chip power-consumption.
The clock control cell receives clock control signal according to first input end, to the second input terminal receive when
The processing that clock signal is exported, closed, so that treated that clock signal changes frequency, the appearance of high level for its output
No longer there is regularity.Wherein since clock control signal is signal generation unit according to generating random number, thus clock control
Unit handles also with randomness output, the closing of clock signal.If generated in present clock selection time window
Clock gating signal is Clock gating enable signal, then controls in clock gating circuit output present clock selection time window
Target clock signal；If selecting time window clock gating signal generated to close for Clock gating in present clock to believe
Number, then control clock gating circuit output low level signal.
Finally, by treated, clock signal is exported to by protective module clock control cell.It should treated clock letter
Number there is good randomness, thus by protective module using treated clock signal when will increase the difficulty of analysis,
So as to effective defensive attack.
By protective module
Embodiment as shown in Figure 1, when SOC system is attacked, processor and cryptographic system are main targets of attack,
It is Prevention-Security object to be protected, as by protective module.Due to the clock signal that uses has good randomness can be with
Attack is resisted, to reach protected effect.
Wherein, processor is one piece of ultra-large integrated circuit, is the arithmetic core and control core of an electronic equipment
The heart.Processor mainly includes arithmetic unit (Arithmetic Logic Unit, ALU) and cache memory (Cache) and reality
The bus of the data, control and the state that are now contacted between them.It and internal storage and input-output apparatus are collectively referred to as electronics
The big core component of equipment three.Its function is mainly the data in interpretive machine instruction and processing computer software.
Cryptographic system can have five parts such as message space, the cryptogram space, key space, Encryption Algorithm, decipherment algorithm.
Wherein, the message wait pretend or encrypt (Message) is generally referred to as in plain text.In a communications system, it may be bit stream, such as text
Sheet, bitmap, digitized voice flow or digitized video image etc..It can generally be simply considered that meaningful word in plain text
Symbol or sets of bits, or by certain disclosed coding standard with regard to obtainable message.Ciphertext is to applying certain camouflage in plain text
Or transformed output, it is also believed to the character not directly understood or sets of bits.Key is that one in cryptographic algorithm can
The parameter of change, two kinds of decruption key be divided into the encryption key and decipherment algorithm in Encryption Algorithm.Encryption is original letter
Breath (plaintext) is converted to the information conversion process of ciphertext.Decryption is that the information (ciphertext) encrypted is reverted to raw information is (bright
Text) process, also referred to as DecryptDecryption.Thus, cryptographic system can be encrypted information to guarantee safe transmission, can also be with
The encrypted message received is decrypted, information is obtained.
Fig. 4 is a kind of flow chart of clock signal generation method provided by the embodiments of the present application.In the embodiment of the present application,
Clock selecting unit is represented with MUX, clock gating circuit represents clock control cell.Fig. 5 is provided by the embodiments of the present application one
A clock signal generates the signal schematic representation of process.
Referring to fig. 4 and Fig. 5, the embodiment can specifically include following step:
401, clock source module generates multiple clock signals, and multiple clock signals are sent to shuffle module, often
A clock signal has different frequencies.
Multiple clock signals that clock source module generates are exported from the output end of clock source module, from shuffle module
The second input terminal of MUX be input to MUX.Referring to Fig. 5, multiple clock signals are indicated by CLKA, CLKB.
402, stochastic source module generates random number, and random number is output to shuffle module.
The random number that stochastic source module generates is exported from the output end of stochastic source module, from the signal in shuffle module
The input terminal for generating unit is input to signal generation unit.
It should be noted that above-mentioned 401,402 steps can carry out simultaneously in practice, in no particular order.That is, when
Zhong Yuan generates multiple clock signals, and while multiple clock signals are exported to MUX, stochastic source is also generating random number, and
Random number is exported to signal generation unit.
403, the signal generation unit in shuffle module receives random number and multiple clock signals, and according to random
Number generates clock selection signal and clock gating signal, clock selection signal is sent to MUX, clock gating signal is sent
To clock gating circuit.
Wherein, the algorithm of signal generator module generation clock selection signal is as follows:
Wherein, x is random number.I is the clock count in clock selecting time window.Window_size is clock selecting
Time window, which is the time window of clock selection circuit effect, in the clock selecting time window
Interior, only one clock signal can be selected.Random_data () is random function.
In the beginning of each clock selecting time window (window_size), generated with stochastic source module first with
For machine number x as port numbers, clock selection signal selects the clock signal of the corresponding port output of random number x to select as the clock
Select the target clock in time window.
The algorithm that signal generator module generates clock gating signal is as follows:
Wherein, y is random number.J is the clock count in Clock gating time window.When gating_th is Clock gating
Between window, the Clock gating time window be clock gating circuit effect time window, in the time window, Clock gating
Signal can change according to random number.Clock_enable is the parameter of clock gating signal.Weights () is weight calculation
Function.
Each multiple Clock gating time windows of clock selecting time window packet, in each Clock gating time window
(gating_th) beginning, the first random number y generated using stochastic source module is as weight calculation function wrights's ()
Parameter is inputted, in the Clock gating time window, y is remained unchanged, the parameter (clock_ for the clock gating signal being calculated
Enable it) also remains unchanged.In the clock selecting time window, each Clock gating time window is according to weight calculation function
The parameter (clock_enable) for calculating corresponding clock gating signal can be different.If the parameter of clock gating signal
(clock_enable) it is 1, then generates Clock gating enable signal, if (clock_enable) is 0, generates Clock gating
Shutdown signal.It should be noted that because the parameter of clock gating signal is generated according to random number, after clock gating signal generates
What is presented is random pulse train.
404, MUX selection target clock signal from multiple clock signals, and exporting to clock gating circuit, when the target
Clock signal is clock signal corresponding with clock selection signal.
After MUX receives the clock selection signal of signal generator module output, port is extracted from the clock selection signal
Number, wherein MUX according to the clock signal of the port numbers and port numbers corresponding ports as target clock signal, and should be with end
The clock signal of slogan corresponding ports is exported to clock gating circuit.For example, the port numbers of clock signal clk A shown in fig. 5 are
Port 0, the port numbers of clock signal clk B are port 1.Under some length of window, random number 0, then port numbers are 0, then
The CLKA that selection port 0 inputs is as target clock signal.Under another length of window after some time, random number 1, then
Port numbers are 1, then the CLKB that selection port 1 inputs is as target clock signal.MUX exports target clock signal to clock gate
Control the second input terminal of circuit.
405, clock gating circuit is controlled according to clock gating signal to handle target clock signal, and export processing
Clock signal afterwards.
Clock gating circuit receives the target of the clock gating signal inputted from first input end and the input of the second input terminal
Clock signal, the processing that target clock signal is exported or is closed according to clock gating signal.Referring to Fig. 5, window1
When, the clock selection signal that signal generation unit generates is 0, thus the clock signal selected in current slot is for port numbers
0 clock signal clk A, signal generation unit are 1011001 according to the clock gating signal that random number generates, Clock gating letter
Number be 1 when, export CLKA waveform, clock gating signal be 0 when, export low level, to obtain the clock signal of final output.
Wherein the clock signal of final output is compared to the pulse that clock signal clk A is deducted, practical when to be clock gating signal be 0
Caused by.Similarly, after some time, when window2, the clock selection signal that signal generation unit generates is 1, thus it is current when
Between the clock signal that selects in section be 1 for port numbers clock signal clk B, signal generation unit according to random number generate when
Clock gate-control signal is 1001011, and what the signal of final output was then exported when clock gating signal is 0 is low level, in clock
That gate-control signal exports when being 1 is CLKB.
The embodiment of the present application is special instead of having with pure digi-tal logic circuit compared with existing clock signal generation method
The oscillator and special delay circuit of different oscillation rings, reduce costs；And the Digital Logical Circuits can be directly multiplexed, nothing
It needs to redesign, enhances versatility；And clock source offer is the clock signal of multiple and different frequencies, it is multiple without generating
The clock signal of out of phase, thus timing closure difficulty when reducing by protective module using clock signal.
It should be noted that clock signal generation method and device involved by the application can be applied not only to SOC system
System, can also be applied to any system that may be subjected to the attack based on clock or power consumption analysis, and the application is specific to its
Application environment is without limitation.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, which can store in a kind of computer-readable storage
In medium, storage medium mentioned above can be read-only memory, disk or CD etc..
It above are only the alternative embodiment of the application, it is all in spirit herein and principle not to limit the application
Within, any modification, equivalent replacement, improvement and so on should be included within the scope of protection of this application.
Claims (10)
1. a kind of clock signal generation method, which is characterized in that the described method includes:
Multiple clock signals are generated, each clock signal has different frequencies；
Generate random number；
According to the random number, clock selection signal and clock gating signal are generated, the clock selection signal is used for described
Signal behavior is carried out in multiple clock signals, the clock gating signal is for controlling clock gating circuit；
The selection target clock signal from the multiple clock signal, and exporting to the clock gating circuit, when the target
Clock signal is clock signal corresponding with the clock selection signal；
The clock gating circuit is controlled according to the clock gating signal to handle the target clock signal, and is exported
Clock signal that treated.
2. clock selection signal is generated the method according to claim 1, wherein described according to the random number,
Include:
The clock selection signal is generated according to the port numbers using the random number as port numbers.
3. according to the method described in claim 2, it is characterized in that, the selection target clock from the multiple clock signal
Signal includes:
When selecting the clock signal exported by the port numbers corresponding ports from the multiple clock signal as the target
Clock signal.
4. clock gating signal is generated the method according to claim 1, wherein described according to the random number,
Include:
Random number caused by each clock selecting time window and the corresponding weight of random number are weighted, if plus
The result that power calculates is 1, then generates Clock gating enable signal, if the result of weighted calculation is 0, generates Clock gating pass
Close signal.
5. according to the method described in claim 4, it is characterized in that, described control the clock according to the clock gating signal
Gating circuit carries out processing to the target clock signal
If selecting time window clock gating signal generated for Clock gating enable signal in present clock, institute is controlled
It states clock gating circuit and exports target clock signal in present clock selection time window；
If selecting time window clock gating signal generated for Clock gating shutdown signal in present clock, institute is controlled
State clock gating circuit output low level signal.
6. a kind of clock signal generating apparatus, which is characterized in that described device includes:
Clock source module, for generating multiple clock signals, each clock signal has different frequencies；
Stochastic source module, for generating random number；
Shuffle module, for generating clock selection signal and clock gating signal, the clock choosing according to the random number
It selects signal and is used for for carrying out signal behavior, the clock gating signal in the multiple clock signal to clock gating circuit
It is controlled；The selection target clock signal from the multiple clock signal, and export to the clock gating circuit, the mesh
Mark clock signal is clock signal corresponding with the clock selection signal；The clock is controlled according to the clock gating signal
Gating circuit handles the target clock signal, and exports treated clock signal.
7. device according to claim 6, which is characterized in that the shuffle module includes:
Signal generation unit, for generating the clock selecting letter according to the port numbers using the random number as port numbers
Number.
8. device according to claim 6, which is characterized in that the shuffle module further include:
Clock selecting unit, for selecting the clock exported by the port numbers corresponding ports to believe from the multiple clock signal
Number be used as the target clock signal.
9. device according to claim 6, which is characterized in that the shuffle module further include:
Signal generation unit is also used to random number caused by each clock selecting time window and the corresponding weight of random number
It is weighted, if the result of weighted calculation is 1, Clock gating enable signal is generated, if the result of weighted calculation
It is 0, then generates Clock gating shutdown signal.
10. device according to claim 6, which is characterized in that the shuffle module further include:
Clock control cell, if being Clock gating for selecting time window clock gating signal generated in present clock
Enable signal then controls the clock gating circuit and exports target clock signal in present clock selection time window；
If selecting time window clock gating signal generated for Clock gating shutdown signal in present clock, when controlling described
Clock gating circuit exports low level signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN110022201A (en) * | 2019-05-10 | 2019-07-16 | 上海观源信息科技有限公司 | Bypass attack power consumption profile based on FPGA acquires synchronized clock system |
| CN111624478A (en) * | 2020-06-12 | 2020-09-04 | 山东云海国创云计算装备产业创新中心有限公司 | Clock signal control circuit and equipment |
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