CN109244121A - Ertical tunneling field effect transistor with grid field plate structure - Google Patents
Ertical tunneling field effect transistor with grid field plate structure Download PDFInfo
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- 239000000758 substrate Substances 0.000 claims description 24
- 239000000463 material Substances 0.000 claims description 16
- 239000002184 metal Substances 0.000 claims description 9
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- 230000007547 defect Effects 0.000 abstract description 2
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/739—Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
- H01L29/7391—Gated diode structures
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- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
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- H01L29/66356—Gated diodes, e.g. field controlled diodes [FCD], static induction thyristors [SITh], field controlled thyristors [FCTh]
Abstract
The present invention relates to semiconductor device arts, will cause off-state leakage current such as the purpose of the present invention is overcoming the problems, such as current TFET device when promoting on-state current increased defect or causes device frequency characteristic to fail therewith, provide a kind of ertical tunneling field effect transistor with grid field plate structure, its technical solution can be summarized as: grid field plate dielectric area and grid field plate electrode are increased on the basis of existing ertical tunneling field effect transistor, grid field plate dielectric area is set to above intrinsic region, and it is in contact with the upper surface of intrinsic region, its thickness is more than or equal to the thickness of gate oxide, side is in contact with the side of the side of gate oxide and gate electrode, grid field plate electrode is arranged on grid field plate dielectric area, and it is in contact with the upper surface of grid field plate dielectric area, the side of grid field plate electrode is in contact with the side of gate electrode.The invention has the advantages that on-state current increases and obtain simultaneously lower average subthreshold swing, it is suitable for tunneling field-effect transistor.
Description
Technical field
The invention belongs to field of semiconductor devices, and in particular to tunneling field-effect transistor (TFET, Tunneling
FieldEffect Transistor) technology.
Background technique
With the continuous reduction of MOSFET size in integrated circuit, short-channel effect caused by small size, high electric field, leakage is lured
Growing situation, which is built, to be reduced and hot carrier's effect causes device performance significantly to be degenerated；Importantly, being determined by hot carrier in jection mechanism
The subthreshold swing (SS) of fixed MOSFET can not be lower than 60mV/dec, cause biggish OFF state leakage power supply.Disadvantages mentioned above is made
Serious difficulty is encountered when size further reduces at MOSFET, researcher is actively finding other new principle devices
To replace application of the MOSFET in large scale integrated circuit.TEFT based on band-to-band-tunneling principle has more compared to MOSFET
Low off-state current, smaller subthreshold swing, and it is mutually compatible with traditional cmos process, thus become following and be most hopeful to take
For the device of MOSFET.
Typical tunneling field-effect transistor is substantially the grid-control P- based on metals-oxides-semiconductor structure
I-N diode belongs to lateral tunneling field effect transistor (LTFET), and structure is as shown in Figure 1, include semiconductor substrate 1, source
Area 2, intrinsic region 3, drain region 4, gate oxide 6 and gate electrode 7, wherein source region 2, intrinsic region 3 and drain region 4 are separately positioned on and partly lead
The top of body substrate 1, and be in contact respectively with the upper surface of semiconductor substrate 1, the side phase of the side and intrinsic region 3 of source region 2
Contact, the other side of intrinsic region 3 are in contact with the side in drain region 4, and gate oxide 6 is covered on the upper surface of intrinsic region 3, gate electrode
7 are arranged in the top of gate oxide 6, and are in contact with the upper surface of gate oxide 6.By taking N-type TFET as an example, when gate electrode bias
When being zero, P-I-N diode is reverse-biased, only has the reverse saturation current of very little to flow through between source region 2 and drain region 4；When gate electrode is applied
When adding biggish positive voltage, 3 energy band of intrinsic region is moved down, and potential barrier increases between source region 2 and intrinsic region 3, if source region divalent band is higher than this
3 conduction band of area is levied, then electronics can be tunneling to 3 conduction band of intrinsic region from source region divalent band, and then drift about under the high electric field of intrinsic region 3
To drain region 4, biggish drain-source current is generated.
Happens is that point tunnelling, i.e. tunnelling only occur in source region and intrinsic region interface in lateral tunneling field effect transistor
At (contact zone) in the very little region of gate oxide interface, due to tunnelling region area very little lead to not obtain it is biggish
On-state current.In order to improve on-state current, researcher proposes a variety of solutions.
Method first is that tunnel region use low bandgap material, such as GeSi (germanium-silicon alloy).Low bandgap material can have significantly
Low tunneling barrier improves on-state current to increase tunnelling probability.But intrinsic carrier concentration is higher after the band gap of material narrows,
Off-state leakage current increases therewith.
Another method is tunneling field-effect transistor (VTFET, the longitudinal tunneling field-effect crystal using vertical structure
Pipe), structure is as shown in Fig. 2, include semiconductor substrate 1, source region 2, intrinsic region 3, drain region 4, epitaxial region 5, gate oxide 6 and grid
Electrode 7, wherein source region 2, intrinsic region 3 and drain region 4 are separately positioned on the top of semiconductor substrate 1, and respectively with semiconductor substrate
1 upper surface is in contact, and the side of source region 2 is in contact with the side of intrinsic region 3, the other side of intrinsic region 3 and the side in drain region 4
It is in contact, the top of source region 2 is arranged in epitaxial region 5, and is in contact with the upper surface of source region 2, the side and intrinsic region of epitaxial region 5
3 are in contact, if length of the epitaxial region 5 from the side being in contact with intrinsic region 3 to the other side be its lateral length, source region 2 from
The length of the side that intrinsic region 3 is in contact to the other side is its lateral length, then the lateral length of epitaxial region 5 is less than source region 2
The upper surface of lateral length, epitaxial region 5 is flushed with the upper surface of intrinsic region 3 and drain region 4, and gate oxide 6 is covered on epitaxial region 5
Upper surface, the top of gate oxide 6 is arranged in gate electrode 7, and is in contact with the upper surface of gate oxide 6.In this configuration,
Asymmetrical source region 2 and 4 junction area of drain region and relatively low 4 doping concentration of drain region can effectively inhibit bipolar conduction.Grid voltage
The source region 2 covered in vertical direction by grid occurs for the tunnelling of control, and (i.e. source region 2 is in contact with epitaxial region 5 with 5 interface of epitaxial region
Region), and thin 5 thickness of epitaxial region can effectively reduce tunneling distance, significantly improve on-state current and reduce subthreshold swing.This
Happens is that threaded list is worn in kind structure, i.e., the area in tunnelling region is directly proportional to the size of grid for covering it, passes through and increases covering
On-state current can be improved in length, but also increases gate-source capacitance simultaneously, and device frequency characteristic is caused to fail.
Summary of the invention
The purpose of the present invention is overcome current TFET device will cause when promoting on-state current as off-state leakage current with
Increased defect or cause device frequency characteristic fail the problem of, a kind of longitudinal tunneling field-effect with grid field plate structure is provided
Transistor.
The present invention solves its technical problem, the technical solution adopted is that, longitudinal tunneling field-effect with grid field plate structure is brilliant
Body pipe, including semiconductor substrate, source region, intrinsic region, drain region, epitaxial region, gate oxide and gate electrode, which is characterized in that also wrap
Grid field plate dielectric area and grid field plate electrode are included, grid field plate dielectric area is set to above intrinsic region, and the upper table with intrinsic region
Face is in contact, and thickness is more than or equal to the thickness of gate oxide, and side connects with the side of the side of gate oxide and gate electrode
Touching, the setting of grid field plate electrode are in contact on grid field plate dielectric area, and with the upper surface of grid field plate dielectric area, grid field plate electrode
Side is in contact with the side of gate electrode.
Specifically, the thickness of grid field plate dielectric area is not more than 30nm.According to the simulation experiment result, grid field plate dielectric area
Thickness to cross conference invalid, thus select a preferably range.
Further, when gate electrode is greater than 60nm from the length for contacting that side to the other side with grid field plate electrode, root
According to electrode material in the prior art, then the material of gate electrode and grid field plate electrode is metal or polysilicon or silicide, conversely,
To avoid grid-control reduced capability caused by depletion of polysilicon, then the material of gate electrode and grid field plate electrode is metal.
Specifically, when the material of gate electrode and grid field plate electrode is metal, the metal material respectively used it is identical or
It is different.It selects identical or different metal material to will not influence overall effect, the range of choice of metal material can be increased in this way.
Further, when gate electrode is not more than 60nm from the length for contacting that side to the other side with grid field plate electrode
When, the gate oxide uses high K dielectric, and relative dielectric constant is greater than 20.
Specifically, the relative dielectric constant range of the grid field plate medium is 6~14.
Further, when gate electrode is not more than 60nm from the length for contacting that side to the other side with grid field plate electrode
When, the gate-oxide thicknesses be less than 10nm, the epitaxial region thickness be not more than 10nm, the intrinsic region from source contact that
Side to the length range with that side of drain contact is 10nm~30nm.
Specifically, when the ertical tunneling field effect transistor with grid field plate structure is N-type longitudinal direction tunneling field-effect crystal
Guan Shi, source region are p-type doping, and drain region is n-type doping；
When the ertical tunneling field effect transistor with grid field plate structure is p-type ertical tunneling field effect transistor, source
Area is n-type doping, and drain region is p-type doping.
Further, the source region and the doping concentration range in drain region are 1 × 1017~1 × 1019cm-3, and source region is mixed
Miscellaneous concentration is greater than drain region doping concentration.
Specifically, the epitaxial region is adulterated using n-type doping or p-type, doping concentration is less than 1 × 1017cm-3；Described
It levies area to adulterate using n-type doping or p-type, doping concentration is less than 1 × 1017cm-3。
The invention has the advantages that the above-mentioned ertical tunneling field effect transistor with grid field plate structure, vertical using it as N-type
To for tunneling field-effect transistor, in OFF state or smaller grid voltage, due to intrinsic region carrier concentration very little, additional source and drain
Voltage mainly drops to intrinsic region, and tunnel junctions institute differential pressure drop very little；In ON state or larger grid voltage, in the control of grid field plate
Under, intrinsic region carrier concentration is significantly increased because of band curvature below, and in intrinsic region, pressure drop becomes smaller additional source-drain voltage
And partial pressure becomes larger in tunnel junctions, tunneling junction field enhancing, on-state current increases and obtains lower average subthreshold swing simultaneously.
On the other hand, the interface in source and intrinsic section also becomes the tunnelling controlled by grid voltage because of being covered by field plate in transverse direction
Knot, additional contribution on-state current.In addition, the introducing of grid field plate improves the field distribution on intrinsic region top, make field distribution more
Add uniformly, generates peak electric field in intrinsic region in application, can be avoided as large-size device in the device so as to cause breakdown
Generation.
Detailed description of the invention
Fig. 1 is lateral tunneling field effect transistor sectional view in the prior art；
Fig. 2 is ertical tunneling field effect transistor sectional view in the prior art；
Fig. 3 is the ertical tunneling field effect transistor sectional view with grid field plate structure in the present invention；
Fig. 4 is the ertical tunneling field effect transistor with grid field plate structure and common longitudinal tunnelling in the embodiment of the present invention 1
The field distribution schematic diagram of intrinsic region 3 midline position of the field effect transistor in Vgs=1.5V and Vds=1.0V；
Fig. 5 is the ertical tunneling field effect transistor with grid field plate structure and common longitudinal tunnelling in the embodiment of the present invention 1
Transfer characteristic curve schematic diagram of the field effect transistor in Vds=1.0V；
Fig. 6 is the ertical tunneling field effect transistor with grid field plate structure and common longitudinal tunnelling in the embodiment of the present invention 1
Output characteristic curve schematic diagram of the field effect transistor in Vgs=1.5V；
Fig. 7 is to be cutd open in the embodiment of the present invention 3 using the ertical tunneling field effect transistor with grid field plate structure of SOI substrate
Face figure；
Wherein, 1 is semiconductor substrate, and 2 be source region, and 3 be intrinsic region, and 4 be drain region, and 5 be epitaxial region, and 6 be gate oxide, 7
It is grid field plate dielectric area for gate electrode, 8,9 be grid field plate electrode, and 10 be buried oxide layer, and A curve is referred to grid field plate structure
Ertical tunneling field effect transistor, B curve refer to the common ertical tunneling field effect transistor without grid field plate structure.
Specific embodiment
With reference to the accompanying drawings and embodiments, the technical schemes of the invention are described in detail.
Ertical tunneling field effect transistor with grid field plate structure of the invention, sectional view is referring to Fig. 3, including semiconductor
Substrate 1, source region 2, intrinsic region 3, drain region 4, epitaxial region 5, gate oxide 6, gate electrode 7, grid field plate dielectric area 8 and grid field plate electrode
9, wherein be to increase grid field plate dielectric area 8 and grid field plate electricity with the place of prior art ertical tunneling field effect transistor
Pole 9, grid field plate dielectric area 8 is set to 3 top of intrinsic region, and is in contact with the upper surface of intrinsic region 3, and thickness is more than or equal to grid
The thickness of oxide 6, side are in contact with the side of the side of gate oxide 6 and gate electrode 7, and grid field plate electrode 9 is arranged in grid
On field plate dielectric area 8, and it is in contact with the upper surface of grid field plate dielectric area 8, the side of grid field plate electrode 9 and the one of gate electrode 7
Side is in contact.
By taking it is N-type ertical tunneling field effect transistor as an example, in OFF state or smaller grid voltage, due to 3 current-carrying of intrinsic region
Sub- concentration very little, additional source-drain voltage mainly drop to intrinsic region 3, and tunnel junctions institute differential pressure drop very little；In ON state or grid voltage
When larger, under the control of grid field plate (grid field plate dielectric area 8 and grid field plate electrode 9), below 3 carrier concentration of intrinsic region because
Band curvature and be significantly increased, additional source-drain voltage 3 pressure drop of intrinsic region become smaller and in tunnel junctions partial pressure become larger, tunnel junctions electricity
Field enhancing, on-state current increase and obtain lower average subthreshold swing simultaneously.On the other hand, in transverse direction source region 2 with
Interface (region that source region 2 is in contact with intrinsic region 3) between intrinsic region 3 is also because by grid field plate (grid field plate dielectric area 8 and grid field
Plate electrode 9) it covers and becomes the tunnel junctions controlled by grid voltage, additional contribution on-state current.
And according to side-wall technique, i.e., using high K dielectric production side wall replace above-mentioned grid field plate (grid field plate dielectric area 8 and
Grid field plate electrode 9), then can have FIBL (Fringing-induced barrier lowering) effect, here, FIBL
(Fringing-induced barrier lowering) effect refers to: if dielectric constant changes when power line passes through material
Become the change that will cause the density of electric fluxline (namely electric field), this is basic electromagnetic common sense, general high dielectric constant material meeting
It causes surrounding electric field to concentrate, is exactly the semiconductor regions electric field increase that grid two is surveyed for FET device, to cause
Device performance changes, and here it is FIBL effects.
Compared to side wall use high K dielectric scheme, the present invention in grid field plate (grid field plate dielectric area 8 and grid field plate electrode
9) covering drain region 4 is not needed to eliminate FIBL (Fringing-induced barrier brought by enhancing electric field
Lowering) effect, therefore reduce the influence of gate-drain parasitic capacitances, this is because grid field plate (grid field plate dielectric area 8 and grid field plate
Electrode 9) structure is considered as grid 7 (including the gate oxide 6 and epitaxial region 5 under it) to a certain extent and extends to the right, therefore
The uneven of electric field has been mitigated, has been laterally that there are tunnellings can in structure especially of the invention so reduce the influence of FIBL
Energy property, the simple side wall of ratio of elongation preferably enhances grid to grid 7 (including the gate oxide 6 and epitaxial region 5 under it) to the right
Control ability, thus FIBL effect is inhibited.In addition, the introducing of grid field plate improves the field distribution on intrinsic region top, make electricity
Field distribution is more uniform, in the device as large-size device (when gate electrode is from that side is contacted with grid field plate electrode to another
When the length of side is greater than 60nm) in application, can be avoided the generation in intrinsic region generation peak electric field so as to cause breakdown.
Here, the thickness of grid field plate dielectric area 8 is preferably not greater than 30nm.According to the simulation experiment result, grid field plate medium
It is invalid that the thickness in area 8 crosses conference, thus selects a preferably range.
When gate electrode 7 is greater than 60nm from the length for contacting that side to the other side with grid field plate electrode 9, according to existing skill
Electrode material in art, then the material of gate electrode 7 and grid field plate electrode 9 can be metal or polysilicon or silicide, conversely, being
Grid-control reduced capability caused by depletion of polysilicon is avoided, then the material of gate electrode 7 and grid field plate electrode 9 is preferably metal.
When the material of gate electrode 7 and grid field plate electrode 9 is metal, the metal material that respectively uses can it is identical can also
With difference.It selects identical or different metal material to will not influence overall effect, the selection model of metal material can be increased in this way
It encloses.
(the i.e. small size when gate electrode 7 is not more than 60nm from the length for contacting that side to the other side with grid field plate electrode 9
Device), gate oxide 6 preferably uses high K dielectric, and relative dielectric constant is greater than 20.This is because: in order to improve grid (grid
7, gate oxide 6 and epitaxial region 5) to the control ability of channel current it is necessary to keep 6 thickness of gate oxide the smaller the better, existing skill
It requires 6 thickness of gate oxide very thin if gate oxide 6 uses low-k in art, will occur in this case straight
Tunnelling is connect, grid leak electricity increases, while it is difficult to ensure that the quality of gate oxide 6 is grown, if using the gate oxidation of high dielectric constant instead
Object 6, when reaching same grid-control ability, the thickness of gate oxide 6 can be thicker, so that grid leak electricity is effectively reduced, therefore this
In preferably 20.
The relative dielectric constant of grid field plate medium 8 ranges preferably from 6~14.This is because: if grid field plate 8 dielectrics of medium are normal
Number is too small to will lead to that grid-control ability is poor, and electric current is lower, causes subthreshold swing to increase when dielectric constant is very big, switching characteristic
It is deteriorated, therefore is here preferably 6~14.
(the i.e. small size when gate electrode 7 is not more than 60nm from the length for contacting that side to the other side with grid field plate electrode 9
Device), 6 thickness of gate oxide is preferably less than 10nm, this is because 6 thickness of gate oxide should be as far as possible in the prior art
It is small, but cannot be too small, thus preferably less than 10nm, 5 thickness of epitaxial region are not more than 10nm, this is because 5 thickness of epitaxial region
Should be the smaller the better, smaller grid (gate electrode 7 and gate oxide 6) are stronger to the control action of 5 potential of epitaxial region, but in practice
It is difficult to accomplish very thin and very low-doped epitaxial layer, therefore preferably not greater than 10nm, intrinsic region 3 connects from source region 2
Touching that side to the length range that contacts that side with drain region 4 is preferably 10nm~30nm, this is because if 3 length of intrinsic region too
Small that tunnelling will occur when grid voltage is 0, grid (gate electrode 7 and gate oxide 6) lose completely acts on current control, intrinsic region
3 length too high current is not obviously improved, and gate capacitance dramatically increases, and frequency characteristic is caused to be deteriorated, while device area becomes
Very big, in technical field of semiconductors, it is eternal theme that individual devices size, which constantly reduces, thus preferably 10nm~30nm.
When the ertical tunneling field effect transistor with grid field plate structure is N-type ertical tunneling field effect transistor, source
Area 2 is p-type doping, and drain region 4 is n-type doping；When the ertical tunneling field effect transistor with grid field plate structure is p-type longitudinal direction tunnel
When wearing field effect transistor, source region 2 is n-type doping, and drain region 4 is p-type doping.This is technology more mature in the prior art,
And will not be described here in detail.
Source region 2 and the doping concentration range in drain region 4 are preferably 1 × 1017~1 × 1019cm-3, and 2 doping concentration of source region is big
In 4 doping concentration of drain region.This is because: tunnelling occurs in source region 2, source region 2 is highly doped to be conducive to improve tunnelling probability increase electricity
Stream, and leak doping concentration increase and will lead to that OFF state electric leakage is promoted and bipolar conduction phenomenon is more significant, therefore source region 2 wants highly doped
Miscellaneous, drain region 4 wants doping concentration slightly lower, but cannot be too low, too low that drain series resistance is caused to become larger, thus preferably 1
×1017~1 × 1019cm-3, and 2 doping concentration of source region is greater than 4 doping concentration of drain region.
Epitaxial region 5 is adulterated using n-type doping or p-type, and doping concentration is preferably less than 1 × 1017cm-3；It adopts intrinsic region 3
It is adulterated with n-type doping or p-type, doping concentration is preferably less than 1 × 1017cm-3.This is because: epitaxial region 5 and intrinsic region 2 are wanted
Ask essentially the same, theoretically require the two region dopant concentrations very low, but control in practice it is low-doped difficult, thus
Preferably doping concentration is less than 1 × 1017cm-3, but according to simulation result, the two region dopant concentrations are slightly bigger to property
It can not have much affect.
Embodiment 1
The ertical tunneling field effect transistor with grid field plate structure in the embodiment of the present invention 1, cross-sectional view referring to Fig. 3,
Including semiconductor substrate 1, source region 2, intrinsic region 3, drain region 4, epitaxial region 5, gate oxide 6, gate electrode 7, grid field plate dielectric area 8 and
Grid field plate electrode 9, by taking the N-type TFET being produced in P type substrate as an example.
Its production process is as follows: carrying out ion implanting in corresponding region on P-type semiconductor substrate 1 first, is formed highly doped
Miscellaneous p-type source region 2；Then the thin epitaxial layer 5 that epitaxial growth p-type is lightly doped is carried out, then carries out primary ions injection, is formed highly doped
Miscellaneous N-type drain region 5；Gate oxide 6 and grid are grown above epitaxial region 5 and intrinsic region 3 respectively according still further to conventional semiconductor process
Field plate medium 8, finally deposition of electrode material forms gate electrode 7 and grid field plate electrode 9 respectively.
The ertical tunneling field effect transistor with grid field plate structure that the present embodiment obtains, source region 2 length (with it is intrinsic
The length for that side to the other side that area 3 is in contact) it is 60nm, with a thickness of 30nm, doping concentration is 1 × 1020cm-3, drain region 4
Length (length for that side to the other side being in contact with intrinsic region 3) be 20nm, thickness 35nm, doping concentration be 1 ×
1018cm-3, 3 length of intrinsic region (that side being in contact with source region 2 to the length of that side being in contact with drain region 3) is
20nm, thickness 35nm, doping concentration are 1 × 1015cm-3, (that side being in contact with intrinsic region 3 is to another for the length of epitaxial region 5
The length of side) it is 40nm, thickness 5nm, doping concentration is 1 × 1015cm-3, gate oxide 6 and 8 thickness of grid field plate medium are
5nm, gate oxide 6 use HfO2, and dielectric constant 22, grid field plate medium 8 is using Si3N4, dielectric constant 7.5,
The field distribution of 5 midline position of epitaxial region when gate source voltage Vgs=1.5V, drain-source voltage Vds=1.0V as shown in figure 4, with
There is no the ertical tunneling field effect transistor of grid field plate (grid field plate dielectric area 8 and grid field plate electrode 9) to compare, increases grid field plate
(grid field plate dielectric area 8 and grid field plate electrode 9) electric field of epitaxial region 5 significantly increases afterwards, while the electric field of 3 upper surface of intrinsic region point
Cloth is also adjusted, and the presence of electric field paddy and electric field peak is eliminated.Its transfer characteristic curve in drain-source voltage Vds=1.0V
As shown in figure 5, relative to the tunneling field-effect transistor without grid field plate (grid field plate dielectric area 8 and grid field plate electrode 9) structure
Its driving capability is obviously improved.It is in gate source voltage Vgs=1.5V output characteristic curve as shown in fig. 6, due to grid field plate (grid field
Plate dielectric area 8 and grid field plate electrode 9) introducing, 3 carrier concentration of intrinsic region significantly improves under larger grid voltage, identical drain-source
Leakage current is obviously improved under voltage.A curve in Fig. 4, Fig. 5, Fig. 6 all refers to the crystalline substance of longitudinal tunneling field-effect with grid field plate structure
Body pipe, B curve all refer to the common ertical tunneling field effect transistor without grid field plate structure.
Embodiment 2
The ertical tunneling field effect transistor with grid field plate structure in the embodiment of the present invention 2, cross-sectional view referring to Fig. 3,
By taking the N-type TFET being produced in P type substrate as an example.Itself the difference from embodiment 1 is that: epitaxial region 5 in embodiment 2 is using narrow
The germanium silicon material of band gap, to improve the electron tunneling probability at tunnel junctions；Meanwhile being clipped in the sheet between epitaxial region 5 and drain region 4
The intrinsic silicon material still relatively wide using band gap of area 3 is levied, it can be with bipolar conduction phenomenon (the i.e. N-type TFET grid of suppression device
Enough negative voltage is filled up in pole can also make break-over of device) and reduction OFF state electric leakage.By different from the use of intrinsic region 3 in epitaxial region 5
Band gap material can improve the on-state characteristic and OFF state characteristic of device simultaneously.
And on its production method the difference from embodiment 1 is that: to guarantee 5 upper surface of epitaxial region and intrinsic region 3 and drain region 4
Upper surface is concordant, and epitaxial step needs to carry out in two times, i.e., grows thin layer germanium silicon material on entire 1 surface of semiconductor substrate first
Material, then etches away the germanium silicon material of 4 upper surface of intrinsic region 3 and drain region, identical as epitaxial growth above drain region 4 in intrinsic region 3
The intrinsic silicon material of thickness finally carries out one-time surface planarizing process.
Embodiment 3
The ertical tunneling field effect transistor with grid field plate structure in the embodiment of the present invention 3, cross-sectional view referring to Fig. 7,
By taking the N-type TFET being produced in P type substrate as an example, including semiconductor substrate 1, source region 2, intrinsic region 3, drain region 4, epitaxial region 5, grid
Oxide 6, gate electrode 7, grid field plate medium 8, grid field plate electrode 9, buried oxide layer 10.
Itself the difference from embodiment 1 is that: semiconductor substrate 1 in embodiment 3 is SOI substrate (including semiconductor substrate 1
And buried oxide layer 10 thereon), it is consistent in production process and embodiment 1.
Source and drain has been blocked using SOI substrate (buried oxide layer 10 including semiconductor substrate 1 and thereon) in the present embodiment
Between by the current leakage paths of substrate, thus off-state leakage current can be effectively reduced.
Claims (10)
1. the ertical tunneling field effect transistor with grid field plate structure, including semiconductor substrate, source region, intrinsic region, drain region, extension
Area, gate oxide and gate electrode, which is characterized in that further include grid field plate dielectric area and grid field plate electrode, the grid field plate medium
Area is set to above intrinsic region, and is in contact with the upper surface of intrinsic region, and thickness is more than or equal to the thickness of gate oxide, side
Be in contact with the side of the side of gate oxide and gate electrode, grid field plate electrode be arranged on grid field plate dielectric area, and with grid field
The upper surface of plate dielectric area is in contact, and the side of grid field plate electrode is in contact with the side of gate electrode.
2. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that the grid field
The thickness of plate dielectric area is not more than 30nm.
3. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that work as gate electrode
When being greater than 60nm from the length for contacting that side to the other side with grid field plate electrode, then the material of gate electrode and grid field plate electrode is
Metal or polysilicon or silicide, conversely, then the material of gate electrode and grid field plate electrode is metal.
4. the ertical tunneling field effect transistor as claimed in claim 3 with grid field plate structure, which is characterized in that work as gate electrode
When material with grid field plate electrode is metal, the metal material respectively used is identical or different.
5. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that work as gate electrode
From when contacting the length of that side to the other side with grid field plate electrode no more than 60nm, the gate oxide uses high K dielectric,
Relative dielectric constant is greater than 20.
6. the ertical tunneling field effect transistor as claimed in claim 5 with grid field plate structure, which is characterized in that the grid field
The relative dielectric constant range of plate medium is 6~14.
7. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that work as gate electrode
From when contacting the length of that side to the other side with grid field plate electrode no more than 60nm, the gate-oxide thicknesses are less than 10nm,
The epitaxial region thickness be not more than 10nm, the intrinsic region from that side of source contact to the length with that side of drain contact
Range is 10nm~30nm.
8. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that when the band grid
When the ertical tunneling field effect transistor of field plate structure is N-type ertical tunneling field effect transistor, source region is p-type doping, drain region
For n-type doping；
When the ertical tunneling field effect transistor with grid field plate structure is p-type ertical tunneling field effect transistor, source region N
Type doping, drain region are p-type doping.
9. the ertical tunneling field effect transistor as described in claim 1 with grid field plate structure, which is characterized in that the source region
And the doping concentration range in drain region is 1 × 1017~1 × 1019cm-3, and source region doping concentration is greater than drain region doping concentration.
10. such as the described in any item ertical tunneling field effect transistors with grid field plate structure of claim 1-9, feature exists
In the epitaxial region is adulterated using n-type doping or p-type, and doping concentration is less than 1 × 1017cm-3；The intrinsic region uses N-type
Doping or p-type doping, doping concentration is less than 1 × 1017cm-3。
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