CN109244034A - The method for avoiding leading to metal medium fault rupture when chip package routing - Google Patents
The method for avoiding leading to metal medium fault rupture when chip package routing Download PDFInfo
- Publication number
- CN109244034A CN109244034A CN201810959822.0A CN201810959822A CN109244034A CN 109244034 A CN109244034 A CN 109244034A CN 201810959822 A CN201810959822 A CN 201810959822A CN 109244034 A CN109244034 A CN 109244034A
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- layer
- metal layer
- dielectric layer
- hole via
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/528—Geometry or layout of the interconnection structure
- H01L23/5283—Cross-sectional geometry
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Geometry (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of methods for avoiding leading to metal medium fault rupture when chip package routing, comprising: 1) in metal layer M1Dielectric layer IMD1Middle production through-hole Via1With pseudo- through-hole Via1'；2) in dielectric layer IMD1Upper deposited metal layer M, then in the dielectric layer IMD of metal layer M2Middle production through-hole Via2With pseudo- through-hole Via2'；3) in dielectric layer IMD2Upper deposited metal layer Mx, then in the dielectric layer TIMD- of metal layer Mx1Middle production through-hole TVia-1；4) in dielectric layer TIMD-1Upper deposited metal layer TM-1, then in metal layer TM-1Dielectric layer TIMD in make through-hole Tvia1；5) then the deposited metal layer TM on dielectric layer TIMD, the deposit passivation layer on metal layer TM etch pad on the passivation layer.The generation of the situation of metal medium fault rupture when this method can be effectively prevented from chip package routing.
Description
Technical field
The present invention relates to chip package fields, and in particular, to one kind avoids leading to metal medium when chip package routing
The method of fault rupture.
Background technique
In integrated circuit booming today, the yield for how improving product becomes the emphasis of chip maker research,
But when packaged caused by chip damage be also can not ignore, such as: when packaged the power of routing will lead to inside and connect
The damage of line, most directly effective method be reduce routing power, but will lead in this way encapsulation outer lead cannot well or
It firmly connects and yield is caused to reduce.
Summary of the invention
The object of the present invention is to provide a kind of method for avoiding leading to metal medium fault rupture when chip package routing, the party
Metal medium fault rupture when method can be effectively prevented from chip package routing in the case where not requiring connection wire lengths
The generation of situation.
To achieve the goals above, it avoids leading to metal medium fault rupture when chip package routing the present invention provides one kind
Method, comprising:
1) in metal layer M1Dielectric layer IMD1Middle production through-hole Via1With pseudo- through-hole Via1'；
2) in dielectric layer IMD1Upper deposited metal layer M, then in the dielectric layer IMD of metal layer M2Middle production through-hole Via2With
Pseudo- through-hole Via2'；
3) in dielectric layer IMD2Upper deposited metal layer Mx, then in the dielectric layer TIMD- of metal layer Mx1Middle production through-hole
TVia-1；
4) in dielectric layer TIMD-1Upper deposited metal layer TM-1, then in metal layer TM-1Dielectric layer TIMD in production it is logical
Hole Tvia1；
5) then the deposited metal layer TM on dielectric layer TIMD, the deposit passivation layer on metal layer TM are carved on the passivation layer
Lose pad.
Preferably, through-hole Via1With pseudo- through-hole Via1' transpostion interval setting.
Preferably, through-hole Via2With pseudo- through-hole Via2' transpostion interval setting.
Preferably, passivation layer is aluminum passivation layer.
Preferably, outer linkage lines are connected on pad.
Preferably, the distance between adjacent through-holes and the size of weld pad are consistent.
Preferably, weld pad is aluminium welding pad.
In the above-mentioned technical solutions, the side provided by the invention for avoiding leading to metal medium fault rupture when chip package routing
The principle for power that method is reduced using tension with distance and honeycomb disappears, in dielectric layer IMD1, dielectric layer IMD2, dielectric layer TIMD-1, be situated between
Matter layer TIMD is arranged through-hole or pseudo- through-hole and then connects metal layer M1, metal layer M2, metal layer Mx, metal layer TM-1, metal layer
TM so that the tension between metal layer and dielectric layer reduces, and avoid routing power (direction of routing power be self-passivation layer to
Metal layer M11 top-down direction) it is damaged caused by dielectric layer；Wherein, pseudo- through-hole Via1', pseudo- through-hole Via2' it is not join
With conduction, main function is the plane strain for eliminating this layer of dielectric layer.
Other features and advantages of the present invention will the following detailed description will be given in the detailed implementation section.
Detailed description of the invention
The drawings are intended to provide a further understanding of the invention, and constitutes part of specification, with following tool
Body embodiment is used to explain the present invention together, but is not construed as limiting the invention.In the accompanying drawings:
Fig. 1 is the principle signal of the method provided by the invention for avoiding causing when chip package routing metal medium fault rupture
Figure.
Description of symbols
1, metal layer M12, metal layer M2
3, metal layer Mx 4, metal layer TM-1
5, metal layer TM 6, passivation layer
7, through-hole Via18, pseudo- through-hole Via1’
9, through-hole Via210, pseudo- through-hole Via2’
11, through-hole TVia-112, through-hole Tvia1
Specific embodiment
Below in conjunction with attached drawing, detailed description of the preferred embodiments.It should be understood that this place is retouched
The specific embodiment stated is merely to illustrate and explain the present invention, and is not intended to restrict the invention.
In the present invention, in the absence of explanation to the contrary, the noun of locality that " upper and lower " etc. is included in the term only represents
Orientation of the term under normal service condition, or be those skilled in the art understand that be commonly called as, and be not construed as to the term
Limitation.
The present invention provides a kind of methods for avoiding leading to metal medium fault rupture when chip package routing, as shown in Figure 1,
Include:
1) in metal layer M11 dielectric layer IMD1Middle production through-hole Via17 and pseudo- through-hole Via1'8；
2) in dielectric layer IMD1Upper deposited metal layer M22, then in metal layer M22 dielectric layer IMD2Middle production through-hole
Via29 and pseudo- through-hole Via2'10；
3) in dielectric layer IMD2Upper deposited metal layer Mx3, then in the dielectric layer TIMD- of metal layer Mx31Middle production through-hole
TVia-111；
4) in dielectric layer TIMD-1Upper deposited metal layer TM-14, then in metal layer TM-1It is made in 4 dielectric layer TIMD
Through-hole Tvia112；
5) the deposited metal layer TM5 on dielectric layer TIMD, the deposit passivation layer 6 on metal layer TM5, then in passivation layer 6
Upper etching pad.
The above-mentioned method for avoiding causing when chip package routing metal medium fault rupture is reduced using tension with distance
The principle for the power that disappears with honeycomb, in dielectric layer IMD1, dielectric layer IMD2, dielectric layer TIMD-1, dielectric layer TIMD setting through-hole or puppet
Through-hole and then connection metal layer M11, metal layer M22, metal layer Mx3, metal layer TM-14, metal layer TM5, so that metal layer
Tension between dielectric layer reduces, and avoids routing power (direction of routing power is self-passivation layer 6 to metal layer M11 from upper and
Under direction) damaged caused by dielectric layer；Wherein, pseudo- through-hole Via1' 8, pseudo- through-hole Via2' 10 are not involved in conduction, master
Acting on is the plane strain for eliminating this layer of dielectric layer.
In the present invention, through-hole Via17 and pseudo- through-hole Via1The positional relationship and distribution density of ' 8 can be in wide ranges
Interior selection, but in order to further increase through-hole Via17 and pseudo- through-hole Via1' 8 are in the plane strain and medium for eliminating dielectric layer
Tension between layer and metal layer, it is preferable that through-hole Via17 and pseudo- through-hole Via1The setting of the transpostion interval of ' 8.
Similarly, in the present invention, through-hole Via29 and pseudo- through-hole Via2The positional relationship and distribution density of ' 10 can be in width
In the range of select, but in order to further increase through-hole Via29 and pseudo- through-hole Via2' 10 are in the plane strain for eliminating dielectric layer
And the tension between dielectric layer and metal layer, it is preferable that through-hole Via29 and pseudo- through-hole Via2The setting of the transpostion interval of ' 10.
In the present invention, the material of passivation layer 6 can select in a wide range, but in order to improve the blunt of passivation layer 6
Change effect, it is preferable that passivation layer 6 is aluminum passivation layer.
On the basis of the above embodiment, in order to further convenient for the connection between pad and other elements, it is preferable that
Outer linkage lines are connected on pad.
On the basis of the above embodiment, the distribution density of through-hole can select in a wide range, but in order into
One step improves through-hole and is eliminating the effect on tension, it is preferable that the distance between adjacent through-holes and the size of weld pad are consistent.
Finally, the material of weld pad can select in a wide range, but in order to further increase the welding effect of weld pad,
Preferably, weld pad is aluminium welding pad.
It is described the prefered embodiments of the present invention in detail above in conjunction with attached drawing, still, the present invention is not limited to above-mentioned realities
The detail in mode is applied, within the scope of the technical concept of the present invention, a variety of letters can be carried out to technical solution of the present invention
Monotropic type, these simple variants all belong to the scope of protection of the present invention.
It is further to note that specific technical features described in the above specific embodiments, in not lance
In the case where shield, can be combined in any appropriate way, in order to avoid unnecessary repetition, the present invention to it is various can
No further explanation will be given for the combination of energy.
In addition, various embodiments of the present invention can be combined randomly, as long as it is without prejudice to originally
The thought of invention, it should also be regarded as the disclosure of the present invention.
Claims (7)
1. a kind of method for avoiding leading to metal medium fault rupture when chip package routing characterized by comprising
1) in metal layer M1(1) dielectric layer IMD1Middle production through-hole Via1(7) and pseudo- through-hole Via1'(8)；
2) in the dielectric layer IMD1Upper deposited metal layer M2(2), then in the metal layer M2(2) dielectric layer IMD2Middle production
Through-hole Via2(9) and pseudo- through-hole Via2'(10)；
3) in the dielectric layer IMD2Upper deposited metal layer Mx (3), then in the dielectric layer TIMD- of the metal layer Mx (3)1In
Make through-hole TVia-1(11)；
4) in the dielectric layer TIMD-1Upper deposited metal layer TM-1(4), then in the metal layer TM-1(4) dielectric layer
Through-hole Tvia (12) are made in TIMD；
5) the deposited metal layer TM (5) on the dielectric layer TIMD, the deposit passivation layer (6) on the metal layer TM (5), then
Pad is etched on the passivation layer (6).
2. the method according to claim 1, wherein the through-hole Via1(7) and pseudo- through-hole Via1' (8) intersect between
Every setting.
3. the method according to claim 1, wherein the through-hole Via2(9) and pseudo- through-hole Via2' (10) intersection
Interval setting.
4. the method according to claim 1, wherein the passivation layer (6) is aluminum passivation layer.
5. the method according to claim 1, wherein being connected with outer linkage lines on the pad.
6. method described in any one of -5 according to claim 1, which is characterized in that the distance between adjacent through-holes and weld pad
Size be consistent.
7. according to the method described in claim 6, it is characterized in that, the weld pad is aluminium welding pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810959822.0A CN109244034A (en) | 2018-08-22 | 2018-08-22 | The method for avoiding leading to metal medium fault rupture when chip package routing |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810959822.0A CN109244034A (en) | 2018-08-22 | 2018-08-22 | The method for avoiding leading to metal medium fault rupture when chip package routing |
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|---|---|
| CN109244034A true CN109244034A (en) | 2019-01-18 |
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| CN201810959822.0A Pending CN109244034A (en) | 2018-08-22 | 2018-08-22 | The method for avoiding leading to metal medium fault rupture when chip package routing |
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Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097875A (en) * | 2006-06-30 | 2008-01-02 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for making the same |
| CN102064155A (en) * | 2009-11-17 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP2012222256A (en) * | 2011-04-13 | 2012-11-12 | Panasonic Corp | Semiconductor integrated circuit device |
| CN109411407A (en) * | 2017-08-18 | 2019-03-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
-
2018
- 2018-08-22 CN CN201810959822.0A patent/CN109244034A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101097875A (en) * | 2006-06-30 | 2008-01-02 | 台湾积体电路制造股份有限公司 | Semiconductor device and method for making the same |
| CN102064155A (en) * | 2009-11-17 | 2011-05-18 | 台湾积体电路制造股份有限公司 | Semiconductor device and manufacturing method thereof |
| JP2012222256A (en) * | 2011-04-13 | 2012-11-12 | Panasonic Corp | Semiconductor integrated circuit device |
| CN109411407A (en) * | 2017-08-18 | 2019-03-01 | 中芯国际集成电路制造(上海)有限公司 | A kind of semiconductor devices and preparation method thereof |
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Application publication date: 20190118 |