CN109217966B - Operating system clock synchronization method and system under 2oo3 redundant structure - Google Patents
Operating system clock synchronization method and system under 2oo3 redundant structure Download PDFInfo
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Abstract
The invention provides a clock synchronization method and a system of an operating system under a 2oo3 redundant structure, which are characterized by comprising the following steps: a time delay obtaining step: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network; a node dividing step: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes; and a node synchronization step: and establishing a synchronous network to synchronize the slave clock node with the master clock node. The clock synchronization network established by the invention can cover a 2oo3 redundant structure, can autonomously maintain each node in the network, and can perform operations such as adding and deleting nodes or links. Can be adjusted according to different network loads and physical structures.
Description
Technical Field
The invention relates to the technical field of network information transmission, in particular to a clock synchronization method and system of an operating system under a 2oo3 redundant structure.
Background
The real-time embedded processing node has high reliability and safety requirements in safety critical fields such as aerospace, rail transit, military, energy and power and the like. In order to reduce and reduce the risk in the safety critical real-time embedded system, besides selecting high-reliability electronic components, a multi-mode redundancy mode is generally adopted to improve the reliability of the real-time embedded system and reduce the risk probability. Clock synchronization between processing nodes in the multi-mode redundant real-time embedded system is a key for ensuring correct real-time behavior of the system, for example, when voting is carried out on data, whether the data is input data or output data, the data is required to be consistent in time.
In the multi-mode redundant real-time embedded system, the clock attribute difference and the initial time of each real-time embedded processing node are different, a clock synchronization technology is needed to compensate for clock errors, and a uniform time base is constructed and maintained, so that the correctness of the real-time behavior of the system is ensured.
At present, the application field of safety key mainly adopts a clock synchronization technology based on a message switching network to compensate time errors, and two main error sources of clock drift and network message delay uncertainty need to be considered.
Synchronization protocols commonly used in node networks are the Network Time protocol ntp (Network Time protocol) and the simple Network Time protocol sntp (simple Network Time protocol). The node network adopting the NTP protocol synchronizes clocks of all nodes in the network to a certain clock standard, and the currently adopted Time standard is universal Time coordinated (utc). The clock synchronization of the NTP protocol is mainly realized in a master-slave working mode. Because the NTP adopts an application layer synchronization method, the time synchronization precision is generally between 10ms and 100ms, and the requirements of safety critical fields such as strong real time, high precision and the like cannot be met. SNTP is a simplified NTP synchronization protocol whose time accuracy depends on the client and server networks. However, SNTP uses the same clock synchronization strategy as NTP, and therefore, the synchronization accuracy is not high.
Meanwhile, in these clock synchronization methods, only the external clock is synchronized, and there is no adjustment of the internal clock of the operating system. While the system clock of the operating system plays an important role, an out-of-step system clock can affect the scheduling of tasks, the working state of a soft timer, the performance, the real-time response and other key indexes of the operating system. An operating system node that is out of sync in a redundant fabric may cause synchronization related problems with other nodes. For example, when some nodes in the redundant system are abnormally restarted, the internal clock of the operating system is inconsistent with the time in the entire redundant system, or due to clock drift caused by working environment and hardware errors, an abnormal node with a larger clock difference with other operating system nodes may appear in the redundant network.
Due to the appearance of the scenes, the method has partial limitation in the safety critical field because of the adoption of a synchronization method which only synchronizes an external clock and has low precision.
Patent document CN105187148A (application number: CN201510504383) discloses an ARM-based network clock synchronization system and method, the system includes the following: the GPS satellite time service module acquires satellite time information in a short time through a satellite; the NTP server converts the received time message into a standard format by using an embedded processor with an operating system as a server and calibrates the time of the NTP server; the hardware timekeeping module is used for storing the latest calibration time of the NTP server; and the client module acquires the server time and synchronizes the local system time. The patent document adopts a clock synchronization method based on NTP protocol, has high requirements on use environment, more constraint conditions and lower synchronization precision than the clock synchronization method adopting IEEE1588 protocol
Patent document CN102523066A (application number: CN201110438104) discloses a clock synchronization system and synchronization method based on IEEE1588 redundant slave clocks, in the synchronization method, after the system starts to operate, when a slave clock module enters a synchronization state, 1588 master clock information synchronized by the slave clock module is stored in the slave clock scheduling module, the slave clock scheduling module screens and outputs an optimal slave clock, and the synchronization system enters the synchronization state; when a certain slave clock loses the synchronous state in the system operation process, the slave clock scheduling module reselects an optimal slave clock and outputs the optimal slave clock as the clock output of the synchronous system. The synchronization system only synchronizes an external clock and does not use clock difference among nodes to synchronize internal clocks of the operating systems in the nodes.
Disclosure of Invention
Aiming at the defects in the prior art, the invention aims to provide a method and a system for operating system clock synchronization under a 2oo3 redundant structure.
The clock synchronization method of the operating system under the 2oo3 redundant structure provided by the invention comprises the following steps:
a time delay obtaining step: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node dividing step: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
and a node synchronization step: and establishing a synchronous network to synchronize the slave clock node with the master clock node.
Preferably, the node synchronization step includes:
a network creating step: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference obtaining step: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judging step: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, entering a difference adjusting step to continue execution;
and (3) difference adjustment: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, returning to the difference adjusting step to continue to execute; otherwise, judging that the synchronization is finished, obtaining synchronization finishing information, and entering a synchronization finishing step to continue execution;
and a synchronous finishing step: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
Preferably, when the system clock state of the slave clock node is the stop synchronization state Stopped, the slave clock node stops periodically sending the synchronization message to other nodes, the local clock of the slave clock node continues to run, and the slave clock node does not participate in the time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
Preferably, the adjustment queue records a difference value between the slave clock node and the master clock, and stores and reads the difference value in a first-in first-out (FIFO) mode;
and the synchronous message is sent according to a method specified by an IEEE1588 protocol.
Preferably, after each node in the node network receives the synchronization message sent by the method specified by the IEEE1588 protocol, fault detection is performed;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and returning to the delay acquisition step for continuous execution; if not, continuing to execute the node synchronization step;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and the delayed link is returned to the delayed acquisition step for continuous execution; if not, the node synchronization step is continuously executed.
According to the invention, the clock synchronization system of the operating system under the 2oo3 redundant structure comprises:
a delay acquisition module: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node division module: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
a node synchronization module: and establishing a synchronous network to synchronize the slave clock node with the master clock node.
Preferably, the node synchronization module includes:
a network creation module: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference acquisition module: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judgment module: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, triggering a difference adjusting module;
a difference adjusting module: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, triggering a difference adjusting module; otherwise, judging that the synchronization is completed, acquiring synchronization completion information, and triggering a synchronization completion module;
a synchronous completion module: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
Preferably, when the system clock state of the slave clock node is the stop synchronization state Stopped, the slave clock node stops periodically sending the synchronization message to other nodes, the local clock of the slave clock node continues to run, and the slave clock node does not participate in the time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
Preferably, the adjustment queue records a difference value between the slave clock node and the master clock, and stores and reads the difference value in a first-in first-out (FIFO) mode;
and the synchronous message is sent according to a method specified by an IEEE1588 protocol.
After each node in the node network receives the synchronous message sent by the method specified by the IEEE1588 protocol, fault detection is carried out;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and triggering a delay acquisition module; if not, triggering a node synchronization module;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and a delay acquisition module is triggered; if not, triggering the node synchronization module.
According to the present invention, there is provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the operating system clock synchronization method under the 2oo3 redundant structure described in any of the above.
Compared with the prior art, the invention has the following beneficial effects:
1. the clock synchronization network established by the invention can cover a 2oo3 redundant structure, can autonomously maintain each node in the network, and can perform operations such as adding and deleting nodes or links. Can be adjusted according to different network loads and physical structures.
2. The synchronization method adopted by the invention is based on an IEEE1588 clock synchronization protocol, and can improve the clock synchronization precision to ns level. The method can optimize the task scheduling, the working state of the soft timer, the performance, the real-time response and other key indexes of the operating system in the redundant structure operating system. Performance in the safety critical area goes beyond the traditional synchronization method.
3. The invention has certain robustness, can adjust the change of the network structure, can still normally and safely run when the system encounters a fault or an abnormity, and ensures the consistency of the system clocks of all nodes.
4. The clock synchronization method is based on an IEEE1588 high-precision clock synchronization protocol, and can improve the synchronization precision of the system clock of each operating system node to ns level.
5. The clock synchronization network constructed by the invention can dynamically manage the nodes and has certain robustness. When an operating system node or a communication link is abnormal or fails, the node or the link can be removed from the synchronous network, and the synchronization condition of the rest nodes is adjusted. When a new node is added, the synchronous network can dynamically adjust the master-slave clocks to accommodate the new node.
Drawings
Other features, objects and advantages of the invention will become more apparent upon reading of the detailed description of non-limiting embodiments with reference to the following drawings:
fig. 1 is a schematic structural diagram of a master-slave clock model provided in embodiment 3 of the present invention.
Fig. 2 is a schematic diagram of network adjustment after a node failure according to embodiment 3 of the present invention.
Fig. 3 is a schematic diagram of network adjustment after a link failure without involving a master clock according to embodiment 3 of the present invention.
Fig. 4 is a schematic diagram of network adjustment after a link failure related to a master clock according to embodiment 3 of the present invention.
Fig. 5 is a schematic diagram of system clock state transition provided in embodiment 3 of the present invention.
Fig. 6 is a schematic flow chart of a slave clock node synchronization process provided in embodiment 3 of the present invention.
Detailed Description
The present invention will be described in detail with reference to specific examples. The following examples will assist those skilled in the art in further understanding the invention, but are not intended to limit the invention in any way. It should be noted that it would be obvious to those skilled in the art that various changes and modifications can be made without departing from the spirit of the invention. All falling within the scope of the present invention.
The clock synchronization method of the operating system under the 2oo3 redundant structure provided by the invention comprises the following steps:
a time delay obtaining step: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node dividing step: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
and a node synchronization step: and establishing a synchronous network to synchronize the slave clock node with the master clock node.
Specifically, the node synchronization step includes:
a network creating step: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference obtaining step: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judging step: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, entering a difference adjusting step to continue execution;
and (3) difference adjustment: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, returning to the difference adjusting step to continue to execute; otherwise, judging that the synchronization is finished, obtaining synchronization finishing information, and entering a synchronization finishing step to continue execution;
and a synchronous finishing step: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
Specifically, when the system clock state of the slave clock node is a stop synchronization state Stopped, the slave clock node stops periodically sending synchronization messages to other nodes, the local clock of the slave clock node continues to run, and the slave clock node does not participate in time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
Specifically, the adjustment queue records the difference value between the slave clock node and the master clock, and stores and reads the difference value in a first-in first-out (FIFO) mode;
and the synchronous message is sent according to a method specified by an IEEE1588 protocol.
Specifically, after each node in the node network receives a synchronization message sent by a method specified by an IEEE1588 protocol, fault detection is carried out;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and returning to the delay acquisition step for continuous execution; if not, continuing to execute the node synchronization step;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and the delayed link is returned to the delayed acquisition step for continuous execution; if not, the node synchronization step is continuously executed.
The operating system clock synchronization system under the 2oo3 redundant structure provided by the invention can be realized through the step flow of the operating system clock synchronization method under the 2oo3 redundant structure provided by the invention. Those skilled in the art can understand the operating system clock synchronization method under the 2oo3 redundant structure as a preferred example of the operating system clock synchronization system under the 2oo3 redundant structure.
According to the invention, the clock synchronization system of the operating system under the 2oo3 redundant structure comprises:
a delay acquisition module: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node division module: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
a node synchronization module: and establishing a synchronous network to synchronize the slave clock node with the master clock node.
Specifically, the node synchronization module includes:
a network creation module: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference acquisition module: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judgment module: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, triggering a difference adjusting module;
a difference adjusting module: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, triggering a difference adjusting module; otherwise, judging that the synchronization is completed, acquiring synchronization completion information, and triggering a synchronization completion module;
a synchronous completion module: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
Specifically, when the system clock state of the slave clock node is a stop synchronization state Stopped, the slave clock node stops periodically sending synchronization messages to other nodes, the local clock of the slave clock node continues to run, and the slave clock node does not participate in time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
Specifically, the adjustment queue records the difference value between the slave clock node and the master clock, and stores and reads the difference value in a first-in first-out (FIFO) mode;
and the synchronous message is sent according to a method specified by an IEEE1588 protocol.
After each node in the node network receives the synchronous message sent by the method specified by the IEEE1588 protocol, fault detection is carried out;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and triggering a delay acquisition module; if not, triggering a node synchronization module;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and a delay acquisition module is triggered; if not, triggering the node synchronization module.
According to the present invention, there is provided a computer-readable storage medium storing a computer program which, when executed by a processor, implements the steps of the operating system clock synchronization method under the 2oo3 redundant structure described in any of the above.
The present invention will be described more specifically below with reference to preferred examples.
Example 1:
in a network as shown in fig. 1, there are two slave clock nodes and one master clock node, and 3 nodes are functioning normally. At a certain moment, the master clock sends out a synchronization signal according to the IEEE1588 standard, and after receiving the synchronization signal, one slave clock carries out the following synchronization process:
step 1: the Ethernet controller module receives the synchronous message from the main clock, reads the clock information in the high-precision clock module, calculates the clock difference to obtain-10 ms, and transmits the clock difference to the synchronous controller module.
Step 2: the synchronization controller module receives the clock difference, the absolute value of which is greater than the maximum tolerance difference by 1ms, so that the system clock state of the node is changed from Running & synchronizing to Running, the-10 ms clock difference is transmitted to the synchronization adjusting module, and the synchronization adjusting module newly enqueues an adjusting task in an adjusting queue syncList, wherein the task needs to adjust the local system clock forward by 10 ms.
And 4, step 4: and the synchronous adjusting module reads the adjusting queue SyncList, acquires an adjusting task of adjusting forward for 10ms, gradually adjusts the system clock data in the system clock module, polls to monitor whether the adjustment is completed or not, queries the adjusting queue SyncList after the adjustment is completed, repeats the step 4 if a new adjusting task exists, and enters the step 5 if the adjusting queue is empty.
And 5: and the synchronization adjusting module transmits the synchronization completion message to the synchronization controller module, and the synchronization controller sets the system clock state of the node to Running and synchronization. And completing the adjustment to realize clock synchronization.
Example 2:
in a network as shown in fig. 1, there are two slave clock nodes and one master clock node, and 3 nodes are functioning normally. At a certain moment, a slave clock node is restarted due to a fault, and the slave clock node is added into the node again after the restart is completed and is synchronized. The slave clock performs the following synchronization process:
step 1: after the node is newly added, the synchronous controller sets the state of the node to the Stopped state and waits for the synchronization with the main clock.
Step 2: the Ethernet controller module receives the synchronization message from the master clock, reads the clock information in the high-precision clock module, calculates the clock difference to obtain 900ms, and transmits the clock difference to the synchronization controller module.
And step 3: the synchronization controller module receives the clock difference which is larger than the maximum tolerance difference by 1ms, so that the system clock state of the node is changed from Stopped to Running and the 900ms clock difference is transmitted to the synchronization adjusting module, the synchronization adjusting module newly enqueues an adjusting task in an adjusting queue syncList, and the task needs to adjust the local system clock backwards by 900 ms.
And 4, step 4: and the synchronous adjusting module reads the adjusting queue SyncList, acquires an adjusting task of backward adjusting for 900ms, gradually adjusts the system clock data in the system clock module, polls to monitor whether the adjustment is completed or not, queries the adjusting queue SyncList after the adjustment is completed, repeats the step 4 if a new adjusting task exists, and enters the step 5 if the adjusting queue is empty.
And 5: and the synchronization adjusting module transmits the synchronization completion message to the synchronization controller module, and the synchronization controller sets the system clock state of the node to Running and synchronization. And completing the adjustment to realize clock synchronization.
Example 3:
the clock synchronization system of the operating system under the 2oo3 redundant structure is divided into a high-precision clock module, an Ethernet controller module, a synchronous adjustment module and a system clock module. A synchronous network as shown in figure 1 is established.
The high-precision clock module provides high-precision external clock data and adopts an IEEE1588 protocol to synchronize with the high-precision clock module of the master clock node in the network.
The Ethernet controller module is used for communicating with other nodes in the network, transmitting a synchronization message conforming to an IEEE1588 protocol, and transmitting the clock difference to the synchronization controller module.
The synchronization controller module receives the clock difference data from the ethernet controller module, analyzes the difference data, and manages the system clock state of the local node, as shown in fig. 5, which can be switched between three states, Stopped, Running & Synchronous. In the Stopped state, the node stops periodically sending synchronous messages to other nodes, and the local clock continues to run but does not participate in synchronous adjustment in the network; in the Running state, the nodes periodically send synchronization messages to other nodes according to a method specified by an IEEE1588 protocol to participate in synchronization adjustment in the network, but the synchronization state is not reached; and in the Running and Synchronous state, the node reaches a Synchronous state, periodically sends a Synchronous message to other nodes to confirm the Synchronous state of the node, and if the node loses the Synchronous state with the main clock, the node is switched to the Running state to be readjusted. And when the system clock state needs to be adjusted, transmitting the synchronization requirement to the synchronization adjusting module.
The synchronous adjusting module receives a synchronous signal from the synchronous controller module, calculates the time difference required to be adjusted, progressively adjusts the system clock module, polls whether the adjusting process is finished or not, and transmits the adjusting result to the synchronous controller module when the adjusting process is finished.
And the system clock module reads the internal clock data of the operating system, takes the internal clock data as the clock data of the node, receives the synchronization requirement from the synchronization adjusting module and performs synchronization adjustment on the data.
The node selected as the master clock only needs to send a synchronous message to each node in the node network in time according to the protocol. And the synchronization process of a slave clock node comprises the following steps:
step 1: and (4) joining a synchronous node network, and setting the node to a Stopped state by a synchronous controller.
Step 2: the Ethernet controller module receives the synchronous message sent by the main clock node, reads the clock information in the high-precision clock module, calculates the clock difference between the local node and the main clock node, and transmits the clock difference to the synchronous controller module.
And step 3: the synchronous controller module receives the clock difference, judges whether the clock difference is larger than a preset maximum tolerance difference MaxTolerableTime, if so, sets the system clock state of the node to Running and transmits the clock difference to an adjustment queue in the synchronous adjustment module, the adjustment queue records the difference value of the slave node and the master clock, stores and reads the difference value in a first-in first-out (FIFO) mode, and then enters the step 4, otherwise, enters the step 3 to wait for the next clock difference data.
And 4, step 4: and the synchronous adjusting module reads the adjusting queue, acquires the time difference to be adjusted, gradually adjusts the system clock data in the system clock module by modifying the system clock frequency, polls to monitor whether the adjustment is completed or not, inquires the adjusting queue after the adjustment is completed, repeats the step 4 if a new adjusting task is completed, and enters the step 5 if the adjusting queue is empty.
And 5: and the synchronization adjusting module transmits the synchronization completion message to the synchronization controller module, and the synchronization controller sets the system clock state of the node to Running and synchronization. And completing the adjustment to realize clock synchronization.
The establishment process of the whole synchronous network comprises the following steps:
step 1: each node in the node network communicates with other nodes once to obtain the communication delay with other nodes.
Step 2: and selecting a node with the minimum average delay with other two nodes as a master clock node, and taking the other nodes as slave clock nodes.
And step 3: each slave clock node is added into the synchronous node network and is synchronous with the master clock node. The specific process is the synchronization step described above.
And 4, step 4: the slave clock nodes are synchronized, and the whole system is in a synchronous state.
After the synchronous network is established, if each node receives a message for adjusting the topological structure according with an IEEE1588 synchronous protocol, fault detection is carried out, and the processing process comprises the following steps.
If a node failure occurs:
step 1: and (3) determining whether the fault node is a master clock node, if so, entering the step (2), and otherwise, entering the step (3).
Step 2: and reselecting a master clock node from the remaining two nodes.
And step 3: and removing the failed node from the synchronous network, and performing synchronization again, as shown in fig. 2.
If a link failure occurs:
step 1: and (4) confirming whether the fault link relates to a master clock, if so, entering a step 2, otherwise, entering a step 3.
Step 2: as shown in fig. 4, the intermediate node is selected as a new master clock node, and the remaining two nodes are selected as slave clock nodes.
And step 3: and removing the failed link from the synchronous network, and carrying out synchronization again.
Those skilled in the art will appreciate that, in addition to implementing the systems, apparatus, and various modules thereof provided by the present invention in purely computer readable program code, the same procedures can be implemented entirely by logically programming method steps such that the systems, apparatus, and various modules thereof are provided in the form of logic gates, switches, application specific integrated circuits, programmable logic controllers, embedded microcontrollers and the like. Therefore, the system, the device and the modules thereof provided by the present invention can be considered as a hardware component, and the modules included in the system, the device and the modules thereof for implementing various programs can also be considered as structures in the hardware component; modules for performing various functions may also be considered to be both software programs for performing the methods and structures within hardware components.
The foregoing description of specific embodiments of the present invention has been presented. It is to be understood that the present invention is not limited to the specific embodiments described above, and that various changes or modifications may be made by one skilled in the art within the scope of the appended claims without departing from the spirit of the invention. The embodiments and features of the embodiments of the present application may be combined with each other arbitrarily without conflict.
Claims (8)
1. A method for operating system clock synchronization under a 2oo3 redundant structure, comprising:
a time delay obtaining step: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node dividing step: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
and a node synchronization step: establishing a synchronous network, and synchronizing the slave clock node with the master clock node;
the node synchronization step includes:
a network creating step: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference obtaining step: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judging step: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, entering a difference adjusting step to continue execution;
and (3) difference adjustment: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, returning to the difference adjusting step to continue to execute; otherwise, judging that the synchronization is finished, obtaining synchronization finishing information, and entering a synchronization finishing step to continue execution;
and a synchronous finishing step: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
2. The method for operating system clock synchronization under 2oo3 redundancy structure, according to claim 1, wherein when the system clock state of the slave clock node is stop synchronization state Stopped, the slave clock node stops periodically sending synchronization messages to other nodes, the local clock of the slave clock node continues running, and the slave clock node does not participate in time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
3. The method for operating system clock synchronization under 2oo3 redundancy structure of claim 2, wherein the adjustment queue records the difference value between the slave clock node and the master clock, and stores and reads in FIFO mode;
and the synchronous message is sent according to a method specified by an IEEE1588 protocol.
4. The operating system clock synchronization method under the 2oo3 redundant structure according to claim 3, wherein each node in the node network performs fault detection after receiving a synchronization message sent by a method specified by the IEEE1588 protocol;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and returning to the delay acquisition step for continuous execution; if not, continuing to execute the node synchronization step;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and the delayed link is returned to the delayed acquisition step for continuous execution; if not, the node synchronization step is continuously executed.
5. An operating system clock synchronization system under a 2oo3 redundant architecture, comprising:
a delay acquisition module: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network;
a node division module: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes;
a node synchronization module: establishing a synchronous network, and synchronizing the slave clock node with the master clock node;
the node synchronization module includes:
a network creation module: adding each slave clock node into a synchronous network, setting the system clock state of each slave clock node to be a Stopped synchronous state Stopped, and enabling the master clock node to send a synchronous message;
a clock difference acquisition module: receiving a synchronization message sent by a master clock node, sequentially reading clock information of each slave clock node, sequentially calculating clock differences of each slave clock node and the master clock node, and obtaining the clock differences of each slave clock node and the master clock node;
a difference judgment module: sequentially judging whether the clock difference between each slave clock node and the master clock node is greater than a preset maximum tolerance difference MaxTolerableTime according to the acquired clock difference between each slave clock node and the master clock node: if so, setting the system clock state of the corresponding slave clock node as a Running state, and storing the clock difference into an adjustment queue; otherwise, skipping the clock difference and continuously judging the next clock difference; after all clock differences are judged, triggering a difference adjusting module;
a difference adjusting module: reading the adjustment queue, acquiring the clock difference to be adjusted according to the adjustment queue, gradually adjusting system clock data by modifying the system clock frequency, namely synchronizing the clock information of the slave clock node corresponding to the clock difference to be adjusted with the clock information of the master clock node, polling to monitor whether the adjustment is completed or not, and inquiring whether the adjustment queue has the new clock difference to be adjusted or not after the adjustment is completed: if yes, triggering a difference adjusting module; otherwise, judging that the synchronization is completed, acquiring synchronization completion information, and triggering a synchronization completion module;
a synchronous completion module: and according to the obtained synchronization completion information, setting the system clock state of each slave clock node as a synchronization completion state Running & Synchronous.
6. The operating system clock synchronization system under the 2oo3 redundant structure of claim 5, wherein, when the system clock state of the slave clock node is stop synchronization state Stopped, the slave clock node stops periodically sending synchronization messages to other nodes, the local clock of the slave clock node continues to run, and the slave clock node does not participate in time synchronization adjustment in the synchronization network;
when the system clock state of the slave clock node is Running, the slave clock node periodically sends a synchronization message to other nodes according to a method specified by an IEEE1588 protocol to participate in time synchronization adjustment in a synchronization network;
when the system clock state of the slave clock node is a synchronization completion state Running & synchronization, the slave clock node reaches a synchronization state, periodically sends a synchronization message to other nodes to confirm the synchronization state of the slave clock node, and if the slave clock node and the master clock node are out of synchronization, the slave clock node is switched to a continuous synchronization state Running to be readjusted.
7. The operating system clock synchronization system under the 2oo3 redundant structure of claim 6, wherein, the adjustment queue records the difference value between the slave clock node and the master clock, and stores and reads in a first-in-first-out FIFO mode;
the synchronous message is sent according to a method specified by an IEEE1588 protocol;
after each node in the node network receives the synchronous message sent by the method specified by the IEEE1588 protocol, fault detection is carried out;
the node network has 3 nodes;
the fault detection includes:
judging whether node failure occurs: if yes, judging whether the fault node is a main clock node: if the node is the master clock node, reselecting a master clock node from the rest two nodes; if the node is not the master clock node, removing the failed node from the synchronous network, and triggering a delay acquisition module; if not, triggering a node synchronization module;
judging whether a link failure occurs: if yes, judging whether the fault link relates to a master clock node: if the master clock node is involved, selecting the middle node in the effective link as a new master clock node, and taking the other two nodes as slave clock nodes; if the master clock node is not involved, the failed link is removed from the synchronous network, and a delay acquisition module is triggered; if not, triggering the node synchronization module.
8. A computer readable storage medium storing a computer program, wherein the computer program, when executed by a processor, implements the steps of the operating system clock synchronization method under the 2oo3 redundancy architecture of any of claims 1 to 4.
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