CN109217966A - Operating system clock synchronization method and system under 2oo3 redundant structure - Google Patents
Operating system clock synchronization method and system under 2oo3 redundant structure Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
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- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04J—MULTIPLEX COMMUNICATION
- H04J3/00—Time-division multiplex systems
- H04J3/02—Details
- H04J3/06—Synchronising arrangements
- H04J3/0635—Clock or time synchronisation in a network
- H04J3/0638—Clock or time synchronisation among nodes; Internode synchronisation
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Abstract
The invention provides a clock synchronization method and a system of an operating system under a 2oo3 redundant structure, which are characterized by comprising the following steps: a time delay obtaining step: respectively carrying out primary communication between each node in the node network and other nodes in the node network to obtain communication delay between each node and other nodes in the node network; a node dividing step: calculating the average communication delay of each node and other nodes according to the acquired communication delay of each node and other nodes, selecting a node with the minimum average communication delay as a master clock node, and taking other nodes in a node network as slave clock nodes; and a node synchronization step: and establishing a synchronous network to synchronize the slave clock node with the master clock node. The clock synchronization network established by the invention can cover a 2oo3 redundant structure, can autonomously maintain each node in the network, and can perform operations such as adding and deleting nodes or links. Can be adjusted according to different network loads and physical structures.
Description
Technical field
The present invention relates to network information transfer technical fields, and in particular, to the operation system under a kind of 2oo3 redundancy structure
System clock synchronizing method, system.
Background technique
Real-time embedded processing is saved in the safe field that concerns such as aerospace, rail traffic, military affairs and electricity power
Point has very high reliability and security requirement.In security critical real time embedded system, in order to reduce and reduce wind
Danger, other than selecting highly reliable electronic component, the mode for generalling use multi-mode redundant improves the reliable of real time embedded system
Property and reduce risk probability.To synchronize the system of being to ensure that correctly real-time for clock between handling node in multi-mode redundant real time embedded system
The key of sexual behaviour, such as when to data voting, it is desirable that either input data or output data, will when engrave holding
Unanimously.
The Clock properties difference of each real-time embedded processing node and initial in multi-mode redundant real time embedded system
Time is different, needs to carry out compensating clock error using Clock Synchronization Technology, constructs and safeguard a unified time base, so that it is guaranteed that
The correctness of the real-time behavior of system.
Security critical application field is mainly using the Clock Synchronization Technology based on message switching network come when compensating at present
Between error, while needing to consider that clock drift and internet message postpone uncertain two main error sources.
The synchronous protocol being usually used in meshed network have Network Time Protocol NTP (Network Time Protocol) and
Simple Network Time Protocol SNTP (Simple Network Time Protocol).Using the meshed network of Network Time Protocol by net
Each nodal clock is synchronized to some clock standard in network, and currently used time standard is UTC Universal Time Coordinated UTC
(Universal Time Coordinated).The synchronous clock of Network Time Protocol is mainly to realize under principal and subordinate's working method.By
In NTP using layer synchronizing method is applied, timing tracking accuracy is not able to satisfy strong reality generally in 10ms between 100ms
When, the safety-criticals field such as high-precision requirement.SNTP is then a simplified NTP synchronous protocol, and time precision depends on
The case where client and server-side network.But it since SNTP is using clock synchronization policy identical with NTP, synchronizes
Precision is not also high.
Meanwhile in these clock synchronizing methods, external clock is only synchronized, the tune to operating system internal clocking is lacked
It is whole.And the system clock of operating system plays key player, the system clock of a step-out will affect the scheduling of task, soft fixed
When device the operating systems key index such as working condition, performance and real-time response.The behaviour of step-out in one redundancy structure
Relevant issues synchronous with other nodes may be caused by making system node.For example, it is different to work as part of nodes generation in redundant system
After often restarting, operating system internal clocking and the Time Inconsistency in entire redundant system, or due to working environment and firmly
Clock drift caused by part error so that will appear in redundant network differ greatly with other operating system nodal clocks it is different
Chang Jiedian.
The appearance of the above scene, use only synchronizes external clock and the not high synchronous method of precision causes it in safety
Key area has part limitation.
When patent document CN105187148A (application number: CN201510504383) discloses a kind of network based on ARM
Clock synchronization system and method, the system include the following: GPS satellite time service module, when obtaining satellite in a short time by satellite
Between information；Ntp server is switched to received time message using the embeded processor of tape operation system as server
Reference format, and calibrate the machine time；Hardware is kept time module, the time calibrated recently for storing ntp server；Client mould
Block obtains server time, synchronous local system time.The patent document uses the clock synchronizing method based on Network Time Protocol, makes
With environmental requirement height, constraint condition is more and synchronization accuracy is not as good as the clock synchronizing method using IEEE1588 agreement
Patent document CN102523066A (application number: CN201110438104) is disclosed based on IEEE1588 redundancy from clock
Clock system and synchronous method enter synchronous regime from clock module when one after system brings into operation in synchronous method,
The 1588 master clock information preservations synchronized from clock module to from clock scheduler module, screens and export from clock scheduler module
It is optimal from clock, synchronization system enters synchronous regime；In system operation, when some loses synchronous regime from clock, from clock scheduling
It is optimal from clock that module selects one again, and exports the clock output as synchronization system.When the synchronization system only synchronizes outside
Clock, and the timing differential being not used between each node synchronizes node internal operating system internal clocking.
Summary of the invention
For the defects in the prior art, the object of the present invention is to provide when the operating system under a kind of 2oo3 redundancy structure
Clock synchronous method, system.
The operation system clock synchronous method under a kind of 2oo3 redundancy structure provided according to the present invention, comprising:
Delay acquisition step: node each in meshed network and remaining node in meshed network are once led to respectively
News, the communication for obtaining remaining node in each node and meshed network are delayed；
Node division step: it is delayed according to the communication of each node of acquisition and remaining node, calculates each node and its
The average communication of remaining node is delayed, and chooses an average communication and is delayed the smallest node as master clock node, by meshed network
In remaining node be used as from clock node；
Node synchronizing step: establishing synchronizing network, will be synchronous with master clock node from clock node.
Preferably, the node synchronizing step includes:
Network creation step: respectively will be added synchronizing network from clock node, will be respectively from the system clock state of clock node
It is set as stopping synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtaining step: the synchronization message that master clock node is sent is received, is successively read respectively from clock node
Clock information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock
The timing differential of node；
Diversity judgement step: according to each timing differential from clock node and master clock node of acquisition, successively judgement is each
Whether it is greater than preset maximum tolerance difference MaxTolerableTime from the timing differential of clock node and master clock node: if
It is that be then arranged corresponding from the system clock state of clock node be continued synchronization state Running, and the timing differential is deposited
The adjustment queue of storage extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All clock differences are judged
After different, continued to execute into discrepancy adjustment step；
Discrepancy adjustment step: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, is by modification
System clock frequency incrementally adjusts system clock data, i.e., the timing differential that need to be adjusted is corresponding from the clock of clock node letter
Breath, synchronous with the clock information of master clock node, whether poll monitoring adjustment is completed, after the completion of adjustment, inquiry adjustment team
Whether column have the timing differential of new need adjustment: continuing to execute if so, then returning to discrepancy adjustment step；Otherwise, then determine to synchronize
It completes, acquisition synchronously completes information, continues to execute into step is synchronously completed；
It synchronously completes step: information is synchronously completed according to acquisition, will respectively be arranged from the system clock state of clock node
To synchronously complete state Running&Synchronous.
It preferably, is when stopping synchronous regime Stopped, to stop from clock node from the system clock state of clock node
Synchronization message periodically is sent to other nodes, continues to run from the local clock of clock node, is not involved in from clock node
Time synchronization adjustment in synchronizing network；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588
Method as defined in agreement periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, from clock section from the system clock state of clock node
Point reaches synchronous regime, periodically sends synchronization message to other nodes, confirms the synchronous regime from clock node, if discovery
Synchronous regime is lost from clock node and master clock node, then switches to continued synchronization state Running readjustment.
Preferably, the values of disparity from clock node and master clock is had recorded in the adjustment queue, using first in first out
Fifo mode is stored and is read；
The synchronization message is sent by method as defined in IEEE1588 agreement.
Preferably, each node receives the synchronization message sent by method as defined in IEEE1588 agreement in meshed network
Afterwards, fault detection is carried out；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock section
Point then chooses a master clock node in remaining two nodes again；If not master clock node, then by the node of failure from
It is rejected in synchronizing network, returns to delay acquisition step and continue to execute；If it is not, then continuing to execute node synchronizing step；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if be related to main
Intermediate node in active link, then is chosen for new master clock node by clock node, and other two node is used as from clock section
Point；If not being related to master clock node, failed link is rejected from synchronizing network, returns to delay acquisition step and continue to execute；
If it is not, then continuing to execute node synchronizing step.
The operation system clock synchronization system under a kind of 2oo3 redundancy structure provided according to the present invention, comprising:
Delay acquisition module: node each in meshed network and remaining node in meshed network are once led to respectively
News, the communication for obtaining remaining node in each node and meshed network are delayed；
Node division module: it is delayed according to the communication of each node of acquisition and remaining node, calculates each node and its
The average communication of remaining node is delayed, and chooses an average communication and is delayed the smallest node as master clock node, by meshed network
In remaining node be used as from clock node；
Node synchronization module: establishing synchronizing network, will be synchronous with master clock node from clock node.
Preferably, the node synchronization module includes:
Network creation module: respectively will be added synchronizing network from clock node, will be respectively from the system clock state of clock node
It is set as stopping synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtains module: receiving the synchronization message that master clock node is sent, is successively read respectively from clock node
Clock information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock
The timing differential of node；
Diversity judgement module: according to each timing differential from clock node and master clock node of acquisition, successively judgement is each
Whether it is greater than preset maximum tolerance difference MaxTolerableTime from the timing differential of clock node and master clock node: if
It is that be then arranged corresponding from the system clock state of clock node be continued synchronization state Running, and the timing differential is deposited
The adjustment queue of storage extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All clock differences are judged
After different, discrepancy adjustment module is triggered；
Discrepancy adjustment module: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, is by modification
System clock frequency incrementally adjusts system clock data, i.e., the timing differential that need to be adjusted is corresponding from the clock of clock node letter
Breath, synchronous with the clock information of master clock node, whether poll monitoring adjustment is completed, after the completion of adjustment, inquiry adjustment team
Whether column have the timing differential of new need adjustment: if so, then triggering discrepancy adjustment module；Otherwise, then determine to synchronously complete, obtain
Information is synchronously completed, triggering synchronously completes module；
It synchronously completes module: information is synchronously completed according to acquisition, will respectively be arranged from the system clock state of clock node
To synchronously complete state Running&Synchronous.
It preferably, is when stopping synchronous regime Stopped, to stop from clock node from the system clock state of clock node
Synchronization message periodically is sent to other nodes, continues to run from the local clock of clock node, is not involved in from clock node
Time synchronization adjustment in synchronizing network；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588
Method as defined in agreement periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, from clock section from the system clock state of clock node
Point reaches synchronous regime, periodically sends synchronization message to other nodes, confirms the synchronous regime from clock node, if discovery
Synchronous regime is lost from clock node and master clock node, then switches to continued synchronization state Running readjustment.
Preferably, the values of disparity from clock node and master clock is had recorded in the adjustment queue, using first in first out
Fifo mode is stored and is read；
The synchronization message is sent by method as defined in IEEE1588 agreement.
After each node receives the synchronization message sent by method as defined in IEEE1588 agreement in meshed network, event is carried out
Barrier detection；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock section
Point then chooses a master clock node in remaining two nodes again；If not master clock node, then by the node of failure from
It is rejected in synchronizing network, Time delay obtains module；If it is not, then triggering node synchronization module；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if be related to main
Intermediate node in active link, then is chosen for new master clock node by clock node, and other two node is used as from clock section
Point；If not being related to master clock node, failed link is rejected from synchronizing network, Time delay obtains module；If it is not, then touching
Send out node synchronization module.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of the operation system clock synchronous method under 2oo3 redundancy structure described in any of the above embodiments is realized when sequence is executed by processor
Suddenly.
Compared with prior art, the present invention have it is following the utility model has the advantages that
1, clock synchronous network network established by the present invention can cover 2oo3 redundancy structure, can respectively save in independence maintenance network
Point can be added, the operation such as deletion of node or link.It can be adjusted according to different network load and physical structure
It is whole.
2, the synchronous method that the present invention uses is based on IEEE1588 clock synchronization protocol, clock synchronization accuracy can be improved
To ns rank.Can with the working condition of task schedule, soft timer in optimizing redundancy structured operating system, performance and
The operating systems key index such as real-time response.Performance in safety-critical field exceeds conventional synchronization methods.
3, the present invention has certain robustness, and the variation that network structure can occur is made adjustment, and meets with event in system
When barrier or exception, it still is able to normal and safe operation, it is ensured that the consistency of each node system clock.
4, clock synchronizing method of the invention is based on IEEE1588 high precision clock synchronous protocol, can be by each operating system
The synchronization accuracy of the system clock of node is increased to ns rank.
5, the clock synchronous network network constructed by the present invention can dynamically manage node, and have certain robustness.
When having operating system node or communication link to be abnormal or failure, node or link can be rejected from synchronizing network, and
Adjust remaining node synchronous situation.When there is new node addition, synchronizing network can dynamically adjust master-salve clock, accommodate new section
Point.
Detailed description of the invention
Upon reading the detailed description of non-limiting embodiments with reference to the following drawings, other feature of the invention,
Objects and advantages will become more apparent upon:
Fig. 1 is the master-salve clock model structure schematic diagram that the embodiment of the present invention 3 provides.
Fig. 2 is that the network after the node failure that the embodiment of the present invention 3 provides adjusts schematic diagram.
Fig. 3 is the network adjustment schematic diagram being not directed to after the link failure of master clock that the embodiment of the present invention 3 provides.
Fig. 4 is the network adjustment schematic diagram being related to after the link failure of master clock that the embodiment of the present invention 3 provides.
Fig. 5 is the system clock condition conversion schematic diagram that the embodiment of the present invention 3 provides.
The slave clock node synchronizing process flow diagram that Fig. 6 the embodiment of the present invention 3 provides.
Specific embodiment
The present invention is described in detail combined with specific embodiments below.Following embodiment will be helpful to the technology of this field
Personnel further understand the present invention, but the invention is not limited in any way.It should be pointed out that the ordinary skill of this field
For personnel, without departing from the inventive concept of the premise, several changes and improvements can also be made.These belong to the present invention
Protection scope.
The operation system clock synchronous method under a kind of 2oo3 redundancy structure provided according to the present invention, comprising:
Delay acquisition step: node each in meshed network and remaining node in meshed network are once led to respectively
News, the communication for obtaining remaining node in each node and meshed network are delayed；
Node division step: it is delayed according to the communication of each node of acquisition and remaining node, calculates each node and its
The average communication of remaining node is delayed, and chooses an average communication and is delayed the smallest node as master clock node, by meshed network
In remaining node be used as from clock node；
Node synchronizing step: establishing synchronizing network, will be synchronous with master clock node from clock node.
Specifically, the node synchronizing step includes:
Network creation step: respectively will be added synchronizing network from clock node, will be respectively from the system clock state of clock node
It is set as stopping synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtaining step: the synchronization message that master clock node is sent is received, is successively read respectively from clock node
Clock information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock
The timing differential of node；
Diversity judgement step: according to each timing differential from clock node and master clock node of acquisition, successively judgement is each
Whether it is greater than preset maximum tolerance difference MaxTolerableTime from the timing differential of clock node and master clock node: if
It is that be then arranged corresponding from the system clock state of clock node be continued synchronization state Running, and the timing differential is deposited
The adjustment queue of storage extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All clock differences are judged
After different, continued to execute into discrepancy adjustment step；
Discrepancy adjustment step: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, is by modification
System clock frequency incrementally adjusts system clock data, i.e., the timing differential that need to be adjusted is corresponding from the clock of clock node letter
Breath, synchronous with the clock information of master clock node, whether poll monitoring adjustment is completed, after the completion of adjustment, inquiry adjustment team
Whether column have the timing differential of new need adjustment: continuing to execute if so, then returning to discrepancy adjustment step；Otherwise, then determine to synchronize
It completes, acquisition synchronously completes information, continues to execute into step is synchronously completed；
It synchronously completes step: information is synchronously completed according to acquisition, will respectively be arranged from the system clock state of clock node
To synchronously complete state Running&Synchronous.
It specifically, is when stopping synchronous regime Stopped, to stop from clock node from the system clock state of clock node
Synchronization message periodically is sent to other nodes, continues to run from the local clock of clock node, is not involved in from clock node
Time synchronization adjustment in synchronizing network；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588
Method as defined in agreement periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, from clock section from the system clock state of clock node
Point reaches synchronous regime, periodically sends synchronization message to other nodes, confirms the synchronous regime from clock node, if discovery
Synchronous regime is lost from clock node and master clock node, then switches to continued synchronization state Running readjustment.
Specifically, the values of disparity from clock node and master clock is had recorded in the adjustment queue, using first in first out
Fifo mode is stored and is read；
The synchronization message is sent by method as defined in IEEE1588 agreement.
Specifically, each node receives the synchronization message sent by method as defined in IEEE1588 agreement in meshed network
Afterwards, fault detection is carried out；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock section
Point then chooses a master clock node in remaining two nodes again；If not master clock node, then by the node of failure from
It is rejected in synchronizing network, returns to delay acquisition step and continue to execute；If it is not, then continuing to execute node synchronizing step；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if be related to main
Intermediate node in active link, then is chosen for new master clock node by clock node, and other two node is used as from clock section
Point；If not being related to master clock node, failed link is rejected from synchronizing network, returns to delay acquisition step and continue to execute；
If it is not, then continuing to execute node synchronizing step.
The operation system clock synchronization system under 2oo3 redundancy structure provided by the invention, can give through the invention
The step process of the operation system clock synchronous method under 2oo3 redundancy structure is realized.Those skilled in the art can will be described
The operation system clock synchronous method under 2oo3 redundancy structure, the operation system clock being interpreted as under the 2oo3 redundancy structure are same
One preference of step system.
The operation system clock synchronization system under a kind of 2oo3 redundancy structure provided according to the present invention, comprising:
Delay acquisition module: node each in meshed network and remaining node in meshed network are once led to respectively
News, the communication for obtaining remaining node in each node and meshed network are delayed；
Node division module: it is delayed according to the communication of each node of acquisition and remaining node, calculates each node and its
The average communication of remaining node is delayed, and chooses an average communication and is delayed the smallest node as master clock node, by meshed network
In remaining node be used as from clock node；
Node synchronization module: establishing synchronizing network, will be synchronous with master clock node from clock node.
Specifically, the node synchronization module includes:
Network creation module: respectively will be added synchronizing network from clock node, will be respectively from the system clock state of clock node
It is set as stopping synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtains module: receiving the synchronization message that master clock node is sent, is successively read respectively from clock node
Clock information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock
The timing differential of node；
Diversity judgement module: according to each timing differential from clock node and master clock node of acquisition, successively judgement is each
Whether it is greater than preset maximum tolerance difference MaxTolerableTime from the timing differential of clock node and master clock node: if
It is that be then arranged corresponding from the system clock state of clock node be continued synchronization state Running, and the timing differential is deposited
The adjustment queue of storage extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All clock differences are judged
After different, discrepancy adjustment module is triggered；
Discrepancy adjustment module: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, is by modification
System clock frequency incrementally adjusts system clock data, i.e., the timing differential that need to be adjusted is corresponding from the clock of clock node letter
Breath, synchronous with the clock information of master clock node, whether poll monitoring adjustment is completed, after the completion of adjustment, inquiry adjustment team
Whether column have the timing differential of new need adjustment: if so, then triggering discrepancy adjustment module；Otherwise, then determine to synchronously complete, obtain
Information is synchronously completed, triggering synchronously completes module；
It synchronously completes module: information is synchronously completed according to acquisition, will respectively be arranged from the system clock state of clock node
To synchronously complete state Running&Synchronous.
It specifically, is when stopping synchronous regime Stopped, to stop from clock node from the system clock state of clock node
Synchronization message periodically is sent to other nodes, continues to run from the local clock of clock node, is not involved in from clock node
Time synchronization adjustment in synchronizing network；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588
Method as defined in agreement periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, from clock section from the system clock state of clock node
Point reaches synchronous regime, periodically sends synchronization message to other nodes, confirms the synchronous regime from clock node, if discovery
Synchronous regime is lost from clock node and master clock node, then switches to continued synchronization state Running readjustment.
Specifically, the values of disparity from clock node and master clock is had recorded in the adjustment queue, using first in first out
Fifo mode is stored and is read；
The synchronization message is sent by method as defined in IEEE1588 agreement.
After each node receives the synchronization message sent by method as defined in IEEE1588 agreement in meshed network, event is carried out
Barrier detection；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock section
Point then chooses a master clock node in remaining two nodes again；If not master clock node, then by the node of failure from
It is rejected in synchronizing network, Time delay obtains module；If it is not, then triggering node synchronization module；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if be related to main
Intermediate node in active link, then is chosen for new master clock node by clock node, and other two node is used as from clock section
Point；If not being related to master clock node, failed link is rejected from synchronizing network, Time delay obtains module；If it is not, then touching
Send out node synchronization module.
A kind of computer readable storage medium for being stored with computer program provided according to the present invention, the computer journey
The step of the operation system clock synchronous method under 2oo3 redundancy structure described in any of the above embodiments is realized when sequence is executed by processor
Suddenly.
Below by preference, the present invention is more specifically illustrated.
Embodiment 1:
In a network as shown in Figure 1, there are two from clock node and a master clock node, 3 nodes are all just
Often operation.At a time, master clock follows IEEE1588 standard and has issued synchronization signal, one of them is received together from clock
Following synchronizing process has been carried out after step signal:
Step 1: ethernet controller module receives the synchronization message for carrying out master clock, reads in high precision clock module
Clock information calculates the timing differential and obtains -10ms, and timing differential is passed to isochronous controller module.
Step 2: isochronous controller module receives timing differential, and absolute value is greater than maximum tolerance difference 1ms, then incite somebody to action this
The system clock state of node is changed to Running from Running&Synchronous and -10ms timing differential is passed to synchronization
Module is adjusted, synchronous adjustment module is newly joined the team an adjustment task in adjustment queue SyncList, which must be by local system
System clock adjusts forward 10ms.
Step 4: synchronous adjustment module reads adjustment queue SyncList, obtains the adjustment task for adjusting 10ms forward, gradually
System clock data into adjustment system clock module, and whether poll monitoring adjustment is completed, after the completion of it, inquiry adjustment
Queue SyncList, if adjustment queue is sky, enters step 5 if there is new adjustment task duplication step 4.
Step 5: synchronous adjustment module will synchronously complete message and pass to isochronous controller module, and isochronous controller is by this section
The system clock state of point is set as Running&Synchronous.Adjustment is completed, and realizes that clock is synchronous.
Embodiment 2:
In a network as shown in Figure 1, there are two from clock node and a master clock node, 3 nodes are all just
Often operation.At a time, one from clock node since failure is restarted, node is rejoined after the completion of restarting and is carried out same
Step.This has carried out following synchronizing process from clock:
Step 1: after newly added node, node state is set as Stopped state by isochronous controller, is waited and master clock
It is synchronous.
Step 2: ethernet controller module receives the synchronization message for carrying out master clock, reads in high precision clock module
Clock information calculates the timing differential and obtains 900ms, and timing differential is passed to isochronous controller module.
Step 3: isochronous controller module receives timing differential, is greater than maximum tolerance difference 1ms, is then by this node
System clock status is changed to Running from Stopped and 900ms timing differential is passed to synchronous adjustment module, synchronous adjustment mould
Block is newly joined the team an adjustment task in adjustment queue SyncList, which must adjust backward 900ms for local system clock.
Step 4: synchronous adjustment module reads adjustment queue SyncList, obtains the adjustment task for adjusting 900ms backward, gradually
System clock data into adjustment system clock module, and whether poll monitoring adjustment is completed, after the completion of it, inquiry adjustment
Queue SyncList, if adjustment queue is sky, enters step 5 if there is new adjustment task duplication step 4.
Step 5: synchronous adjustment module will synchronously complete message and pass to isochronous controller module, and isochronous controller is by this section
The system clock state of point is set as Running&Synchronous.Adjustment is completed, and realizes that clock is synchronous.
Embodiment 1:
The operation system clock synchronization system under 2oo3 redundancy structure of the invention is divided into high precision clock module, Ethernet
Controller module, isochronous controller module, synchronous adjustment module, system clock module.Establish a synchronization net as shown in Figure 1
Network.
High precision clock module provides high-precision external clock data, using master clock in IEEE1588 agreement and network
The high precision clock module of node synchronizes.
For ethernet controller module for being communicated with other nodes in network, transmitting meets the same of IEEE1588 agreement
Message is walked, timing differential is passed into isochronous controller module.
Isochronous controller module receives the timing differential data from ethernet controller module, carries out to variance data
The system clock state of local node is analyzed and manages, as shown in figure 5, can be in Stopped, Running, Running&
Switch between tri- kinds of states of Synchronous.Under Stopped state, synchronizes to node dwelling period and disappear to the transmission of other nodes
Breath, local clock continues to run, but is not involved in the synchronous adjustment in network；Under Running state, node presses IEEE1588 agreement
Defined method periodically sends synchronization message to other nodes, participates in the synchronous adjustment in network, but not up to synchronous shape
State；Running&Synchronous state, node have reached synchronous regime, periodically send synchronization message to other nodes,
Confirm the synchronous regime of oneself, oneself and master clock lose synchronous regime if finding, switch to Running state and adjust again
It is whole.Synchronous requirement is passed into synchronous adjustment module when needing to adjust system clock state.
Synchronous adjustment module receives the synchronization signal from isochronous controller module, the time difference adjusted required for calculating
It is different, system clock module is incrementally adjusted, whether its adjustment process of poll terminates, and process to be adjusted terminates to adjust
As a result isochronous controller module is passed to.
System clock module read operation internal system clock data receives to come as the clock data of this node
It is required from the synchronization in synchronous adjustment module and adjustment is synchronized to data.
Be chosen as the node of master clock only need to according to agreement into meshed network, each node sends synchronization message i.e. in due course
It can.And one includes the following steps: from the synchronizing process of clock node
Step 1: synchronization node network is added, this node is set Stopped state by isochronous controller.
Step 2: ethernet controller module receives the synchronization message of master clock node transmission, reads high precision clock module
Interior clock information calculates the timing differential of this node Yu master clock node, and timing differential is passed to isochronous controller module.
Step 3: isochronous controller module receives timing differential, judges whether the timing differential is greater than preset maximum tolerance
Difference MaxTolerableTime, if more than the system clock state that this node is arranged is Running and transmits timing differential
To the adjustment queue in synchronous adjustment module, adjusts and have recorded this values of disparity from node and master clock in queue, using elder generation
It is stored and is read into fifo mode is first gone out, subsequently into step 4, otherwise enter step the next clock difference heteromerism of 3 waitings
According to.
Step 4: synchronous adjustment module reads adjustment queue, obtains the time difference that need to be adjusted, by modifying system clock
Frequency incrementally adjusts the system clock data in system clock module, and whether poll monitoring adjustment is completed, and after the completion of it, looks into
Adjustment queue is ask, if there is new adjustment task duplication step 4, if adjustment queue is sky, enters step 5.
Step 5: synchronous adjustment module will synchronously complete message and pass to isochronous controller module, and isochronous controller is by this section
The system clock state of point is set as Running&Synchronous.Adjustment is completed, and realizes that clock is synchronous.
The establishment process of entire synchronizing network includes the following steps:
Step 1: each node is once communicated with remaining node in meshed network, is obtained the communication with other nodes and is prolonged
When.
Step 2: choosing one with other the smallest nodes of two nodes average delay as master clock node, remaining node is made
For from clock node.
Step 3: it is each that synchronization node network is added from clock node, it is synchronous with master clock node.Detailed process is for example above-mentioned
Synchronizing step.
Step 4: being synchronously completed from clock node, whole system is in synchronous regime.
After establishing synchronizing network, if each node is received in compliance with disappearing for the adjustment topological structure of IEEE1588 synchronous protocol
Breath, then carry out fault detection, treatment process includes the following steps.
If node failure has occurred:
Step 1: whether confirmation malfunctioning node is master clock node, if master clock node, enters step 2, otherwise enters
Step 3.
Step 2: choosing a master clock node again in remaining two nodes.
Step 3: failure node being rejected from synchronizing network, re-starts synchronization, as shown in Figure 2.
If link failure has occurred:
Step 1: whether confirmation faulty link is related to master clock, if being related to master clock node, enters step 2, otherwise enters
Step 3.
Step 2: as shown in figure 4, intermediate node to be chosen for new master clock node, other two node is used as from clock
Node.
Step 3: failed link being rejected from synchronizing network, re-starts synchronization.
One skilled in the art will appreciate that in addition to realizing system provided by the invention in a manner of pure computer readable program code
It, completely can be by the way that method and step be carried out programming in logic come so that provided by the invention other than system, device and its modules
System, device and its modules are declined with logic gate, switch, specific integrated circuit, programmable logic controller (PLC) and insertion
The form of controller etc. realizes identical program.So system provided by the invention, device and its modules may be considered that
It is a kind of hardware component, and the knot that the module for realizing various programs for including in it can also be considered as in hardware component
Structure；It can also will be considered as realizing the module of various functions either the software program of implementation method can be Hardware Subdivision again
Structure in part.
Specific embodiments of the present invention are described above.It is to be appreciated that the invention is not limited to above-mentioned
Particular implementation, those skilled in the art can make a variety of changes or modify within the scope of the claims, this not shadow
Ring substantive content of the invention.In the absence of conflict, the feature in embodiments herein and embodiment can any phase
Mutually combination.
Claims (10)
1. the operation system clock synchronous method under a kind of 2oo3 redundancy structure characterized by comprising
Delay acquisition step: respectively once being communicated node each in meshed network and remaining node in meshed network,
The communication for obtaining remaining node in each node and meshed network is delayed；
Node division step: being delayed according to the communication of each node of acquisition and remaining node, calculates each node and remaining section
The average communication delay of point, the selection one average the smallest node that is delayed that communicates, will be in meshed networks as master clock node
Remaining node is used as from clock node；
Node synchronizing step: establishing synchronizing network, will be synchronous with master clock node from clock node.
2. the operation system clock synchronous method under 2oo3 redundancy structure according to claim 1, which is characterized in that described
Node synchronizing step includes:
Network creation step: respectively will be added synchronizing network from clock node, will respectively be arranged from the system clock state of clock node
To stop synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtaining step: the synchronization message that master clock node is sent is received, the clock respectively from clock node is successively read
Information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock node
Timing differential；
Diversity judgement step: according to each timing differential from clock node and master clock node of acquisition, successively judge respectively from when
Whether the timing differential of clock node and master clock node is greater than preset maximum tolerance difference MaxTolerableTime: if so,
Then being arranged corresponding from the system clock state of clock node is continued synchronization state Running, and the timing differential is stored
Adjustment queue extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All timing differentials are judged
Afterwards, it is continued to execute into discrepancy adjustment step；
Discrepancy adjustment step: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, when by modification system
Clock frequency incrementally adjusts system clock data, i.e., by the corresponding clock information from clock node of the timing differential that need to be adjusted, with
The clock information of master clock node is synchronous, and whether poll monitoring adjustment is completed, and after the completion of adjustment, whether inquiry adjustment queue
There is the timing differential of new need adjustment: being continued to execute if so, then returning to discrepancy adjustment step；Otherwise, then determine to synchronously complete, obtain
Information must be synchronously completed, is continued to execute into step is synchronously completed；
It synchronously completes step: information is synchronously completed according to acquisition, respectively will be set as same from the system clock state of clock node
Walk completion status Running&Synchronous.
3. the operation system clock synchronous method under 2oo3 redundancy structure according to claim 2, which is characterized in that from when
The system clock state of clock node is when stopping synchronous regime Stopped, from clock node dwelling period to other nodes
Synchronization message is sent, is continued to run from the local clock of clock node, it is same to be not involved in the time in synchronizing network from clock node
Successive step；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588 agreement
Defined method periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, to be reached from clock node from the system clock state of clock node
To synchronous regime, periodically send synchronization message to other nodes, confirm from the synchronous regime of clock node, if discovery from when
Clock node and master clock node lose synchronous regime, then switch to continued synchronization state Running readjustment.
4. the operation system clock synchronous method under 2oo3 redundancy structure according to claim 3, which is characterized in that described
The values of disparity from clock node and master clock is had recorded in adjustment queue, is stored and is read using fifo fifo mode
It takes；
The synchronization message is sent by method as defined in IEEE1588 agreement.
5. the operation system clock synchronous method under 2oo3 redundancy structure according to claim 4, which is characterized in that node
After each node receives the synchronization message sent by method as defined in IEEE1588 agreement in network, fault detection is carried out；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock node,
Then a master clock node is chosen again in remaining two nodes；If not master clock node, then by the node of failure from same
It is rejected in step network, returns to delay acquisition step and continue to execute；If it is not, then continuing to execute node synchronizing step；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if being related to master clock section
Intermediate node in active link, then is chosen for new master clock node by point, and other two node is used as from clock node；If
It is not related to master clock node, then rejects failed link from synchronizing network, returns to delay acquisition step and continue to execute；If it is not,
Then continue to execute node synchronizing step.
6. the operation system clock synchronization system under a kind of 2oo3 redundancy structure characterized by comprising
Delay acquisition module: respectively once being communicated node each in meshed network and remaining node in meshed network,
The communication for obtaining remaining node in each node and meshed network is delayed；
Node division module: being delayed according to the communication of each node of acquisition and remaining node, calculates each node and remaining section
The average communication delay of point, the selection one average the smallest node that is delayed that communicates, will be in meshed networks as master clock node
Remaining node is used as from clock node；
Node synchronization module: establishing synchronizing network, will be synchronous with master clock node from clock node.
7. the operation system clock synchronization system under 2oo3 redundancy structure according to claim 6, which is characterized in that described
Node synchronization module includes:
Network creation module: respectively will be added synchronizing network from clock node, will respectively be arranged from the system clock state of clock node
To stop synchronous regime Stopped, master clock node is enabled to send synchronization message；
Timing differential obtains module: receiving the synchronization message that master clock node is sent, is successively read the clock respectively from clock node
Information is successively calculated respectively from the timing differential of clock node and master clock node, is obtained respectively from clock node and master clock node
Timing differential；
Diversity judgement module: according to each timing differential from clock node and master clock node of acquisition, successively judge respectively from when
Whether the timing differential of clock node and master clock node is greater than preset maximum tolerance difference MaxTolerableTime: if so,
Then being arranged corresponding from the system clock state of clock node is continued synchronization state Running, and the timing differential is stored
Adjustment queue extremely；Otherwise, then the timing differential is skipped, continues to judge next timing differential；All timing differentials are judged
Afterwards, discrepancy adjustment module is triggered；
Discrepancy adjustment module: reading adjustment queue, obtains the timing differential that need to be adjusted according to adjustment queue, when by modification system
Clock frequency incrementally adjusts system clock data, i.e., by the corresponding clock information from clock node of the timing differential that need to be adjusted, with
The clock information of master clock node is synchronous, and whether poll monitoring adjustment is completed, and after the completion of adjustment, whether inquiry adjustment queue
There is the timing differential of new need adjustment: if so, then triggering discrepancy adjustment module；Otherwise, then determine to synchronously complete, acquisition has synchronized
At information, triggering synchronously completes module；
It synchronously completes module: information is synchronously completed according to acquisition, respectively will be set as same from the system clock state of clock node
Walk completion status Running&Synchronous.
8. the operation system clock synchronization system under 2oo3 redundancy structure according to claim 7, which is characterized in that from when
The system clock state of clock node is when stopping synchronous regime Stopped, from clock node dwelling period to other nodes
Synchronization message is sent, is continued to run from the local clock of clock node, it is same to be not involved in the time in synchronizing network from clock node
Successive step；
From the system clock state of clock node be continued synchronization state Running when, from clock node press IEEE1588 agreement
Defined method periodically sends synchronization message to remaining node, participates in the time synchronization adjustment in synchronizing network；
It is when synchronously completing state Running&Synchronous, to be reached from clock node from the system clock state of clock node
To synchronous regime, periodically send synchronization message to other nodes, confirm from the synchronous regime of clock node, if discovery from when
Clock node and master clock node lose synchronous regime, then switch to continued synchronization state Running readjustment.
9. the operation system clock synchronization system under 2oo3 redundancy structure according to claim 8, which is characterized in that described
The values of disparity from clock node and master clock is had recorded in adjustment queue, is stored and is read using fifo fifo mode
It takes；
The synchronization message is sent by method as defined in IEEE1588 agreement.
After each node receives the synchronization message sent by method as defined in IEEE1588 agreement in meshed network, failure inspection is carried out
It surveys；
3 nodes are shared in the meshed network；
The fault detection includes:
Judge whether that node failure occurs: if so, judging whether malfunctioning node is master clock node: if master clock node,
Then a master clock node is chosen again in remaining two nodes；If not master clock node, then by the node of failure from same
It is rejected in step network, Time delay obtains module；If it is not, then triggering node synchronization module；
Judge whether that link failure occurs: if so, judging whether faulty link is related to master clock node: if being related to master clock section
Intermediate node in active link, then is chosen for new master clock node by point, and other two node is used as from clock node；If
It is not related to master clock node, then rejects failed link from synchronizing network, Time delay obtains module；If it is not, then triggering section
Point synchronization module.
10. a kind of computer readable storage medium for being stored with computer program, which is characterized in that the computer program is located
Reason device realizes the operation system clock synchronous method under 2oo3 redundancy structure described in any one of claims 1 to 5 when executing
The step of.
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