CN109217828B - Analog predistortion circuit and analog predistortion time division cancellation method - Google Patents
Analog predistortion circuit and analog predistortion time division cancellation method Download PDFInfo
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/32—Modifications of amplifiers to reduce non-linear distortion
- H03F1/3241—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits
- H03F1/3247—Modifications of amplifiers to reduce non-linear distortion using predistortion circuits using feedback acting on predistortion circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/189—High frequency amplifiers, e.g. radio frequency amplifiers
- H03F3/19—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only
- H03F3/195—High frequency amplifiers, e.g. radio frequency amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/20—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers
- H03F3/21—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only
- H03F3/213—Power amplifiers, e.g. Class B amplifiers, Class C amplifiers with semiconductor devices only in integrated circuits
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/451—Indexing scheme relating to amplifiers the amplifier being a radio frequency amplifier
Abstract
The application provides an analog predistortion circuit and an analog predistortion time division cancellation method. The analog predistortion circuit includes: the device comprises a module control unit, an analog predistortion chip, a radio frequency power amplifier and N adjustable delay units, wherein N is an integer larger than 1, the module control unit is respectively connected with the N adjustable delay units, the module control unit is connected with the analog predistortion chip, the output end of the analog predistortion chip is respectively connected with the input ends of the N adjustable delay units, the output ends of the N adjustable delay units are respectively connected with the input end of the radio frequency power amplifier, and the output end of the radio frequency power amplifier is connected with the input end of the analog predistortion chip. The module control unit controls the whole analog predistortion circuit, so that the analog predistortion circuit can perform time division processing on an input signal, and the analog predistortion chip processes a signal corresponding to the working frequency band of the analog predistortion chip at one moment, thereby improving the cancellation effect of the analog predistortion circuit on the ultra-wideband signal.
Description
Technical Field
The present disclosure relates to the field of circuit technologies, and in particular, to an analog predistortion circuit and an analog predistortion time division cancellation method.
Background
To improve the linearity of the system rf power amplifier, linearization techniques are typically employed. Currently, there are a number of implementations of linearization techniques, one of which is implemented using analog predistortion techniques.
The analog predistortion technique has the following problems when predistortion cancellation is performed on signals: because of the limitation of the maximum working bandwidth of the analog predistortion chip, when the frequency band of the signal needing predistortion cancellation is larger than the maximum working bandwidth of the analog predistortion chip, the analog predistortion technology cannot realize cancellation of the signal, or the cancellation effect is far from the expected effect.
Disclosure of Invention
The application provides an analog predistortion circuit and an analog predistortion time division cancellation method, which are used for improving the cancellation effect of cancellation on signals with frequency bands larger than the maximum working bandwidth of an analog predistortion chip.
In a first aspect, the present application provides an analog predistortion circuit comprising: the device comprises a module control unit, an analog predistortion chip, a radio frequency power amplifier and N adjustable delay units, wherein N is an integer larger than 1, the module control unit is respectively connected with the N adjustable delay units, the module control unit is connected with the analog predistortion chip, the output end of the analog predistortion chip is respectively connected with the input ends of the N adjustable delay units, the output ends of the N adjustable delay units are respectively connected with the input end of the radio frequency power amplifier, and the output end of the radio frequency power amplifier is connected with the input end of the analog predistortion chip.
The module control unit is used for adjusting the analog predistortion chip in T according to the frequency band of the input signal i The method comprises the steps of working frequency ranges at moment and working states of M adjustable delay units in N adjustable delay units, wherein i is 1 to M, and M is an integer not more than N and more than 1.
An analog predistortion chip for the T i At the moment, according to the input signal, the feedback signal and the analog predistortion chip at T i Determining an ith analog predistortion signal according to a working frequency range of moment, and transmitting the ith analog predistortion signal, wherein the frequency range of the ith analog predistortion signal and an analog predistortion chip are in T i The time working frequency band corresponds to the feedback signal is determined according to the output signal of the radio frequency power amplifier.
And the ith adjustable delay unit in the M adjustable delay units is used for receiving the ith analog predistortion signal, and transmitting the ith analog predistortion signal after delaying the ith time length according to the working state of the ith adjustable delay unit.
And the radio frequency power amplifier is used for outputting a cancellation signal after power amplification, wherein the cancellation signal is generated according to the input signal and M analog predistortion signals.
By the analog predistortion circuit, the analog predistortion chip processes a signal corresponding to the self working frequency band at one moment and outputs an analog predistortion signal corresponding to the self working frequency band, so that the analog predistortion chip of the analog predistortion circuit can not generate an expected effect which cannot be achieved by the generated analog predistortion signal due to overlarge frequency band of the signal, and the cancellation effect of the analog predistortion circuit on the ultra-wideband signal is improved.
In one possible implementation manner, the working state of the ith adjustable delay unit in the M adjustable delay units is T i The ith delay unit of the M delay units can be used for, in particular, T i And receiving the ith analog predistortion signal sent by the analog predistortion chip at any time, and sending the analog predistortion signal at a first time after delaying the ith time length. In this scheme, for each of the M adjustable delay units, after the delay time corresponds to the working state of the unit itself, the analog predistortion signals are sent at the same time (i.e., all at the first time), so that each analog predistortion signal can be sent at the same time, that is, the unit (such as the combiner) that receives the analog predistortion signals can receive the M analog predistortion signals at the same time.
In one possible implementation manner, the circuit may further include a combiner, where output ends of the N adjustable delay units are connected to input ends of the combiner, respectively, and output ends of the combiner are connected to input ends of the radio frequency power amplifier, and the combiner is configured to receive the M analog predistortion signals sent by the M adjustable delay units, determine an analog predistortion composite signal according to the M analog predistortion signals, and send the analog predistortion composite signal to the radio frequency power amplifier, where a frequency band of the analog predistortion composite signal is the same as a frequency band of the input signal. According to the scheme, the analog predistortion signals with different frequency bands are synthesized into the analog predistortion synthesized signals through the combiner, so that cancellation of input signals is facilitated.
In one possible implementation manner, the module control unit may be further configured to determine the value of M according to the frequency band of the input signal and the maximum operating bandwidth of the analog predistortion chip.
In one possible implementation manner, the circuit may further include a signal frequency band detection unit, where an output end of the signal frequency band detection unit is connected to an input end of the module control unit, and the signal frequency band detection unit is configured to receive an input signal, detect the input signal to obtain a frequency band of the input signal, and then send the frequency band of the input signal to the module control unit. In the scheme, the frequency band of the input signal is detected through the frequency band detection unit, and the detected frequency band of the input signal is sent to the module control unit, so that the module control unit controls the analog predistortion chip and the N adjustable delay units according to the frequency band of the input signal.
In one possible implementation, the analog predistortion chip described above may be used in particular at T i At the moment, according to the input signal and the analog predistortion chip at T i Determining an ith section signal of an input signal by a moment working frequency band; based on the feedback signal and the analog predistortion chip at T i The method comprises the steps of determining an ith section signal of a feedback signal in a moment working frequency band, determining an ith analog predistortion coefficient according to the ith section signal of an input signal and the ith section signal of the feedback signal, determining an ith analog predistortion signal according to the ith section signal of the input signal and the ith analog predistortion coefficient, and then transmitting the ith analog predistortion signal. Based on the scheme, time division cancellation of the input signal is realized.
In one possible implementation manner, the circuit may further include N memories, where the N memories are respectively connected to the analog predistortion chip, and an ith memory in the N memories is used to store the ith analog predistortion coefficient. According to the scheme, the analog predistortion coefficients are stored, and when the subsequent signals are processed, the analog predistortion coefficients needed when the subsequent signals are processed can be obtained more quickly according to the analog predistortion coefficients stored in the memory, so that the cancellation speed of the signals is improved.
In one possible implementation manner, the adjustable delay unit may include an adjustable delay line and a switch, where the adjustable delay line is used to adjust a delay time length of the adjustable delay unit, and the switch is used to change an operating state of the adjustable delay unit.
In a second aspect, the present application provides a method for performing time-division cancellation on analog predistortion, where the method may be applied to an analog predistortion circuit, where the analog predistortion circuit includes a module control unit, an analog predistortion chip, a radio frequency power amplifier, and N adjustable delay units, where N is an integer greater than 1, and the method includes:
the module control unit adjusts the analog predistortion chip in T according to the frequency band of the input signal i And adjusting the working states of M adjustable delay units in the N adjustable delay units by the module control unit according to the frequency band of the input signal, wherein i is 1 to M, and M is an integer not more than N and more than 1.
Analog predistortion chip described above T i At the moment, according to the input signal, the feedback signal and the analog predistortion chip at T i Determining an ith analog predistortion signal according to a working frequency range of moment, and transmitting the ith analog predistortion signal, wherein the frequency range of the ith analog predistortion signal and an analog predistortion chip are in T i The time working frequency band corresponds to the feedback signal is determined according to the output signal of the radio frequency power amplifier.
The ith adjustable delay unit in the M adjustable delay units receives the ith analog predistortion signal, and transmits the ith analog predistortion signal after delaying the ith time according to the working state of the ith adjustable delay unit.
The radio frequency power amplifier outputs a cancellation signal after power amplification, wherein the cancellation signal is generated according to an input signal and M analog predistortion signals.
According to the analog predistortion time division cancellation method, the analog predistortion chip processes a signal corresponding to the self working frequency band at one moment and outputs an analog predistortion signal corresponding to the self working frequency band, so that the analog predistortion chip of the analog predistortion circuit can not generate an expected effect which cannot be achieved by the generated analog predistortion signal due to the fact that the frequency band of the signal is too large, and the cancellation effect of the analog predistortion circuit on the ultra-wideband signal is improved.
In one possible implementation manner, the working state of the ith adjustable delay unit in the M adjustable delay units is T i The method specifically can include the steps of: the ith adjustable delay unit in the M adjustable delay units is at T i And receiving the ith analog predistortion signal sent by the analog predistortion chip at any time, and sending the analog predistortion signal at a first time after delaying the ith time length. In this scheme, for each of the M adjustable delay units, the analog predistortion signal is transmitted at the same time after the delay time corresponding to the own operating state, so that it is possible to realize that each analog predistortion signal is transmitted at the same time.
In one possible implementation manner, the circuit may further include a combiner, and the method may further include: the combiner receives M analog predistortion signals respectively sent by the M adjustable delay units, and determines an analog predistortion synthesized signal according to the M analog predistortion signals, wherein the frequency band of the analog predistortion synthesized signal is the same as the frequency band of the input signal. According to the scheme, the analog predistortion signals with different frequency bands are synthesized into the analog predistortion synthesized signals through the combiner, so that cancellation of input signals is facilitated.
In one possible implementation manner, the method may further include: and the module control unit determines the value of M according to the frequency band of the input signal and the maximum working bandwidth of the analog predistortion chip.
In a possible implementation manner, the circuit may further include a signal frequency band detection unit, and the method may further include: the signal frequency band detection unit receives an input signal, detects the input signal to obtain a frequency band of the input signal, and then sends the frequency band of the input signal to the module control unit. In the scheme, the frequency band of the input signal is detected through the frequency band detection unit, and the detected frequency band of the input signal is sent to the module control unit, so that the module control unit controls the analog predistortion chip and the N adjustable delay units according to the frequency band of the input signal.
In a possible implementation manner, the analog predistortion chip is arranged at the T i The moment, according to the input signal, the feedback signal and the analog predistortion chip, the chip is at the T i The determining the ith analog predistortion signal according to the working frequency range of the moment specifically may include: analog predistortion chip at T i At the moment, according to the input signal and the analog predistortion chip at T i Determining an ith section signal of an input signal by a moment working frequency band; based on the feedback signal and the analog predistortion chip at T i The method comprises the steps of determining an ith section signal of a feedback signal in a moment working frequency band, determining an ith analog predistortion coefficient according to the ith section signal of an input signal and the ith section signal of the feedback signal, and determining the ith analog predistortion signal according to the ith section signal of the input signal and the ith analog predistortion coefficient. Based on the scheme, time division cancellation of the input signal is realized.
In one possible implementation manner, the circuit may further include N memories, and the method may further include: an ith memory of the N memories stores an ith analog predistortion coefficient. According to the scheme, the analog predistortion coefficients are stored, and when the subsequent signals are processed, the analog predistortion coefficients needed when the subsequent signals are processed can be obtained more quickly according to the analog predistortion coefficients stored in the memory, so that the cancellation speed of the signals is improved.
Drawings
FIG. 1 is a schematic diagram of an analog predistortion circuit provided herein;
FIG. 2 is a schematic diagram of an internal structure of an adjustable delay unit provided in the present application;
fig. 3 is a schematic flow chart of a method for performing analog predistortion time division cancellation.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the present application will be described in further detail with reference to the accompanying drawings.
Fig. 1 is a schematic diagram of an analog predistortion circuit provided in the present application, as shown in fig. 1, the analog predistortion circuit includes: the device comprises a module control unit, an analog predistortion chip, a radio frequency power amplifier and N adjustable delay units, wherein N is an integer larger than 1, the module control unit is respectively connected with the N adjustable delay units, the module control unit is connected with the analog predistortion chip, the output end of the analog predistortion chip is respectively connected with the input ends of the N adjustable delay units, the output ends of the N adjustable delay units are respectively connected with the input end of the radio frequency power amplifier, and the output end of the radio frequency power amplifier is connected with the input end of the analog predistortion chip.
The module control unit is used for adjusting the analog predistortion chip in T according to the frequency band of the input signal i The method comprises the steps of working frequency ranges at moment and working states of M adjustable delay units in N adjustable delay units, wherein i is 1 to M, and M is an integer not more than N and more than 1.
An analog predistortion chip for the T i At the moment, according to the input signal, the feedback signal and the analog predistortion chip at T i Determining an ith analog predistortion signal according to a working frequency range of moment, and transmitting the ith analog predistortion signal, wherein the frequency range of the ith analog predistortion signal and an analog predistortion chip are in T i The time working frequency band corresponds to the feedback signal is determined according to the output signal of the radio frequency power amplifier.
And the ith adjustable delay unit in the M adjustable delay units is used for receiving the ith analog predistortion signal, and transmitting the ith analog predistortion signal after delaying the ith time length according to the working state of the ith adjustable delay unit.
And the radio frequency power amplifier is used for outputting a cancellation signal after power amplification, wherein the cancellation signal is generated according to the input signal and M analog predistortion signals.
By the analog predistortion circuit, the analog predistortion chip processes a signal corresponding to the self working frequency band at one moment and outputs an analog predistortion signal corresponding to the self working frequency band, so that the analog predistortion chip of the analog predistortion circuit can not generate an expected effect which cannot be achieved by the generated analog predistortion signal due to overlarge frequency band of the signal, and the cancellation effect of the analog predistortion circuit on the ultra-wideband signal is improved.
In one possible implementation manner, the working state of the ith adjustable delay unit in the M adjustable delay units is as follows: at T i The ith analog predistortion signal is sent after the moment is in an open state and the ith time is delayed, and the time is T i The time other than the time is in the off state. When the working state of one adjustable delay unit is in a closed state, the adjustable delay unit does not receive the analog predistortion signal. The N-M-reduced adjustable delay units of the N-M-reduced adjustable delay units except the M-reduced adjustable delay units are not adjusted to be in a working state, and the N-M-reduced adjustable delay units are always in a closing state.
It can also be understood that M adjustable delay units of the N adjustable delay units are used to delay the transmission of the analog predistortion signals received respectively. The value of M is determined according to the relationship between the frequency band of the input signal and the maximum operating bandwidth of the analog predistortion chip, which will be described in detail later.
The ith adjustable delay unit of the M adjustable delay units may be specifically used in T i And receiving the ith analog predistortion signal sent by the analog predistortion chip at any time, and sending the analog predistortion signal at a first time after delaying the ith time length.
The above scheme is illustrated below, for example, when M takes a value of 2, the module control unit adjusts the working states of 2 adjustable delay units in the N adjustable delay units, and the adjustable delay units with the adjusted working states are assumed to be the adjustable delay unit 1 and the adjustable delay unit 2, and the module control unit is configured to 1 At the moment, the adjustable delay unit 1 is in an on state, the adjustable delay unit 2 is in an off state (adjustable delayThe unit 2 is in an off state and therefore does not receive the 1 st analog predistortion signal), at which time the adjustable delay unit 1 receives the 1 st analog predistortion signal and the adjustable delay unit 1 transmits the 1 st analog predistortion signal at a time T (which may also be referred to as a first time) after a first time period. At T 2 At the moment, the adjustable delay unit 2 is in an open state, the adjustable delay unit 1 is in a closed state (the adjustable delay unit 1 is in a closed state, and therefore, the 2 nd analog predistortion signal is not received), at this moment, the adjustable delay unit 2 receives the 2 nd analog predistortion signal, and at the time T after delaying the second time period, the adjustable delay unit 2 sends the 2 nd analog predistortion signal, wherein the difference between the time length of the first time period and the time length of the second time period (the first time period is longer than the second time period) is equal to T 1 From moment to T 2 The time lengths of the time instants are the same, so that after the first time delay of the adjustable delay unit 1 and after the second time delay of the adjustable delay unit 2, corresponding analog predistortion signals can be sent at the same time instant (i.e. time instant T or called first time instant).
According to the scheme, the analog predistortion signals are sent at the same moment after the time delay is corresponding to the working state of each of the M adjustable time delay units, so that each analog predistortion signal can be sent at the same moment.
In one possible implementation manner, the circuit may further include a combiner, where output ends of the N adjustable delay units are connected to input ends of the combiner, respectively, and output ends of the combiner are connected to input ends of the radio frequency power amplifier, and the combiner is configured to receive the M analog predistortion signals sent by the M adjustable delay units, determine an analog predistortion composite signal according to the M analog predistortion signals, and send the analog predistortion composite signal to the radio frequency power amplifier, where frequency bands of the M analog predistortion signals are different from each other, and frequency bands of the analog predistortion composite signal are the same as frequency bands of the input signal. For example, when the frequency band of the input signal is 1600MHz-2000MHz, if M is equal to 4 at this time, there are 4 analog predistortion signals, and if four analog predistortion signals are respectively an analog predistortion signal 1, an analog predistortion signal 2, an analog predistortion signal 3, and an analog predistortion signal 4, then the frequency band of the analog predistortion signal 1 may be 1600MHz-1700MHz, the frequency band of the analog predistortion signal 2 may be 1700MHz-1800MHz, the frequency band of the analog predistortion signal 3 may be 1800MHz-1900MHz, the frequency band of the analog predistortion signal 4 may be 1900MHz-2000MHz, and the frequency band of the generated analog predistortion composite signal is 1600MHz-2000 MHz. According to the scheme, the analog predistortion signals with different frequency bands are synthesized into the analog predistortion synthesized signals through the combiner, so that cancellation of input signals is facilitated.
In one possible implementation manner, the module control unit may be further configured to determine the value of M according to the frequency band of the input signal and the maximum operating bandwidth of the analog predistortion chip.
The value of M can be determined by the following formula:i.e. the value of M is the result of the upward rounding of the ratio of the frequency band of the input signal to the maximum operating bandwidth of the analog predistortion chip. For example, when the frequency band of the input signal is 1600MHz-2040MHz and the maximum operating bandwidth of the analog predistortion chip is 100MHz, the +.>
In yet another implementation, the value of M may also be determined by the following formula:k is a certain preset value smaller than the maximum working bandwidth of the analog predistortion chip, namely the value of M is the result of upward rounding of the ratio of the frequency band of the input signal to K. For example, when the frequency band of the input signal is 1600MHz-2040MHz, the maximum working bandwidth of the analog predistortion chip is 100MHz, and the preset value of K is 80MHz, at which time it can be determined
In one possible implementation manner, the circuit may further include a signal frequency band detection unit, where an output end of the signal frequency band detection unit is connected to an input end of the module control unit, and the signal frequency band detection unit is configured to receive an input signal, detect the input signal to obtain a frequency band of the input signal, and then send the frequency band of the input signal to the module control unit. In the scheme, the frequency band of the input signal is detected through the frequency band detection unit, and the detected frequency band of the input signal is sent to the module control unit, so that the module control unit controls the analog predistortion chip and the N adjustable delay units according to the frequency band of the input signal.
In one possible implementation, the above-mentioned analog predistortion chip may specifically determine T by i Analog predistortion signal of time instant:
at T i At the moment, according to the input signal and the analog predistortion chip at T i Determining an ith section signal of an input signal by a moment working frequency band; based on the feedback signal and the analog predistortion chip at T i Determining an ith section signal of a feedback signal in a moment working frequency band, and then determining an ith analog predistortion coefficient according to the ith section signal of an input signal and the ith section signal of the feedback signal; an i-th analog predistortion signal is determined according to an i-th segment signal of the input signal and an i-th analog predistortion coefficient. Wherein the frequency band of the i-th segment signal of the input signal is the same as the frequency band of the i-th segment signal of the feedback signal.
For example, when the frequency band of the input signal is 1800MHz-2000MHz, the frequency band of the feedback signal is 1800MHz-2000MHz, the maximum working bandwidth of the analog predistortion chip is 100MHz, and at this time, M is 2, then:
at T 1 At the moment, the module control unit adjusts the working frequency band of the analog predistortion chip to 1800MHz-1900MHz, the analog predistortion chip determines the frequency band of the 1 st segment signal of the input signal to 1800MHz-1900MHz,the analog predistortion chip determines that the frequency band of the 1 st segment signal of the feedback signal is 1800MHz-1900MHz, then the analog predistortion chip determines the 1 st analog predistortion coefficient according to the 1 st segment signal of the input signal and the 1 st segment signal of the feedback signal, and determines the 1 st analog predistortion signal according to the 1 st segment signal of the input signal and the 1 st analog predistortion coefficient. The frequency band of the 1 st analog predistortion signal is 1800MHz-1900MHz.
At T 2 At the moment, the module control unit adjusts the working frequency band of the analog predistortion chip to 1900MHz-2000MHz, the analog predistortion chip determines that the frequency band of the 2 nd section signal of the input signal is 1900MHz-2000MHz, the analog predistortion chip determines that the frequency band of the 2 nd section signal of the feedback signal is 1900MHz-2000MHz, then the analog predistortion chip determines the 2 nd analog predistortion coefficient according to the 2 nd section signal of the input signal and the 2 nd section signal of the feedback signal, and determines the 2 nd analog predistortion signal according to the 2 nd section signal of the input signal and the 2 nd analog predistortion coefficient. The frequency band of the 2 nd analog predistortion signal is 1900MHz-2000MHz.
In one possible implementation manner, the circuit may further include N memories, where the N memories are respectively connected to the analog predistortion chip, and an ith memory in the N memories is used to store the ith analog predistortion coefficient. According to the scheme, the analog predistortion coefficients are stored, and when the subsequent signals are processed, the analog predistortion coefficients needed when the subsequent signals are processed can be obtained more quickly according to the analog predistortion coefficients stored in the memory, so that the cancellation speed of the signals is improved.
In one possible implementation, the internal structure of the adjustable delay unit may include an adjustable delay line and a switch, where the positions of the adjustable delay line and the switch are interchangeable, as shown in fig. 2. The line 201 is used for receiving the analog predistortion signal sent by the analog predistortion chip, the line 202 is used for sending the analog predistortion signal, the line 203 is used for receiving the signal of the module control unit, and the delay time length of the adjustable delay line and the working state (on or off) of the switch can be adjusted according to the signal of the module control unit. When the switch is in a closed state, the adjustable delay unit is in an open state, and can receive an analog predistortion signal sent by the analog predistortion chip. When the switch is in an off state, the adjustable delay unit is in an off state, and an analog predistortion signal sent by the analog predistortion chip is not received at the moment.
In one possible implementation manner, the analog predistortion circuit may further include a splitter, and the analog predistortion signal sent by the analog predistortion chip is sent to the corresponding adjustable delay unit through the splitter.
In one possible implementation manner, the analog predistortion circuit may further include a delay line, where the delay line is used to prolong the time required for the input signal to be transmitted to the radio frequency power amplifier, so as to enable the input signal to be cancelled with the analog predistortion signal output by the analog predistortion chip.
In one possible implementation, the analog predistortion circuit described above may further include one or more couplers, which may be in the position shown in fig. 1, the couplers being used to split or combine the signals.
The specific implementation of the analog predistortion circuit shown in fig. 1 is illustrated in one specific embodiment.
In fig. 1, it is assumed that the frequency band of the input signal is 1800MHz-2040MHz, the frequency band of the feedback signal is 1800MHz-2040MHz, the maximum operating bandwidth of the analog predistortion chip is 100MHz, and the n value is 5 (i.e., the circuit includes 5 adjustable delay units, such as an adjustable delay unit 1, an adjustable delay unit 2, an adjustable delay unit 3, an adjustable delay unit 4, and an adjustable delay unit 5, respectively, the circuit includes 5 memories, such as a memory 1, a memory 2, a memory 3, a memory 4, and a memory 5, respectively), the input signal enters the signal frequency band detection unit through the coupler 1, and after the signal frequency band detection unit receives the input signal, the frequency band of the input signal is 1800MHz-2040MHz, which is detected, and the frequency band is sent to the module control unit.
After receiving the frequency band of the input signal, the module control unit performs the operation according to the frequency band of the input signal and the maximum operating bandwidth of the analog predistortion signal,determining M to be 3 (according to the formulaTherefore, the module control unit adjusts the working states of 3 adjustable delay units in the N adjustable delay units, and the adjusted adjustable delay units are the adjustable delay unit 1, the adjustable delay unit 2 and the adjustable delay unit 3, and at this time, the adjustable delay unit 4 and the adjustable delay unit 5 are in a closed state, that is, the adjustable delay unit 4 and the adjustable delay unit 5 are not started for the input signal. The module control unit also adjusts the analog predistortion chip in T according to the frequency band of the input signal 1 The working frequency band at the moment is 1800MHz-1880MHz, at T 2 The frequency band at the moment is 1880MHz-1960MHz, at T 3 The frequency band at the moment is 1960MHz-2040MHz (in the example, the frequency band equipartition of the input signal is processed, and the specific division method of the working frequency band of the analog predistortion chip at each moment can be adjusted according to actual needs).
The analog predistortion chip receives the input signal and the feedback signal, at T 1 At the moment, the working frequency band of the analog predistortion chip is 1800MHz-1880MHz, so that the frequency band of the 1 st section signal of the input signal is 1800MHz-1880MHz, the frequency band of the 1 st section signal of the feedback signal is 1800MHz-1880MHz, the 1 st analog predistortion coefficient is determined according to the 1 st section signal of the input signal and the 1 st section signal of the feedback signal, the 1 st analog predistortion signal is determined according to the 1 st section signal of the input signal and the 1 st analog predistortion coefficient, the 1 st analog predistortion coefficient is stored in the memory 1, the 1 st analog predistortion signal is sent to the adjustable delay unit 1, and the frequency band of the 1 st analog predistortion signal is 1800MHz-1880MHz. And at this time, the adjustable delay unit 1 is in an on state, and the other adjustable delay units are in an off state.
At T 2 At the moment, the working frequency band of the analog predistortion chip is 1880MHz-1960MHz, so that the frequency band of the 2 nd section signal of the input signal is 1880MHz-1960MHz, the frequency band of the 2 nd section signal of the feedback signal is 1880MHz-1960MHz, and the 2 nd section signal of the input signal and the 2 nd section signal of the feedback signal are determinedThe method comprises the steps of determining a 2 nd analog predistortion coefficient of a signal, determining a 2 nd analog predistortion signal according to a 2 nd section signal of an input signal and the 2 nd analog predistortion coefficient, storing the 2 nd analog predistortion coefficient into a memory 2, and then sending the 2 nd analog predistortion signal to an adjustable delay unit 2, wherein the frequency band of the 2 nd analog predistortion signal is 1880MHz-1960MHz. And at this time, the adjustable delay unit 2 is in an open state, and the other adjustable delay units are in a closed state.
At T 3 At the moment, the working frequency band of the analog predistortion chip is 1960MHz-2040MHz, so that the frequency band of the 3 rd section signal of the input signal is 1960MHz-2040MHz, the frequency band of the 3 rd section signal of the feedback signal is 1960MHz-2040MHz, the 3 rd analog predistortion coefficient is determined according to the 3 rd section signal of the input signal and the 3 rd section signal of the feedback signal, the 3 rd analog predistortion signal is determined according to the 3 rd section signal of the input signal and the 3 rd analog predistortion coefficient, meanwhile, the 3 rd analog predistortion coefficient is stored in the memory 3, the 3 rd analog predistortion signal is sent to the adjustable delay unit 3, and the frequency band of the 2 nd analog predistortion signal is 1960MHz-2040MHz. And at this time, the adjustable delay unit 3 is in an on state, and the other adjustable delay units are in an off state.
Let T be 1 Time of day and T 2 Time interval of 0.01 second, T 2 Time of day and T 3 The time interval is 0.01 second, then after the adjustable delay unit 1 receives the 1 st analog predistortion signal, the 1 st analog predistortion signal is sent to the combiner after the delay time is 0.02 seconds, after the adjustable delay unit 2 receives the 2 nd analog predistortion signal, the 2 nd analog predistortion signal is sent to the combiner after the delay time is 0.01 seconds, after the adjustable delay unit 3 receives the 3 rd analog predistortion signal, the 3 rd analog predistortion signal is directly sent to the combiner without delay time, of course, the adjustable delay unit 3 delays, and then the adjustable delay unit 1 and the adjustable delay unit 2 correspondingly delay time with the same time length.
The combiner receives the 1 st analog predistortion signal, the 2 nd analog predistortion signal and the 3 rd analog predistortion signal at the same time, and generates an analog predistortion synthesized signal according to the 1 st analog predistortion signal, the 2 nd analog predistortion signal and the 3 rd analog predistortion signal, the frequency band of the analog predistortion synthesized signal is 1800MHz-2040MHz, and then the combiner sends the analog predistortion synthesized signal to the coupler 2.
The analog predistortion synthesized signal is canceled with the input signal transmitted by the delay line in the coupler 2 to generate a cancellation signal, the frequency band of the cancellation signal is 1800MHz-2040MHz, and the cancellation signal enters the radio frequency power amplifier.
The radio frequency power amplifier amplifies the power of the cancellation signal and outputs the cancellation signal.
According to the analog predistortion circuit, the analog predistortion chip processes a signal corresponding to the self working frequency band at one moment and outputs the analog predistortion signal corresponding to the self working frequency band, so that the analog predistortion chip of the analog predistortion circuit cannot generate an analog predistortion signal which cannot achieve an expected effect due to overlarge frequency band of the signal, and the cancellation effect of the analog predistortion circuit on the ultra-wideband signal is improved.
Based on the same conception, the application provides an analog predistortion time division cancellation method which can be applied to an analog predistortion circuit, wherein the analog predistortion circuit comprises a module control unit, a radio frequency power amplifier and N analog predistortion chips, and N is an integer larger than 1. Fig. 3 is a schematic flow chart of a method for time-division cancellation of an analog predistortion line provided in the present application, as shown in fig. 3, the method includes:
step 301, a module control unit respectively adjusts working states of M adjustable delay units in N adjustable delay units according to frequency bands of input signals, and adjusts an analog predistortion chip in T i The working frequency band at the moment.
Wherein i is taken from 1 to M, M is an integer not more than N and more than 1.
Step 302, the analog predistortion chip is set forth above as T i At the moment, according to the input signal, the feedback signal and the analog predistortion chip at T i Determining the ith analog predistortion according to the working frequency range of the momentA signal.
Wherein the frequency band of the ith analog predistortion signal and the analog predistortion chip are in T i The time working frequency band corresponds to the feedback signal is determined according to the output signal of the radio frequency power amplifier.
Step 303, the analog predistortion chip is set forth above as T i At the moment, the ith analog predistortion signal is transmitted.
And 304, the ith adjustable delay unit in the M adjustable delay units receives the ith analog predistortion signal, and transmits the ith analog predistortion signal after delaying the ith time according to the working state of the ith adjustable delay unit.
In step 305, the rf power amplifier amplifies the power of the cancellation signal and outputs the amplified cancellation signal.
Wherein the cancellation signal is generated from the input signal and the M analog predistortion signals.
In one possible implementation manner, the working state of the ith adjustable delay unit in the M adjustable delay units is as follows: at T i And the ith analog predistortion signal is sent after the ith time is in an open state and the ith time is delayed. The step 304 may specifically include: the ith adjustable delay unit in the M adjustable delay units is at T i And receiving the ith analog predistortion signal sent by the analog predistortion chip at any time, and sending the analog predistortion signal at a first time after delaying the ith time length.
In a possible implementation manner, before the step 301, the module control unit determines the value of M according to the frequency band of the input signal and the maximum operating bandwidth of the analog predistortion chip.
In a possible implementation manner, the circuit may further include a signal frequency band detection unit, and before the step 301, the signal frequency band detection unit receives an input signal, detects the input signal to obtain a frequency band of the input signal, and then sends the frequency band of the input signal to the module control unit.
In one possible implementation manner, the step 302 may specifically include: analog predistortion chip at T i According to the time of dayInput signal and analog predistortion chip at T i Determining an ith section signal of an input signal by a moment working frequency band; based on the feedback signal and the analog predistortion chip at T i The method comprises the steps of determining an ith section signal of a feedback signal in a moment working frequency band, determining an ith analog predistortion coefficient according to the ith section signal of an input signal and the ith section signal of the feedback signal, and determining the ith analog predistortion signal according to the ith section signal of the input signal and the ith analog predistortion coefficient.
In a possible implementation manner, the circuit may further include N memories, and after the step 302, before the step 304, may further include: an ith memory of the N memories stores an ith analog predistortion coefficient.
The specific implementation process and beneficial effects of the analog predistortion time division cancellation method shown in fig. 3 are the same as those in the foregoing analog predistortion circuit embodiment, and reference is made to the foregoing description, and no further description is given here.
It will be apparent to those skilled in the art that various modifications and variations can be made in the present application without departing from the spirit or scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims and the equivalents thereof, the present application is intended to cover such modifications and variations.
Claims (9)
1. The analog predistortion circuit is characterized by comprising a module control unit, an analog predistortion chip, a radio frequency power amplifier and N adjustable delay units, wherein N is an integer greater than 1;
the module control unit is respectively connected with the N adjustable delay units, the module control unit is connected with the analog predistortion chip, the output end of the analog predistortion chip is respectively connected with the input ends of the N adjustable delay units, the output ends of the N adjustable delay units are respectively connected with the input ends of the radio frequency power amplifier, and the output end of the radio frequency power amplifier is connected with the input end of the analog predistortion chip;
the module control listA unit for adjusting the analog predistortion chip at T according to the frequency band of the input signal i The working frequency range at the moment and the working state of M adjustable delay units in the N adjustable delay units are adjusted, wherein i is 1 to M, and M is an integer not more than N and more than 1;
the analog predistortion chip is used for processing the signal at the T i Time according to the input signal and the analog predistortion chip at the T i Determining an ith section signal of the input signal by a time working frequency band; according to the feedback signal and the analog predistortion chip at the T i Determining an ith section signal of the feedback signal by a moment working frequency band; then determining an ith analog predistortion coefficient according to an ith section signal of the input signal and an ith section signal of the feedback signal; determining the ith analog predistortion signal according to the ith segment signal of the input signal and the ith analog predistortion coefficient, and transmitting the ith analog predistortion signal, wherein the frequency band of the ith analog predistortion signal and the analog predistortion chip are arranged in the T i The working frequency range at the moment corresponds to the feedback signal which is determined according to the output signal of the radio frequency power amplifier;
the ith adjustable delay unit in the M adjustable delay units is used for receiving the ith analog predistortion signal, and transmitting the ith analog predistortion signal after delaying the ith time length according to the working state of the ith adjustable delay unit;
the radio frequency power amplifier is used for amplifying power of cancellation signals and outputting the cancellation signals, and the cancellation signals are generated according to the input signals and M analog predistortion signals.
2. The circuit of claim 1, wherein an i-th one of the M adjustable delay units is operated at the T i The ith analog predistortion signal is sent after the ith time is in an open state and the ith time is delayed;
the ith adjustable delay in the M adjustable delay unitsTime unit, in particular for, at said T i And receiving the ith analog predistortion signal transmitted by the analog predistortion chip at moment, and transmitting the analog predistortion signal at a first moment after delaying the ith time length.
3. The circuit according to claim 1 or 2, further comprising a combiner, wherein the outputs of the N adjustable delay units are respectively connected to the inputs of the combiner, and the outputs of the combiner are connected to the inputs of the radio frequency power amplifier;
the combiner is configured to receive M analog predistortion signals sent by the M adjustable delay units, determine an analog predistortion synthesized signal according to the M analog predistortion signals, and send the analog predistortion synthesized signal to the radio frequency power amplifier, where a frequency band of the analog predistortion synthesized signal is the same as a frequency band of the input signal.
4. The circuit of claim 1 or 2, wherein the module control unit is further configured to determine the value of M according to a frequency band of the input signal and a maximum operating bandwidth of the analog predistortion chip.
5. The circuit according to claim 1 or 2, further comprising a signal band detection unit, an output of the signal band detection unit being connected to an input of the module control unit;
the signal frequency band detection unit is used for receiving the input signal, detecting the frequency band of the input signal, and sending the frequency band of the input signal to the module control unit.
6. The circuit of claim 1, further comprising N memories, each connected to the analog predistortion chip;
and the ith memory in the N memories is used for storing the ith analog predistortion coefficient.
7. The analog predistortion time division cancellation method is characterized by being applied to an analog predistortion circuit, wherein the analog predistortion circuit comprises a module control unit, an analog predistortion chip, a radio frequency power amplifier and N adjustable delay units, and N is an integer greater than 1, and the method comprises the following steps:
the module control unit adjusts the analog predistortion chip in T according to the frequency band of the input signal i The module control unit adjusts the working states of M adjustable delay units in the N adjustable delay units according to the frequency band of the input signal, wherein i is from 1 to M, and M is an integer not more than N and more than 1;
the analog predistortion chip is arranged at the T i Time according to the input signal and the analog predistortion chip at the T i Determining an ith section signal of the input signal by a time working frequency band; according to the feedback signal and the analog predistortion chip at the T i Determining an ith section signal of the feedback signal in a moment working frequency range, and then determining an ith analog predistortion coefficient according to the ith section signal of the input signal and the ith section signal of the feedback signal; determining the ith analog predistortion signal according to the ith segment signal of the input signal and the ith analog predistortion coefficient, and transmitting the ith analog predistortion signal, wherein the frequency band of the ith analog predistortion signal and the analog predistortion chip are arranged in the T i The working frequency range at the moment corresponds to the feedback signal which is determined according to the output signal of the radio frequency power amplifier;
an ith adjustable delay unit in the M adjustable delay units receives the ith analog predistortion signal, and transmits the ith analog predistortion signal after delaying the ith time length according to the working state of the ith adjustable delay unit;
the radio frequency power amplifier outputs a cancellation signal after power amplification, and the cancellation signal is generated according to the input signal and M analog predistortion signals.
8. The method of claim 7, wherein an i-th adjustable delay unit of the M adjustable delay units is operated at the T i The ith analog predistortion signal is sent after the ith time is in an open state and the ith time is delayed;
the ith adjustable delay unit in the M adjustable delay units receives the ith analog predistortion signal, and sends the ith analog predistortion signal after delaying the ith time length according to the working state of the ith adjustable delay unit, and the method comprises the following steps:
an ith adjustable delay unit in the M adjustable delay units is arranged at the T i And receiving the ith analog predistortion signal transmitted by the analog predistortion chip at moment, and transmitting the analog predistortion signal at a first moment after delaying the ith time length.
9. The method of claim 7 or 8, wherein the method further comprises:
and the module control unit determines the value of M according to the frequency band of the input signal and the maximum working bandwidth of the analog predistortion chip.
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