CN109216442A - Semiconductor structure manufacturing method - Google Patents
Semiconductor structure manufacturing method Download PDFInfo
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- CN109216442A CN109216442A CN201811038479.2A CN201811038479A CN109216442A CN 109216442 A CN109216442 A CN 109216442A CN 201811038479 A CN201811038479 A CN 201811038479A CN 109216442 A CN109216442 A CN 109216442A
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- layer
- ohmic contact
- barrier layer
- semiconductor structure
- structure manufacturing
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 29
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 27
- 230000004888 barrier function Effects 0.000 claims abstract description 51
- 239000000758 substrate Substances 0.000 claims abstract description 22
- 230000000737 periodic effect Effects 0.000 claims abstract description 13
- 239000010410 layer Substances 0.000 claims description 127
- 239000011241 protective layer Substances 0.000 claims description 25
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000002184 metal Substances 0.000 claims description 23
- 229920002120 photoresistant polymer Polymers 0.000 claims description 9
- 230000014759 maintenance of location Effects 0.000 claims description 8
- 238000004151 rapid thermal annealing Methods 0.000 claims description 7
- 229910052710 silicon Inorganic materials 0.000 claims description 7
- 239000010703 silicon Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 4
- 238000001816 cooling Methods 0.000 claims description 4
- 229910052732 germanium Inorganic materials 0.000 claims description 4
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 3
- 229910052760 oxygen Inorganic materials 0.000 claims description 3
- 239000001301 oxygen Substances 0.000 claims description 3
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 claims description 2
- 150000002500 ions Chemical class 0.000 description 33
- 239000000463 material Substances 0.000 description 14
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 12
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 10
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 10
- 238000000137 annealing Methods 0.000 description 10
- 229910002601 GaN Inorganic materials 0.000 description 9
- 229910002704 AlGaN Inorganic materials 0.000 description 8
- -1 InN Chemical compound 0.000 description 8
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 8
- 238000002347 injection Methods 0.000 description 7
- 239000007924 injection Substances 0.000 description 7
- 238000000034 method Methods 0.000 description 7
- 229910052759 nickel Inorganic materials 0.000 description 6
- 229910052581 Si3N4 Inorganic materials 0.000 description 5
- 239000000956 alloy Substances 0.000 description 5
- 239000000203 mixture Substances 0.000 description 5
- 239000000377 silicon dioxide Substances 0.000 description 5
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 5
- 229910017083 AlN Inorganic materials 0.000 description 4
- PIGFYZPCRLYGLF-UHFFFAOYSA-N Aluminum nitride Chemical compound [Al]#N PIGFYZPCRLYGLF-UHFFFAOYSA-N 0.000 description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 229910052737 gold Inorganic materials 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- 239000012071 phase Substances 0.000 description 4
- 229910052697 platinum Inorganic materials 0.000 description 4
- 238000005036 potential barrier Methods 0.000 description 4
- 230000005533 two-dimensional electron gas Effects 0.000 description 4
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 3
- 229910045601 alloy Inorganic materials 0.000 description 3
- 239000004411 aluminium Substances 0.000 description 3
- 229910052782 aluminium Inorganic materials 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 239000010936 titanium Substances 0.000 description 3
- 229910052719 titanium Inorganic materials 0.000 description 3
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- 239000002253 acid Substances 0.000 description 2
- 238000000354 decomposition reaction Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 229910003460 diamond Inorganic materials 0.000 description 2
- 239000010432 diamond Substances 0.000 description 2
- 238000005530 etching Methods 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 229910052594 sapphire Inorganic materials 0.000 description 2
- 239000010980 sapphire Substances 0.000 description 2
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 239000000243 solution Substances 0.000 description 2
- 229910001020 Au alloy Inorganic materials 0.000 description 1
- 206010016825 Flushing Diseases 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005669 field effect Effects 0.000 description 1
- 238000011010 flushing procedure Methods 0.000 description 1
- 239000003292 glue Substances 0.000 description 1
- 239000003353 gold alloy Substances 0.000 description 1
- 239000007943 implant Substances 0.000 description 1
- 238000001883 metal evaporation Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 1
- 238000004528 spin coating Methods 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/45—Ohmic electrodes
- H01L29/452—Ohmic electrodes on AIII-BV compounds
- H01L29/454—Ohmic electrodes on AIII-BV compounds on thin film AIII-BV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/2654—Bombardment with radiation with high-energy radiation producing ion implantation in AIIIBV compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- High Energy & Nuclear Physics (AREA)
- Ceramic Engineering (AREA)
- Health & Medical Sciences (AREA)
- Toxicology (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The application proposes a kind of semiconductor structure manufacturing method, comprising: provides substrate, sequentially forms buffer layer and barrier layer over the substrate；Dielectric layer is formed on the barrier layer；Ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer；Carry out periodic rapid thermo anneal.The semiconductor structure manufacturing method that the application is proposed can be effectively reduced ohmic contact resistance, increase the Performance And Reliability of device.
Description
Technical field
The present invention relates to technical field of manufacturing semiconductors, more particularly to a kind of semiconductor structure manufacturing method.
Background technique
As the representative of third generation semiconductor material, gallium nitride (GaN) has many excellent characteristics, high critical breakdown potential
Field, high electron mobility, high two-dimensional electron gas and good high temperature operation capability etc..The third generation based on gallium nitride is partly led
Application has been obtained in body structure, such as high electron mobility transistor (HEMT), hetero-structure field effect transistor (HFET),
Especially high-power and high-frequency field is needed to have a clear superiority in radio frequency, microwave etc..
The critical technological point of nitride HEMT first is that the formation of low resistance Ohmic contact.For operator at high frequencies
Part, contact resistance must be as low as possible, and the contact resistance refers in metal electrode and channel between 2DEG (two-dimensional electron gas)
All-in resistance.Under normal conditions, in order to reduce metal electrode with the contact resistance between semiconductor material, semiconductor is generally required
Carrier mobility with very high doping concentration and appropriateness.But in conventional AlGaN/GaN HEMT structure, AlGaN
Excessively high doping concentration will damage the mobility of 2DEG in channel in layer, and therefore reduce the performance of device.Meanwhile AlGaN material
The broad-band gap feature of material is but also it is very difficult to obtain good Ohmic contact.Ohmic contact is formed in AlGaN potential barrier,
The specific metal layer of vapor deposition is usually required, and is aided with high-temperature annealing process.But nonetheless, the resistance of generated Ohmic contact
Rate is still higher.
Summary of the invention
The application proposes a kind of semiconductor structure manufacturing method, comprising:
Substrate is provided, sequentially forms buffer layer and barrier layer over the substrate；
Protective layer is formed on the barrier layer；
Ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer；
Carry out periodic rapid thermo anneal.
In one embodiment, the protective layer thickness is 10nm-100nm.
In one embodiment, ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer specifically to wrap
It includes:
Mask layer is formed on the protective layer, and defines ohmic contact regions；
Remove the mask layer of ohmic contact regions；
Ion implanting is carried out to ohmic contact regions, makes to need to form Ohmic contact in ion implanting to the barrier layer
In region.
In one embodiment, the mask layer is metal or photoresist.If carrying out fast speed heat using photoresist
It needs to remove it before annealing.
In one embodiment, a rapid thermal annealing period includes be rapidly heated phase, temperature retention period and fast cooling
Phase.
In one embodiment, the time of the temperature retention period is 1s-30s, and the temperature of temperature retention period is greater than 1300
℃。
In one embodiment, the ion is one or more of silicon, oxygen, Germanium.
The application also proposes another semiconductor structure manufacturing method, comprising:
Substrate is provided, sequentially forms buffer layer and barrier layer over the substrate；
Ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer；
Protective layer is formed on the barrier layer；
Carry out periodic rapid thermo anneal.
In one embodiment, ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer specifically to wrap
It includes:
Mask layer is formed on the barrier layer, and defines ohmic contact regions；
Remove the mask layer of ohmic contact regions；
Ion implanting is carried out to ohmic contact regions, makes to need to form Ohmic contact in ion implanting to the barrier layer
In region.
Remove remaining mask layer；
In one embodiment, the protective layer be metal layer or dielectric layer or be metal layer or dielectric layer heap
It is folded.The mask layer can be photoresist, metal or dielectric layer.
The semiconductor structure manufacturing method that the application is proposed can be effectively reduced ohmic contact resistance, increase device
Performance And Reliability.
Detailed description of the invention
Fig. 1 is semiconductor structure manufacturing method flow chart provided by one embodiment；
Fig. 2-Fig. 4 is the schematic diagram for indicating the semiconductor structure of manufacture one embodiment；
Fig. 5 is the relational graph of temperature and time in annealing process；
Fig. 6 is semiconductor structure manufacturing method flow chart provided by one embodiment；
Fig. 7-Fig. 9 is the schematic diagram for indicating the semiconductor structure of manufacture one embodiment.
Specific embodiment
Semiconductor structure manufacturing method proposed by the present invention is made below in conjunction with the drawings and specific embodiments further detailed
Explanation.According to following explanation and claims, advantages and features of the invention will be become apparent from.It should be noted that attached drawing is adopted
With very simplified form and using non-accurate ratio, only to facilitate, lucidly aid in illustrating the embodiment of the present invention
Purpose.
Embodiment one
Fig. 1-Fig. 4 is please referred to, semiconductor structure manufacturing method provided by the present embodiment includes:
S10: substrate is provided, sequentially forms buffer layer and barrier layer over the substrate.
Specifically, the substrate material includes but is not limited to sapphire, silicon carbide, silicon, diamond, GaAs, gallium nitride
With the materials such as aluminium nitride.The substrate 1 with a thickness of 50 to 1000 microns.Buffer layer 2 can be formed on the substrate 1, is used for
The path of electric current flowing is provided.The buffer layer 2 can be one or more materials such as GaN, InN, AlN, AlGaN or InGaN
Material combination.The buffer layer 2 with a thickness of 50 to 10000 nanometers.Barrier layer 3, the potential barrier can be formed on the buffer layer 2
Layer 3 can be AlGaN, ScAlN, InAlN, the one or more superposition of the alloy materials such as InGaAlN.The thickness of the barrier layer 3
Degree is 3 to 100 nanometers.Buffer layer 2 is formed on substrate 1 and the structure of barrier layer 3 is as shown in Figure 2.
S20: ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer.
The Ohmic contact refers to that barrier layer 3 is contacted with source electrode and drain electrode metal to be formed to be formed by.The source
The region that pole and drain electrode are contacted with the barrier layer 3 can be determined by preparatory design.Specifically, can be in the potential barrier
Mask layer 4 is formed on layer 3, the mask layer 4 can be photoresist, can also be metal layer or dielectric layer.The mask layer 4 is
When photoresist, by techniques such as spin coating, exposure, baking, development, flushings, removal needs to form the photoetching in the region of Ohmic contact
Glue, to define ohmic contact regions.The mask layer be metal layer or dielectric layer when, the metal can for nickel, platinum, aluminium,
The alloy that any one or more in titanium etc. forms, the medium can be silicon nitride or silica.Correspondingly, in order to fixed
Justice goes out ohmic contact regions, it is also desirable to carry out photoetching, metal evaporation or chemical vapor-phase growing, etching etc. technique to expose Europe
Nurse contact area.After the mask layer removal of ohmic contact regions, implant ions into barrier layer and buffer layer, since non-ohm connects
Touching area is covered by mask layer, therefore ion will not be injected into non-ohmic contact area, and only ohmic contact regions have ion implanting.
The ion is n-type doping ion, can be single ionic, such as silicon ion, oxonium ion, germanium ion, be also possible to these yuan
The codope of element.The dosage of ion implanting is greater than 1016/cm2, the energy of injection is greater than 150keV, guarantee buffer layer and barrier layer
Enough Doped ions can be absorbed, temperature when injection is between room temperature between 300 DEG C.Device architecture after ion implanting is such as
Shown in Fig. 3.
S30: protective layer is formed on the barrier layer.
It before forming the protective layer 5, needs first to remove remaining mask layer 4, can be removed using wet etching
Remaining mask layer 4.After mask layer removal, barrier layer 5 is formed on the barrier layer 3, is formed described in structure as shown in Figure 4
Protective layer material can be the stacking of metal layer or dielectric layer or metal layer and dielectric layer.The metal can be the gold
Belong to can for tungsten, nickel, in platinum any one or more composition alloy, the medium can be silicon nitride or silica,
It is also possible to the stacking of silicon nitride or silica.PVD (physical vapour deposition (PVD)) or PECVD (plasma can be used
Enhance chemical vapor deposition) form the protective layer 5.By depositing protective layer 5 on barrier layer, gallium nitride material can be prevented
Decomposed is generated at high temperature.When unprotect layer 5, the decomposition temperature of gallium nitride is about 900 DEG C or so, after protective layer 5 covers,
It is 1500 DEG C or so that the decomposition temperature of gallium nitride, which mentions,.Therefore the annealing temperature during subsequent anneal can be improved, more to have
Effect activates the ion injected and is formed and mixed.
S40: periodic rapid thermo anneal is carried out.
Damage when in order to activate the ion of injection and repair ion implanting to lattice needs to carry out whole wafer quick
Thermal annealing.In the present embodiment, using periodic rapid thermo anneal as shown in Figure 5, wherein abscissa indicates time (ms), indulges
Coordinate representation temperature (DEG C).One annealing cycle T=T1+T2+T3, T1 are to be rapidly heated the phase, and T2 is temperature retention period, and T3 is fast
Fast cooldown period.During annealing, temperature is quickly risen to 1300 DEG C or more from 700 DEG C within the T1 period, and T2's
This temperature is kept in period, and temperature quickly then will drop to 700 DEG C hereinafter, until carrying out again quickly in the T3 period
Heating, and repeat above-mentioned heating and cooling operation.The T1 is 10s-60s, and the T2 is 1s-30s, and the T3 is 10s-60s.
By constantly carrying out periodic rapid thermal annealing, can effectively activate the ion of injection, make the source electrode being subsequently formed and
Drain electrode obtains good Ohmic contact, and contact resistance is effectively reduced.
After periodic rapid thermal annealing, acid etching solution can be used and remove the protective layer 5, and in barrier layer
It is respectively formed source electrode, drain and gate on 3, continues the production of transistor arrangement.The source electrode and drain electrode is located at institute
State the two sides of grid.The grid can be the metal laminated of the compositions such as nickel, gold, platinum, the source electrode and drain electrode can for titanium,
The alloy of any a variety of compositions in the metals such as aluminium, nickel, gold.
Embodiment two
Fig. 6-9 is please referred to, semiconductor structure manufacturing method provided by the present embodiment includes:
S100: substrate is provided, sequentially forms buffer layer and barrier layer over the substrate.
Specifically, 1 material of substrate includes but is not limited to sapphire, silicon carbide, silicon, diamond, GaAs, gallium nitride
With the materials such as aluminium nitride.The substrate 1 with a thickness of 50 to 1000 microns.Buffer layer 2 can be formed on the substrate 1, is used for
The path of electric current flowing is provided.The buffer layer 2 can be one or more materials such as GaN, InN, AlN, AlGaN or InGaN
Material combination.The buffer layer 2 with a thickness of 50 to 10000 nanometers.Barrier layer 3, the potential barrier can be formed on the buffer layer 2
Layer 3 can be AlGaN, ScAlN, InGaAlN, the one or more superposition of the alloy materials such as InAlN.The thickness of the barrier layer 3
Degree is 3 to 100 nanometers.Buffer layer 2 is formed on substrate 1 and the structure of barrier layer 3 is as shown in Figure 7.
S200: protective layer is formed on the barrier layer.
Specifically, forming protective layer 5 on the barrier layer 3, the protective layer 5 covers the barrier layer 3, is formed as schemed
Structure shown in 8.The protective layer 5 can perhaps silica be also possible to the heap of silicon nitride or silica with silicon nitride
It is folded.The protective layer 5 with a thickness of 10nm-100nm, reduce the subsequent influence to ion implanting to the greatest extent.PECVD can be used
(plasma enhanced chemical vapor deposition) forms the protective layer.
S300: ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer.
The Ohmic contact refers to that barrier layer 3 is contacted with source electrode and drain electrode to be formed to be formed by.The source electrode and
The region that drain electrode is contacted with the barrier layer can be determined by preparatory design.Specifically, can be on the protective layer 5
Mask layer 4 is formed, the mask layer 4 can be photoresist, can also be metal layer.Technique as same embodiment one kind can be used
Ohmic contact regions are defined, and remove the mask layer 4 of ohmic contact regions, form structure as shown in Figure 9.Ohmic contact regions do not have
Mask layer 4 covers, and energetic ion pierce through the protection layer 5 can be used and be injected into barrier layer 3 and buffer layer 2, since non-ohm connects
Touching area is covered by mask layer 5, therefore ion will not be injected into non-ohmic contact area, and only ohmic contact regions have ion note
Enter.The ion is n-type doping ion, can be single ionic, such as silicon ion, be also possible to silicon ion, germanium ion, oxygen from
The codope of son.It injects dosage and energy the case where being all larger than embodiment one of ion, temperature when injection is between room temperature to 300
Between DEG C.
S400: periodic rapid thermo anneal is carried out.
Damage when in order to activate the ion of injection and repair ion implanting to lattice needs to carry out whole wafer quick
Thermal annealing.In the present embodiment, using periodic rapid thermo anneal as shown in Figure 5, wherein abscissa indicates time (ms), indulges
Coordinate representation temperature (DEG C).One annealing cycle T=T1+T2+T3, T1 are to be rapidly heated the phase, and T2 is temperature retention period, and T3 is fast
Fast cooldown period.During annealing, temperature is quickly risen to 1300 DEG C or more from 700 DEG C within the T1 period, and T2's
This temperature is kept in period, and temperature quickly then will drop to 700 DEG C hereinafter, until carrying out again quickly in the T3 period
Heating, and repeat above-mentioned heating and cooling operation.The T1 is 10s-60s, and the T2 is 1s-30s, and the T3 is 10s-60s.
By constantly carrying out periodic rapid thermal annealing, can effectively activate the ion of injection, make the source electrode being subsequently formed and
Drain electrode obtains good Ohmic contact, and contact resistance is effectively reduced.
During above-mentioned rapid thermal annealing, since temperature is very high, if mask layer is photoresist, remaining mask layer
It needs to remove by the way of wet process or Plasma burning before the anneal.
After periodic rapid thermal annealing, acid solution can be used and remove the protective layer, and on barrier layer
It is respectively formed source electrode, drain and gate.The source electrode and drain electrode is located at the two sides of the grid.The grid can be
The compositions such as nickel, gold, platinum it is metal laminated, the source electrode and drain electrode can be a variety of compositions any in the metals such as titanium, aluminium, nickel, gold
Alloy.
Each technical characteristic of embodiment described above can be combined arbitrarily, for simplicity of description, not to above-mentioned reality
It applies all possible combination of each technical characteristic in example to be all described, as long as however, the combination of these technical characteristics is not deposited
In contradiction, all should be considered as described in this specification.
The embodiments described above only express several embodiments of the present invention, and the description thereof is more specific and detailed, but simultaneously
It cannot therefore be construed as limiting the scope of the patent.It should be pointed out that coming for those of ordinary skill in the art
It says, without departing from the inventive concept of the premise, various modifications and improvements can be made, these belong to protection of the invention
Range.Therefore, the scope of protection of the patent of the invention shall be subject to the appended claims.
Claims (10)
1. a kind of semiconductor structure manufacturing method characterized by comprising
Substrate is provided, sequentially forms buffer layer and barrier layer over the substrate；
Protective layer is formed on the barrier layer；
Ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer；
Carry out periodic rapid thermo anneal.
2. semiconductor structure manufacturing method according to claim 1, which is characterized in that the protective layer thickness is 10nm-
100nm。
3. semiconductor structure manufacturing method according to claim 1, which is characterized in that being needed to form on the barrier layer
The region of Ohmic contact carries out ion implanting and specifically includes:
Mask layer is formed on the protective layer, and defines ohmic contact regions；
Remove the mask layer of the ohmic contact regions；
Ion implanting is carried out to ohmic contact regions, makes the region for needing to form Ohmic contact in ion implanting to the barrier layer
It is interior.
4. semiconductor structure manufacturing method according to claim 3, which is characterized in that the mask layer can for metal layer or
Photoresist layer, the protective layer are dielectric layer.
5. semiconductor structure manufacturing method according to claim 1, which is characterized in that a rapid thermal annealing period includes
It is rapidly heated phase, temperature retention period and fast cooling phase.
6. semiconductor structure manufacturing method according to claim 5, which is characterized in that the time of the temperature retention period is
The temperature of 1s-30s, temperature retention period are greater than 1300 DEG C.
7. semiconductor structure manufacturing method according to claim 1, which is characterized in that the ion is silicon, oxygen, Germanium
One or more of.
8. a kind of semiconductor structure manufacturing method characterized by comprising
Substrate is provided, sequentially forms buffer layer and barrier layer over the substrate；
Ion implanting is carried out to the region for needing to form Ohmic contact on the barrier layer；Protection is formed on the barrier layer
Layer；
Carry out periodic rapid thermo anneal.
9. semiconductor structure manufacturing method according to claim 8, which is characterized in that being needed to form on the barrier layer
The region of Ohmic contact carries out ion implanting and specifically includes:
Mask layer is formed on the barrier layer, and defines ohmic contact regions；
Remove the mask layer of the ohmic contact regions；
Ion implanting is carried out to ohmic contact regions, makes the region for needing to form Ohmic contact in ion implanting to the barrier layer
It is interior.
Remove remaining mask layer.
10. semiconductor structure manufacturing method according to claim 8, which is characterized in that the protective layer be metal layer or
Person's dielectric layer or stacking for metal layer or dielectric layer.The mask layer is photoresist, metal or dielectric layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811038479.2A CN109216442A (en) | 2018-09-11 | 2018-09-11 | Semiconductor structure manufacturing method |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811038479.2A CN109216442A (en) | 2018-09-11 | 2018-09-11 | Semiconductor structure manufacturing method |
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| Publication Number | Publication Date |
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| CN109216442A true CN109216442A (en) | 2019-01-15 |
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