CN109192783A - Thin film transistor and its manufacturing method - Google Patents
Thin film transistor and its manufacturing method Download PDFInfo
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- CN109192783A CN109192783A CN201810821086.2A CN201810821086A CN109192783A CN 109192783 A CN109192783 A CN 109192783A CN 201810821086 A CN201810821086 A CN 201810821086A CN 109192783 A CN109192783 A CN 109192783A
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- 239000010409 thin film Substances 0.000 title claims abstract description 58
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 39
- 239000004020 conductor Substances 0.000 claims abstract description 45
- 239000000758 substrate Substances 0.000 claims abstract description 25
- 229920002120 photoresistant polymer Polymers 0.000 claims description 42
- 229910052751 metal Inorganic materials 0.000 claims description 41
- 239000002184 metal Substances 0.000 claims description 41
- 239000000463 material Substances 0.000 claims description 23
- 239000010949 copper Substances 0.000 claims description 21
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 20
- 229910052802 copper Inorganic materials 0.000 claims description 20
- 238000000034 method Methods 0.000 claims description 20
- 239000004065 semiconductor Substances 0.000 claims description 19
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 claims description 16
- 229910052750 molybdenum Inorganic materials 0.000 claims description 16
- 239000011733 molybdenum Substances 0.000 claims description 16
- 239000010408 film Substances 0.000 claims description 14
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 13
- 229910052733 gallium Inorganic materials 0.000 claims description 13
- 229910052738 indium Inorganic materials 0.000 claims description 13
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 13
- 239000010936 titanium Substances 0.000 claims description 13
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 claims description 12
- XLOMVQKBTHCTTD-UHFFFAOYSA-N Zinc monoxide Chemical compound [Zn]=O XLOMVQKBTHCTTD-UHFFFAOYSA-N 0.000 claims description 12
- 239000004411 aluminium Substances 0.000 claims description 12
- 229910052782 aluminium Inorganic materials 0.000 claims description 12
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 12
- 229910052719 titanium Inorganic materials 0.000 claims description 12
- 238000009832 plasma treatment Methods 0.000 claims description 9
- 238000001039 wet etching Methods 0.000 claims description 9
- 238000005240 physical vapour deposition Methods 0.000 claims description 7
- XOLBLPGZBRYERU-UHFFFAOYSA-N tin dioxide Chemical compound O=[Sn]=O XOLBLPGZBRYERU-UHFFFAOYSA-N 0.000 claims description 6
- 229910001887 tin oxide Inorganic materials 0.000 claims description 6
- 239000011787 zinc oxide Substances 0.000 claims description 6
- 230000015572 biosynthetic process Effects 0.000 claims description 5
- 238000010276 construction Methods 0.000 claims description 4
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 2
- 229910052737 gold Inorganic materials 0.000 claims description 2
- 239000010931 gold Substances 0.000 claims description 2
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims 1
- 230000003647 oxidation Effects 0.000 claims 1
- 238000007254 oxidation reaction Methods 0.000 claims 1
- 229910052725 zinc Inorganic materials 0.000 claims 1
- 239000011701 zinc Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 238000012545 processing Methods 0.000 description 6
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 238000000151 deposition Methods 0.000 description 3
- 230000008021 deposition Effects 0.000 description 3
- 238000011161 development Methods 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 238000000137 annealing Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 239000012774 insulation material Substances 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 239000000377 silicon dioxide Substances 0.000 description 2
- 230000009286 beneficial effect Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005401 electroluminescence Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 230000003287 optical effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
The present invention provides a kind of thin film transistor and its manufacturing method.The thin film transistor (TFT) includes: underlay substrate, on underlay substrate and spaced first grid and second grid, the covering underlay substrate, the gate insulating layer of first grid and second grid, the active layer on gate insulating layer and is set on active layer and spaced first source/drain, the second source/drain and third source/drain；Active layer includes being located at the first channel region above first grid, the second channel region above second grid and positioned at the conductor region of the first channel region and the second channel region two sides.Using the present invention, channel configuration can be formed by not needing setting etch stop layer, reduced the production cost of thin film transistor (TFT), simplified manufacture craft；And it reduces the contact resistance between the first source/drain, the second source/drain and third source/drain and active layer and improves the binding force between the first source/drain, the second source/drain and third source/drain and active layer.
Description
Technical field
The present invention relates to field of display technology more particularly to a kind of thin film transistor and its manufacturing methods.
Background technique
Thin film transistor (TFT) (Thin Film Transistor, TFT) is current liquid crystal display device (Liquid Crystal
Display, LCD) and active matrix drive type organic electroluminescence display device and method of manufacturing same (Active Matrix Organic Light-
Emitting Diode, AMOLED) in main driving element, the display performance of direct relation panel display apparatus.
Liquid crystal display on existing market is largely backlight liquid crystal display comprising liquid crystal display panel and back
Optical mode group (backlight module).The working principle of liquid crystal display panel is in thin-film transistor array base-plate (Thin
Film Transistor Array Substrate, TFT Array Substrate) and colored filter (Color
Filter, CF) liquid crystal molecule is poured between substrate, and apply pixel voltage and common voltage respectively on two plate bases, pass through
The direction of rotation of the electric field controls liquid crystal molecule formed between pixel voltage and common voltage transmits the light of backlight module
Picture is generated out.
The oxide semiconductor materials such as indium gallium zinc oxide (IGZO) are wide due to high mobility and on-state current
It is general to be applied in display industry TFT device.However currently used back channel (BCE) bottom-gate oxide semiconductor TFT processing procedure
It is complex, need to increase etch stop layer (Etching-Stop-Layer, ESL), for avoiding in source-drain electrode layer wet etching
When on the oxide semiconductor at channel cause damage and influence device performance.Meanwhile in order to improve the on-state current of TFT device
With save space, prior art also teaches double channel oxide semiconductor TFT, but, technique similar with etch stop layer structure
Process is complex, and thermal annealing (thermal annealing) process is additionally needed to carry out hydrogen diffusion to active layer
(hydrogen diffusion) operation.Therefore exploitation does not need the bottom-gate double channel oxide semiconductor of etch stop layer
TFT is of great significance.
Summary of the invention
The purpose of the present invention is to provide a kind of thin film transistor (TFT)s, and double channel can be formed by not needing setting etch stop layer
Structure reduces the production cost of thin film transistor (TFT), simplifies manufacture craft.
The object of the invention is also to provide a kind of production methods of thin film transistor (TFT), do not need setting etch stop layer i.e.
Channel configuration can be formed, the production cost of thin film transistor (TFT) is reduced, simplifies manufacture craft.
To achieve the above object, the present invention provides a kind of thin film transistor (TFT)s, comprising: underlay substrate is set to the substrate
On substrate and spaced first grid and second grid, the covering underlay substrate, first grid and second grid grid
Pole insulating layer, the active layer on the gate insulating layer and be set to the active layer on and spaced first source/
Drain electrode, the second source/drain and third source/drain；
The active layer includes the first channel region above the first grid, above the second grid
Second channel region and positioned at the conductor region of first channel region and the second channel region two sides.
Optionally, first source/drain connects between the first channel region and the second channel region and with the conductor region
Touching；Second source/drain is contacted far from the first source/drain side and with the conductor region；The third source/drain is far from
The one source/drain other side is simultaneously contacted with the conductor region.
Optionally, it is brilliant to constitute the first film for the first grid, the first channel region, the first source/drain and the second source/drain
Body pipe；The second grid, the second channel region, the first source/drain and third source/drain constitute the second thin film transistor (TFT).
Optionally, the thickness of the conductor region is greater than
Optionally, the material of the first grid and second grid is one of molybdenum, aluminium, copper and titanium or a variety of；Institute
The material for stating the first source/drain, the second source/drain and third source/drain is one of molybdenum, aluminium, copper and titanium or a variety of.
Optionally, the first grid and second grid are the stepped construction of metal molybdenum layer and metal copper layer；Described
The material of one source/drain, the second source/drain and third source/drain is copper.
Optionally, the material of the active layer is one of indium gallium zinc oxide and indium gallium tin-oxide.
The present invention also provides a kind of production methods of thin film transistor (TFT), include the following steps:
Step S1, provides underlay substrate, one layer of the first metal layer is formed on the underlay substrate, to the first metal layer
It carries out patterned process and forms spaced first grid and second grid；
Step S2, the gate insulating layer for covering the underlay substrate, first grid and second grid is formed, in the grid
Oxide semiconductor layer is formed on insulating layer；
Step S3, one layer of photoresist is formed on the oxide semiconductor layer, and patterned process is carried out to the photoresist and is formed
The first photoresist layer above the first grid and second grid；
Step S4, it is to block with first photoresist layer, plasma treatment is carried out to the oxide semiconductor layer and is formed
Active layer；The active layer includes the first channel region above the first grid, above the second grid
Second channel region and positioned at the conductor region of first channel region and the second channel region two sides；
Step S5, second metal layer is formed on first photoresist layer and conductor region by physical vapour deposition (PVD)；It is located at
Second metal layer on first photoresist layer and the second metal layer on the conductor region discontinuously form a film；
Step S6, it removes first photoresist layer and exposes first channel region and the second channel region, while removing position
Second metal layer on first photoresist layer；
Step S7, one layer of photoresist is formed in first channel region, the second channel region and second metal layer, to the photoresist
It carries out patterned process and forms the second photoresist layer for exposing part second metal layer；
Step S8, it is to block with second photoresist layer, wet etching is carried out to the second metal layer, is formed and is located at first
The first source/drain for being contacted between channel region and the second channel region and with the conductor region, far from the first source/drain side and with
Second source/drain of the conductor region contact and the separate first source/drain other side and the third contacted with the conductor region
Source/drain；Remove second photoresist layer.
Optionally, it is brilliant to constitute the first film for the first grid, the first channel region, the first source/drain and the second source/drain
Body pipe；The second grid, the second channel region, the first source/drain and third source/drain constitute the second thin film transistor (TFT)；
Optionally, the thickness of the conductor region is greater than
Optionally, the material of the first grid and second grid is one of molybdenum, aluminium, copper and titanium or a variety of；Institute
The material for stating the first source/drain, the second source/drain and third source/drain is one of molybdenum, aluminium, copper and titanium or a variety of；
Optionally, the material of the active layer is one of indium gallium zinc oxide and indium gallium tin-oxide.
Beneficial effects of the present invention: thin film transistor (TFT) of the invention, which does not need setting etch stop layer, can form double channel
Structure reduces the production cost of thin film transistor (TFT), simplifies manufacture craft；And due to the first source/drain, the second source/drain and
Third source/drain is contacted with conductor region, to reduce the first source/drain, the second source/drain and third source/drain and active layer
Between contact resistance and improve the binding force between the first source/drain, the second source/drain and third source/drain and active layer.
The production method of thin film transistor (TFT) of the invention forms channel configuration by plasma treatment, then carries out to second metal layer
Double patterning processing, the removal of first time patterned process are located at the second metal above the first channel region and the second channel region
Layer, second of the first source/drain of patterned process formation, the second source/drain and third source/drain, the second photoresist layer can be right
First channel region and the second channel region are protected, prevent when wet etching to the first channel region and the second channel region cause damage and
Device performance is influenced, therefore does not need setting etch stop layer to protect channel region, reduces the production cost of thin film transistor (TFT), letter
Change manufacture craft；And partial oxide semiconductor layer is carried out by conductor using plasma treatment, to reduce the first source/drain
Contact resistance and raising the first source/drain, the second source/drain between pole, the second source/drain and third source/drain and active layer
Binding force between pole and third source/drain and active layer.
Detailed description of the invention
For further understanding of the features and technical contents of the present invention, it please refers to below in connection with of the invention detailed
Illustrate and attached drawing, however, the drawings only provide reference and explanation, is not intended to limit the present invention.
In attached drawing,
Fig. 1 is the structural schematic diagram of thin film transistor (TFT) of the invention；
Fig. 2 is the flow chart of the production method of thin film transistor (TFT) of the invention；
Fig. 3 and Fig. 4 is the schematic diagram of the production method step S1 of thin film transistor (TFT) of the invention；
Fig. 5 is the schematic diagram of the production method step S2 of thin film transistor (TFT) of the invention；
Fig. 6 is the schematic diagram of the production method step S3 of thin film transistor (TFT) of the invention；
Fig. 7 is the schematic diagram of the production method step S4 of thin film transistor (TFT) of the invention；
Fig. 8 is the schematic diagram of the production method step S5 of thin film transistor (TFT) of the invention；
Fig. 9 is the schematic diagram of the production method step S6 of thin film transistor (TFT) of the invention；
Figure 10 is the schematic diagram of the production method step S7 of thin film transistor (TFT) of the invention；
Figure 11 and Figure 12 is the schematic diagram of the production method step S8 of thin film transistor (TFT) of the invention.
Specific embodiment
Further to illustrate technological means and its effect adopted by the present invention, below in conjunction with preferred implementation of the invention
Example and its attached drawing are described in detail.
Referring to Fig. 1, the present invention provides a kind of thin film transistor (TFT), comprising: underlay substrate 10 is set to the underlay substrate 10
Upper and spaced first grid 21 and second grid 22, the covering underlay substrate 10, first grid 21 and second grid
It 22 gate insulating layer 30, the active layer 43 on the gate insulating layer 30 and on the active layer 43 and is spaced
The first source/drain 51, the second source/drain 52 and the third source/drain 53 being arranged.
Specifically, the active layer 43 includes positioned at the first channel region 431 of 21 top of first grid, positioned at described
Second channel region 432 of the top of second grid 22 and leading positioned at first channel region 431 and 432 two sides of the second channel region
Body area 433.
Specifically, first source/drain 51 between the first channel region 431 and the second channel region 432 and with it is described
Conductor region 433 contacts；Second source/drain 52 is contacted far from 51 side of the first source/drain and with the conductor region 433；Institute
Third source/drain 53 is stated to contact far from 51 other side of the first source/drain and with the conductor region 433.
Specifically, the gate insulating layer 30 is transparent insulation material (such as silica).
Specifically, the material of the first grid 21 and second grid 22 is molybdenum (Mo), aluminium (Al), copper (Cu) and titanium
One of (Ti) or it is a variety of；Preferably, the first grid 21 and second grid 22 are metal molybdenum layer and metal copper layer
Stepped construction.
Specifically, the material of the active layer 43 is in indium gallium zinc oxide (IGZO) and indium gallium tin-oxide (IGTO)
It is a kind of.
Specifically, the material of first source/drain 51, the second source/drain 52 and third source/drain 53 be molybdenum, aluminium,
One of copper and titanium are a variety of.Preferably, first source/drain 51, the second source/drain 52 and third source/drain 53
Material is copper.
Specifically, the first grid 21, the first channel region 431, the first source/drain 51 and the second source/drain 52 are constituted
First film transistor T1；The second grid 22,53 structure of the second channel region 432, the first source/drain 51 and third source/drain
At the second thin film transistor (TFT) T2；That is first film transistor T1 and the second thin film transistor (TFT) T2 shares the first source/drain 51, this
One source/drain 51 can both be equivalent to the source/drain of first film transistor T1, can also be equivalent to the second thin film transistor (TFT) T2
Source/drain.
It should be noted that thin film transistor (TFT) of the invention, which does not need setting etch stop layer, can form double channel knot
Structure reduces the production cost of thin film transistor (TFT), simplifies manufacture craft；And due to the first source/drain 51, the second source/drain 52
It is contacted with conductor region 433 with third source/drain 53, to reduce the first source/drain 51, the second source/drain 52 and third source/drain
Contact resistance and the first source/drain 51 of raising, the second source/drain 52 and third source/drain 53 between pole 53 and active layer 43
With the binding force between active layer 43.
Preferably, the thickness of the conductor region 433 is greater thanWith further decrease the first source/drain 51, the second source/
Drain electrode 52 and the contact resistance between third source/drain 53 and active layer 43.
Referring to Fig. 2, the present invention provides a kind of production method of thin film transistor (TFT), include the following steps:
Step S1 please refers to Fig. 3 and Fig. 4, provides underlay substrate 10, and one layer of first gold medal is formed on the underlay substrate 10
Belong to layer 20, patterned process (exposure, development, wet etching and removing photoresistance) is carried out to the first metal layer 20 and forms interval setting
First grid 21 and second grid 22.
Specifically, the material of the first grid 21 and second grid 22 is one of molybdenum, aluminium, copper and titanium or more
Kind；Preferably, the first grid 21 and second grid 22 are the stepped construction of metal molybdenum layer and metal copper layer.
Step S2, referring to Fig. 5, forming the grid for covering the underlay substrate 10, first grid 21 and second grid 22
Insulating layer 30 forms oxide semiconductor layer 40 on the gate insulating layer 30.
Specifically, the gate insulating layer 30 is transparent insulation material (such as silica).
Step S3, referring to Fig. 6, forming one layer of photoresist on the oxide semiconductor layer 40, figure is carried out to the photoresist
Caseization processing (exposure, development) forms the first photoresist layer 100 for being located at 22 top of the first grid 21 and second grid.
Step S4, referring to Fig. 7, being to block with first photoresist layer 100, the oxide semiconductor layer 40 is carried out
The resistance of plasma treatment, the partial oxide semiconductor layer 40 not sheltered from by the first photoresist layer 100 reduces, thus by leading
Bodyization processing makes the property of partial oxide semiconductor layer 40 close to conductor, forms active layer 43；The active layer 43 includes position
The first channel region 431 above the first grid 21, the second channel region 432 above the second grid 22 and
Positioned at the conductor region 433 of 432 two sides of first channel region 431 and the second channel region.
Specifically, the material of the active layer 43 is one of indium gallium zinc oxide and indium gallium tin-oxide.
Step S5, referring to Fig. 8, by physical vapour deposition (PVD) (PVD) in first photoresist layer 100 and conductor region 433
Upper formation second metal layer 50 can be by controlling physics gas since the first photoresist layer 100 and conductor region 433 have difference in height
The mutually deposition rate or other deposition parameters of deposition makes the second metal layer 50 being located on first photoresist layer 100 and is located at
Second metal layer 50 on the conductor region 433 discontinuously forms a film.
Step S6, referring to Fig. 9, removing first photoresist layer 100 exposes first channel region 431 and the second ditch
Road area 432, while removing the second metal layer 50 being located on first photoresist layer 100.
Step S7, referring to Fig. 10, in first channel region 431, the second channel region 432 and second metal layer 50 shape
At one layer of photoresist, patterned process (exposure, development) formation is carried out to the photoresist and exposes the second of part second metal layer 50
Photoresist layer 200.
Step S8, Figure 11 and Figure 12 is please referred to, is to block with second photoresist layer 200, to the second metal layer 50
Wet etching is carried out, the contacted between the first channel region 431 and the second channel region 432 and with the conductor region 433 is formed
One source/drain 51, far from 51 side of the first source/drain and the second source/drain 52 for being contacted with the conductor region 433 and separate
First source/drain, 51 other side and the third source/drain 53 contacted with the conductor region 433；Remove second photoresist layer
200。
Specifically, the material of first source/drain 51, the second source/drain 52 and third source/drain 53 be molybdenum, aluminium,
One of copper and titanium are a variety of.Preferably, first source/drain 51, the second source/drain 52 and third source/drain 53
Material is copper.
Specifically, the first grid 21, the first channel region 431, the first source/drain 51 and the second source/drain 52 are constituted
First film transistor T1；The second grid 22,53 structure of the second channel region 432, the first source/drain 51 and third source/drain
At the second thin film transistor (TFT) T2；That is first film transistor T1 and the second thin film transistor (TFT) T2 shares the first source/drain 51, this
One source/drain 51 can both be equivalent to the source/drain of first film transistor T1, can also be equivalent to the second thin film transistor (TFT) T2
Source/drain.
It should be noted that thin film transistor (TFT) of the invention forms channel configuration by plasma treatment, then to the
Two metal layers 50 carry out double patterning processing, and the removal of first time patterned process is located at the first channel region 431 and the second channel
The second metal layer 50 of 432 top of area, second of patterned process form the first source/drain 51, the second source/drain 52 and third
Source/drain 53, due to wet etching can simultaneously by second metal layer 50 and positioned at the lower section of second metal layer 50 conductor region 433 simultaneously
It etches away, therefore when forming the first source/drain 51, the second source/drain 52 and third source/drain 53, the second photoresist layer 200 can
To be protected to the first channel region 431 and the second channel region 432, to the first channel region 431 and the second ditch when preventing wet etching
Road area 432 causes to damage and influence device performance, therefore does not need setting etch stop layer to protect channel region, and it is brilliant to reduce film
The production cost of body pipe simplifies manufacture craft；And partial oxide semiconductor layer 40 is carried out by conductor using plasma treatment
Change, simultaneously with the contact resistance between the first source/drain 51 of reduction, the second source/drain 52 and third source/drain 53 and active layer 43
Improve the binding force between the first source/drain 51, the second source/drain 52 and third source/drain 53 and active layer 43.
Preferably, the thickness of the conductor region 433 is greater thanWith further decrease the first source/drain 51, the second source/
Drain electrode 52 and the contact resistance between third source/drain 53 and active layer 43.
In conclusion thin film transistor (TFT) of the invention, which does not need setting etch stop layer, can form channel configuration, drop
The production cost of low thin film transistor (TFT) simplifies manufacture craft；And due to the first source/drain, the second source/drain and third source/
Drain electrode is contacted with conductor region, with connecing between the first source/drain of reduction, the second source/drain and third source/drain and active layer
Electric shock hinders and improves the binding force between the first source/drain, the second source/drain and third source/drain and active layer.Of the invention
The production method of thin film transistor (TFT) forms channel configuration by plasma treatment, then carries out pattern twice to second metal layer
Change processing, the removal of first time patterned process are located at the second metal layer above the first channel region and the second channel region, for the second time
The first source/drain of patterned process formation, the second source/drain and third source/drain, the second photoresist layer can be to the first channel regions
And second channel region protected, prevent when wet etching on the first channel region and the second channel region cause damage and influence device
Can, therefore setting etch stop layer is not needed to protect channel region, the production cost of thin film transistor (TFT) is reduced, production work is simplified
Skill；And using plasma treatment by partial oxide semiconductor layer carry out conductor, with reduce the first source/drain, the second source/
Drain electrode and the contact resistance between third source/drain and active layer and improve the first source/drain, the second source/drain and third source/
Binding force between drain electrode and active layer.
The above for those of ordinary skill in the art can according to the technique and scheme of the present invention and technology
Other various corresponding changes and modifications are made in design, and all these change and modification all should belong to the claims in the present invention
Protection scope.
Claims (9)
1. a kind of thin film transistor (TFT) characterized by comprising underlay substrate (10), be set to the underlay substrate (10) on and between
Every the first grid (21) and second grid (22) of setting, the covering underlay substrate (10), first grid (21) and second gate
The gate insulating layer (30) of pole (22), be set to the gate insulating layer (30) on active layer (43) and be set to the active layer
(43) on and spaced first source/drain (51), the second source/drain (52) and third source/drain (53)；The active layer
It (43) include being located at the first channel region (431) above the first grid (21), being located above the second grid (22)
Second channel region (432) and the conductor region (433) for being located at first channel region (431) and the second channel region (432) two sides.
2. thin film transistor (TFT) as described in claim 1, which is characterized in that first source/drain (51) is located at the first channel
It is contacted between area (431) and the second channel region (432) and with the conductor region (433)；Second source/drain (52) is far from the
One source/drain (51) side is simultaneously contacted with the conductor region (433)；The third source/drain (53) is far from the first source/drain
(51) it the other side and is contacted with the conductor region (433).
3. thin film transistor (TFT) as claimed in claim 2, which is characterized in that the first grid (21), the first channel region
(431), the first source/drain (51) and the second source/drain (52) constitute first film transistor (T1)；The second grid
(22), the second channel region (432), the first source/drain (51) and third source/drain (53) constitute the second thin film transistor (TFT) (T2).
4. thin film transistor (TFT) as described in claim 1, which is characterized in that the thickness of the conductor region (433) is greater than
5. thin film transistor (TFT) as described in claim 1, which is characterized in that the first grid (21) and second grid (22)
Material is one of molybdenum, aluminium, copper and titanium or a variety of；First source/drain (51), the second source/drain (52) and third
The material of source/drain (53) is one of molybdenum, aluminium, copper and titanium or a variety of.
6. thin film transistor (TFT) as claimed in claim 5, which is characterized in that the first grid (21) and second grid (22) are equal
For the stepped construction of metal molybdenum layer and metal copper layer；First source/drain (51), the second source/drain (52) and third source/drain
The material of pole (53) is copper.
7. thin film transistor (TFT) as described in claim 1, which is characterized in that the material of the active layer (43) is the oxidation of indium gallium zinc
One of object and indium gallium tin-oxide.
8. a kind of production method of thin film transistor (TFT), which comprises the steps of:
Step S1 provides underlay substrate (10), and one layer of the first metal layer (20) is formed on the underlay substrate (10), to this
One metal layer (20) carries out patterned process and forms spaced first grid (21) and second grid (22)；
Step S2, the gate insulating layer for covering the underlay substrate (10), first grid (21) and second grid (22) is formed
(30), it is formed on the gate insulating layer (30) oxide semiconductor layer (40)；
Step S3, one layer of photoresist is formed on the oxide semiconductor layer (40), and patterned process is carried out to the photoresist and is formed
The first photoresist layer (100) above the first grid (21) and second grid (22)；
Step S4, it is to block with first photoresist layer (100), plasma treatment is carried out to the oxide semiconductor layer (40)
It is formed active layer (43)；The active layer (43) includes the first channel region (431) above the first grid (21), position
The second channel region (432) above the second grid (22) and it is located at first channel region (431) and the second channel
The conductor region (433) of area (432) two sides；
Step S5, second metal layer is formed on first photoresist layer (100) and conductor region (433) by physical vapour deposition (PVD)
(50)；Second metal layer (50) on first photoresist layer (100) and the second gold medal on the conductor region (433)
Belong to layer (50) discontinuously to form a film；
Step S6, it removes first photoresist layer (100) and exposes first channel region (431) and the second channel region (432),
Removing is located at the second metal layer (50) on first photoresist layer (100) simultaneously；
Step S7, one layer of light is formed in first channel region (431), the second channel region (432) and second metal layer (50)
Resistance carries out the second photoresist layer (200) that patterned process formation exposes part second metal layer (50) to the photoresist；
Step S8, it is to block with second photoresist layer (200), wet etching is carried out to the second metal layer (50), forms position
The first source/drain contacted between the first channel region (431) and the second channel region (432) and with the conductor region (433)
(51), far from the first source/drain (51) side and the second source/drain (52) for being contacted with the conductor region (433) and separate
First source/drain (51) other side and the third source/drain (53) contacted with the conductor region (433)；Remove second light
Resistance layer (200).
9. the production method of thin film transistor (TFT) as claimed in claim 8, which is characterized in that the first grid (21), first
Channel region (431), the first source/drain (51) and the second source/drain (52) constitute first film transistor (T1)；The second gate
Pole (22), the second channel region (432), the first source/drain (51) and third source/drain (53) constitute the second thin film transistor (TFT)
(T2)；
The thickness of the conductor region (433) is greater than
The material of the first grid (21) and second grid (22) is one of molybdenum, aluminium, copper and titanium or a variety of；Described
The material of one source/drain (51), the second source/drain (52) and third source/drain (53) is one of molybdenum, aluminium, copper and titanium
Or it is a variety of；
The material of the active layer (43) is one of indium gallium zinc oxide and indium gallium tin-oxide.
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| CN201810821086.2A CN109192783A (en) | 2018-07-24 | 2018-07-24 | Thin film transistor and its manufacturing method |
| PCT/CN2018/117522 WO2020019606A1 (en) | 2018-07-24 | 2018-11-26 | Tft array substrate and manufacturing method thereof |
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Cited By (2)
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| CN109148372A (en) * | 2018-08-20 | 2019-01-04 | 深圳市华星光电技术有限公司 | Thin film transistor (TFT) production method, thin film transistor (TFT) and display panel |
| CN115548127A (en) * | 2022-09-30 | 2022-12-30 | 惠科股份有限公司 | Transistor, array substrate and display panel |
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| CN1316633C (en) * | 2004-07-08 | 2007-05-16 | 吉林大学 | Polycrystalline SiTFT of multi-grid double-channel structure |
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| WO2020019606A1 (en) | 2020-01-30 |
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