CN109192698B - Method for realizing GaN device isolation based on InGaN insertion layer - Google Patents

Method for realizing GaN device isolation based on InGaN insertion layer Download PDF

Info

Publication number
CN109192698B
CN109192698B CN201810771532.3A CN201810771532A CN109192698B CN 109192698 B CN109192698 B CN 109192698B CN 201810771532 A CN201810771532 A CN 201810771532A CN 109192698 B CN109192698 B CN 109192698B
Authority
CN
China
Prior art keywords
layer
ingan
gan
barrier layer
isolation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CN201810771532.3A
Other languages
Chinese (zh)
Other versions
CN109192698A (en
Inventor
孙辉
胡腾飞
刘美华
林信南
陈东敏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Peking University Shenzhen Graduate School
Original Assignee
Peking University Shenzhen Graduate School
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Peking University Shenzhen Graduate School filed Critical Peking University Shenzhen Graduate School
Priority to CN201810771532.3A priority Critical patent/CN109192698B/en
Publication of CN109192698A publication Critical patent/CN109192698A/en
Application granted granted Critical
Publication of CN109192698B publication Critical patent/CN109192698B/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/7605—Making of isolation regions between components between components manufactured in an active substrate comprising AIII BV compounds

Abstract

The invention discloses a method for realizing GaN device isolation based on an InGaN insertion layer, which comprises the following steps: preparing a GaN epitaxial wafer, forming two-dimensional electron gas between a GaN channel layer and an AlGaN barrier layer of the GaN epitaxial wafer, arranging an InGaN insertion layer between isolation regions of the GaN epitaxial wafer, wherein the InGaN insertion layer is arranged outside the AlGaN layer, and inducing polarized negative charges in heterojunction of the InGaN insertion layer and the AlGaN barrier layer, and the polarized negative charges exhaust electrons in the two-dimensional electron gas to realize isolation of different device regions. The invention realizes the isolation of the device, and the isolation region has high stability and good planarization. The method avoids damage and instability caused by ion implantation in the isolation process of the traditional GaN device, avoids interface damage and deep grooves caused by etching, ensures the planarization of the device, and is a very good technical choice in the process of mass production of GaN devices based on large-size platforms.

Description

Method for realizing GaN device isolation based on InGaN insertion layer
Technical Field
The invention relates to the technical field of semiconductors, in particular to a method for realizing GaN device isolation based on an InGaN insertion layer.
Background
With the increasing demand for highly efficient and self-contained power conversion circuits and systems, power devices having low power consumption and high-speed characteristics have recently attracted much attention. GaN is a third generation wide bandgap semiconductor material, and has strong advantages under high-voltage, high-frequency, high-temperature, high-power and anti-radiation environmental conditions due to its large bandgap width (3.4eV), high electron saturation rate (2 × 107cm/s), high breakdown electric field (1 × 1010-3 × 1010V/cm), high thermal conductivity, corrosion resistance and radiation resistance, and is considered as an optimal material for researching short-wave photoelectronic devices and high-voltage high-frequency high-power devices. GaN-based AlGaN/GaN high mobility transistors are a research hotspot in power devices because AlGaN/GaN suppresses the formation of a high-concentration, high-mobility two-dimensional electron gas (2DEG) at the junction, while the heterojunction has a good regulating effect on the 2 DEG.
Good device isolation technology is fundamental to the realization of high density discrete device and integrated circuit fabrication on large size wafers. Currently, to speed up the commercial application of AlGaN/GaN heterostructures, a common idea and practice in the industry is to develop Si platform-based compatible 4-8inch GaN devices. There are mainly 2 of these schemes for device isolation: firstly, ion implantation isolation is carried out, namely O, H, He and other ions are implanted into an isolation region to realize isolation among devices in a chip; the isolation technology based on the scheme has the problems of poor high-temperature stability of an isolation region, serious damage to the surface of a material and the like; dry etching isolation, wherein AlGaN on the upper layer of an isolation region and part of GaN are etched off by a Cl2/BCl 3-based plasma etching method, and a channel of 2DEG of the isolation region is cut off, so that isolation between devices is realized, the scheme is a scheme commonly adopted by most commercial device developers at present, and the scheme also has inevitable problems, namely, a deep groove is formed, the surface of the device is not easy to flatten, and particularly, the flat surface of the device is the basis for realizing excellent performance of the device based on the development of small-size devices in the future; secondly, a better deep groove medium filling technology is needed, and particularly for a high-power device, the 2DEG channel exposed out of the isolation region is greatly contacted with electrode metal and a substrate Si material, so that the risks of electric leakage and short circuit are caused; therefore, in view of the increasing market demand, there is a need to develop a device isolation technology that can satisfy both stability and sustainability of technology extension.
Disclosure of Invention
The application provides a method for realizing GaN device isolation based on an InGaN insertion layer, which is used for solving the technical problems of poor high-temperature stability of a device isolation region, serious material surface damage and poor surface planarization of a device caused by the existing ion implantation and dry etching isolation technology.
In order to solve the problems, the technical scheme of the invention is as follows:
a method for realizing GaN device isolation based on an InGaN insertion layer comprises the following steps: preparing a GaN epitaxial wafer, forming two-dimensional electron gas between a GaN channel layer and an AlGaN barrier layer of the GaN epitaxial wafer, arranging an InGaN insertion layer between different device areas of the GaN epitaxial wafer, arranging the InGaN insertion layer outside the AlGaN layer, inducing polarized negative charges in heterojunction of the InGaN insertion layer and the AlGaN barrier layer, and exhausting electrons in the two-dimensional electron gas by the polarized negative charges to realize the isolation of the different device areas.
A GaN device based on InGaN insertion layer isolation comprises a substrate, a GaN buffer layer, a GaN channel layer and an AlGaN barrier layer which are sequentially arranged from bottom to top, wherein a plurality of independent device areas are formed on the AlGaN barrier layer, each device area is provided with an active electrode, a drain electrode and a gate electrode, a passivation layer connected with the AlGaN barrier layer covers between the electrodes, and an InGaN insertion layer is arranged between the AlGaN barrier layer and the passivation layer in different device areas.
The invention has the beneficial effects that:
the method of inserting the InGaN thin layer into the isolation region is adopted, electrons in the channel are exhausted, so that isolation of different device regions is achieved, the stability of the isolation region is high, and the planarization is good. The method avoids damage and instability caused by ion implantation in the isolation process of the traditional GaN device, avoids interface damage and deep grooves caused by etching, ensures the planarization of the device, and is a very good technical choice in the process of mass production of GaN devices based on large-size platforms.
Drawings
Fig. 1 is a cross-sectional view of an isolation region formed of an InGaN insertion layer of the present invention.
Fig. 2 is an energy band diagram of the isolation region of fig. 1.
Fig. 3 is a schematic view of a GaN epitaxial wafer structure.
FIG. 4 is a structural view of a GaN crystal.
FIG. 5 is a schematic view showing the polarization effect of AlGaN/GaN heterojunction on GaN epitaxial wafer.
FIG. 6 is a schematic diagram showing the polarization effect of InGaN/AlGaN heterojunction.
FIG. 7 is a schematic diagram showing the principle of two-dimensional electron gas exhaustion in the method of the present invention.
FIG. 8 is a schematic diagram of a GaN device structure and its device and isolation region band diagrams prepared according to an embodiment of the invention.
In the figure, 101-substrate, 102-GaN buffer layer, 103-GaN channel layer, 104-two-dimensional electron gas, 105-AlGaN barrier layer, 106-InGaN insertion layer, 107-passivation layer.
Detailed Description
At present, there are two main schemes commonly used for GaN device isolation, namely ion implantation isolation and dry etching isolation, and the two methods can cause the problems of poor high-temperature stability of a device isolation region, serious damage to the surface of a material, poor surface planarization of a device, and easy leakage and short circuit of the device. Therefore, there is a need to develop a device isolation technology that can satisfy both stability and sustainability of technology extension.
In order to solve the above problems, the present invention provides a method for realizing GaN device isolation based on an InGaN insertion layer, and the basic idea of the method is to insert an InGaN thin layer into different device regions of a GaN epitaxial wafer to deplete electrons in a channel, thereby realizing device isolation. The method avoids damage and instability caused by ion implantation, avoids a deep groove formed by dry etching isolation, ensures the planarization of the device, and is a good choice in the mass production process development of the GaN device. Fig. 1 and 2 show a cross-sectional view and an energy band diagram of a device isolation region, respectively, and it can be seen that the device isolation region has a simple physical structure and a very excellent isolation effect.
The InGaN insertion layer is used for depleting electrons in a channel to realize the isolation between devices, and the principle is as follows:
before explaining the principle, the polarization effect and the estimated polarization-induced electron concentration are known by explaining the cause of high-concentration two-dimensional electron gas (2-DEG) in the AlGaN/GaN heterojunction in the GaN epitaxial wafer.
Fig. 3 shows a schematic view of an epitaxial structure commonly used in devices made of GaN, which generally includes a 2-3um GaN channel layer and 20-30nm AlGaN barrier layer, wherein the Al composition is 25% of the most common.
GaN and AlN materials used for power and radio frequency device development are all materials based on a wurtzite structure grown in a (111) lattice direction, and referring to fig. 4, the materials have strong ferroelectricity and strong spontaneous polarization effect; meanwhile, piezoelectric polarization effect caused by lattice mismatch exists between AlGaN and GaN; a large amount of polarization charges are induced at the AlGaN/GaN contact interface, and the induced charges are positive charges as can be seen from the analysis of the polarization direction, as shown in fig. 5. Thus, the high concentration of forward polarized charges eventually induces a high density of electrons at the GaN side of the AlGaN/GaN interface, and this thin layer of electrons is called a two-dimensional electron gas (2-DEG) as shown by the dashed line in fig. 3.
The concentration of electrons induced by the polarization effect can be calculated using the following formula:
Figure GDA0002624579000000031
wherein x represents an Al component, in this case 0.25. d is the thickness of the AlGaN layer, σ is the polarization amount, e φbIs a Schottky barrier, EFIs the Fermi level,. DELTA.ECThe conduction band difference of the AlGaN/GaN interface is the relative dielectric constant;
to calculate the electron concentration nsSome of the following estimates need to be made:
(x)＝-0.5x+(GaN) (1)
eφb＝1.3x+eφb(GaN)eV (2)
Figure GDA0002624579000000032
wherein the content of the first and second substances,
Figure GDA0002624579000000041
ΔEC＝0.7[Eg(x)-Eg(0)] (5)
wherein the content of the first and second substances,
Eg(x)＝xEg(AlN)+(1-x)Eg(GaN)-x(1-x)1.0eV (6)
Figure GDA0002624579000000042
wherein a is a lattice constant, e is a piezoelectric polarization coefficient, C is an elastic constant, and PSP is a spontaneous polarization quantity; their estimation can use the following linear equation:
Figure GDA0002624579000000043
the table below gives the basic constants for GaN, AlN, InN:
TABLE 1 parameter tables for GaN, AlN, InN
Figure GDA0002624579000000044
By substituting these constants into the equations (1) - (8), the electron concentration n can be obtainedsIs 10 in size13Magnitude; and ns increases with increasing AlGaN thickness and Al composition.
The above principle is now applied to the analysis of InGaN/AlGaN, and the depletion effect of the InGaN insertion layer on the two-dimensional electron gas (2-DEG) in the method of the present invention can be well illustrated. The following table shows Al calculated by the formulas (1), (6), (8)0.25Ga0.75Values of the parameters of N:
TABLE 2 GaN, Al0.25Ga0.75N parameter table
Figure GDA0002624579000000051
According to the linear modulation theory of (1), (6) and (8), In can be deducedxGa1-xN estimation formula of each parameter:
Figure GDA0002624579000000052
InxGa1-xn forbidden band width EgCan be obtained using the following method:
Eg(x)＝xEg(GaN)+(1-x)Eg(InN)-x(1-x)1.4eV (10)
the parameters obtained by substituting the parameters in table 1 into equations (9) and (10) are shown in the following table:
TABLE 3 GaN, In0.2Ga0.8N parameter table
Figure GDA0002624579000000053
For better comparison of the relationship between AlGaN/GaN and InGaN/AlGaN, tables 2 and 3 are integrated into one table, as shown in Table 4 below. It can be qualitatively seen from the table that the piezoelectric polarization of the InGaN/AlGaN heterojunction is in the opposite direction (the size of lattice a) to that of the AlGaN/GaN heterojunction, and negative polarization charges are induced.
TABLE 4 GaN, Al0.25Ga0.75N、In0.2Ga0.8N parameter table
Figure GDA0002624579000000061
The following semi-quantitative analysis is made of the polarization effect between InGaN/AlGaN. Since the GaN structure of the conventional wurtzite structure is grown by using Ga surface, the spontaneous polarization direction of the epitaxial material is the reverse Ga surface direction, namely the direction toward the substrate, according to the symmetry of the hexagonal lattice. In addition, the direction of piezoelectric polarization is judged by judging the positive and negative values of the following formula (11), if the result is less than 0, the direction of piezoelectric polarization points to the substrate, otherwise, to the surface;
Figure GDA0002624579000000062
wherein a is the lattice constant of AlGaN0Is the lattice constant of InGaN, e31,e33,C13,C33Respectively, the piezoelectric coefficient and the elastic coefficient of AlGaN in different directions. Al in Table 40.25Ga0.75N、In0.2Ga0.8The formula of each parameter in N can be found out PPEGreater than 0. Its piezoelectric polarization direction is directed towards the surface. Because the intensity of piezoelectric polarization is much greater than spontaneous polarization, negative polarization charges are induced at the InGaN/AlGaN interface, and the charges are located in the AlGaN material, as shown in fig. 6.
Thus, the InGaN/AlGaN heterojunction induces polarized negative charges that repel electrons generated by the AlGaN/GaN heterojunction, thereby depleting the two-dimensional electron gas (2-DEG), as shown in FIG. 7. The electron depletion degree can be adjusted by adjusting the composition and thickness of Al and In AlGaN and InGaN, and finally the electron depletion degree can be reached, so that the complete isolation between devices is realized.
In addition, it can be seen from the energy band diagram in fig. 2 that the conduction band of AlGaN/GaN is raised to above the fermi level by inserting the InGaN thin layer, and the fermi capability represents the electron filling level, below the fermi level, all electrons are filled, and above the fermi level, there is no electron filling, so that the depletion effect of the InGaN layer on the electrons of the AlGaN/GaN heterojunction can be well illustrated from this point of view.
In order to make the objects, technical solutions and advantages of the present invention clearer, the present invention will be described in further detail with reference to the accompanying drawings, and it is apparent that the described embodiments are only a part of the embodiments of the present invention, not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
Example (b):
a method for realizing GaN device isolation based on an InGaN insertion layer specifically comprises the following steps:
epitaxially growing a GaN buffer layer 102, a GaN channel layer 103 and an AlGaN barrier layer 105 in this order on a substrate 101 to form a GaN epitaxial wafer; in other embodiments, the GaN epitaxial wafer may be a GaN epitaxial wafer that is already used for manufacturing GaN devices, or may be formed on a common silicon wafer through a suitable process.
And cleaning and drying the surface of the GaN epitaxial wafer.
An InGaN thin layer region is formed on the surface of the AlGaN barrier layer 105 to form isolation regions of different device regions, which may specifically adopt, but is not limited to, the following two methods: the method comprises the steps of 1, depositing an InGaN insertion layer 106 outside an AlGaN barrier layer 105 by a metal organic compound chemical vapor deposition method or a molecular beam epitaxy method, etching the InGaN insertion layer 106 by an inductively coupled plasma etching method, only reserving InGaN thin layers in boundary areas of different device areas, and forming an isolation area with the InGaN insertion layer 106; method 2, depositing a layer of SiO on the surface of AlGaN barrier layer 1052As a growth barrier layer; defining an InGaN growth area by growing the barrier layer through yellow light photoetching; removing the growth barrier layer in the InGaN growth area by adopting dry etching or/and wet etching; depositing an InGaN insertion layer 106 by a metal organic chemical vapor deposition method or a molecular beam epitaxy method; and removing the growth barrier layer of the non-InGaN growth area by wet etching to form an isolation area with the InGaN insertion layer 106.
Depositing a passivation layer 107 on the surfaces of the AlGaN barrier layer 105 and the InGaN insertion layer 106; the passivation layer 107 is selected from SiN prepared by PECVD, LPCVD, ALD, or Sputter depositionx、SiO2、SiNO、Al2O3And AIN.
Respectively etching the ohmic contact holes of the device areas in each device area; specifically, an ICP process (plasma inductive coupling) is used to etch an ohmic contact hole on the passivation layer, and the etching is stopped inside the AlGaN barrier layer 105 or the AlGaN barrier layer 105 is completely removed.
Depositing ohmic metal in the ohmic contact hole; specifically, an ohmic contact hole is cleaned by HF, ohmic contact metal is deposited in the ohmic contact hole by adopting a magnetron sputtering method to form a Source electrode (Source level) and a Drain electrode (Drain level), the ohmic contact metal is in a Ti/Al/Ti/TiN structure, and after the ohmic contact metal is patterned, the N is at 850 DEG C2RTS 45s under atmosphere to ensure good ohmic contact characteristics.
And manufacturing a Gate electrode (Gate electrode) on a region where the Gate is to be formed in each device region.
The GaN device structure prepared by the above method is shown in the upper part of fig. 8, and comprises a substrate 101, a GaN buffer layer 102, a GaN channel layer 103 and an AlGaN barrier layer 105 which are sequentially arranged from bottom to top, wherein a plurality of independent device regions are formed on the AlGaN barrier layer 105, each device region is provided with an active electrode, a drain electrode and a gate electrode, a passivation layer 107 connected with the AlGaN barrier layer 105 covers between the electrodes, and an InGaN insertion layer 106 is arranged between the AlGaN barrier layer 105 and the passivation layer 107 in different device regions.
Theoretically, the thicker the InGaN insertion layer is, the higher the In component is, the thinner the AlGaN barrier layer is, the lower the Al component is, and the more obvious the electron depletion effect is; however, considering the overall performance of the device, the thickness and the Al component of the AlGaN barrier layer must reach certain values to ensure that enough electrons exist in the conduction channel of the device; on the other hand, from the perspective of the InGaN insertion layer, increasing the thickness and In composition of the InGaN insertion layer increases the difficulty of growth of the InGaN insertion layer, resulting In a sharp increase In manufacturing cost. Therefore, through a plurality of experiments and calculations of the inventor, the following reasonably selected numerical ranges are obtained: the deposition thickness of the InGaN insertion layer 106 is 5-15nm, and the In composition is selected within the range of 5% -30%; correspondingly, the deposition thickness of the AlGaN barrier layer 105 is 20-30nm, and the composition of Al is selected within the range of 5% -30%.
Preferably, In this embodiment, the InGaN insertion layer 106 is deposited with a thickness of 15nm and an In composition of 20%, and correspondingly, the AlGaN barrier layer 105 is deposited with a thickness of 20nm and an Al composition of 25%.
In summary, the thickness of the InGaN insertion layer 106 can adjust the electron depletion degree of the two-dimensional electron gas layer 104 by properly adjusting the AlGaN, the Al and In compositions In InGaN, and the AlGaN barrier layer 105.
The lower part of fig. 8 gives their band diagrams corresponding to the device and isolation regions, which can well illustrate the isolation effect of InGaN.
In conclusion, the patent provides a scheme for realizing isolation between devices by adopting an InGaN insertion layer method, an isolation region manufactured by using the scheme has high stability and good planarization, and simultaneously avoids the problems of interface damage and the like caused by etching, and the scheme is a good technical choice based on large-size platform mass production development.
The present invention has been described in terms of specific examples, which are provided to aid understanding of the invention and are not intended to be limiting. For a person skilled in the art to which the invention pertains, several simple deductions, modifications or substitutions may be made according to the idea of the invention.

Claims (10)

1. A method for realizing GaN device isolation based on an InGaN insertion layer comprises the following steps:
preparing a GaN epitaxial wafer, and forming a two-dimensional electron gas (104) between a GaN channel layer (103) and an AlGaN barrier layer (105) of the GaN epitaxial wafer, wherein an InGaN insertion layer (106) is arranged between different device regions of the GaN epitaxial wafer, the InGaN insertion layer (106) is arranged outside the AlGaN barrier layer (105), polarized negative charges are induced in a heterojunction between the InGaN insertion layer (106) and the AlGaN barrier layer (105), and the polarized negative charges deplete electrons in the two-dimensional electron gas (104) to realize the isolation of the different device regions.
2. The method according to claim 1, characterized in that it comprises in particular the steps of:
epitaxially growing a GaN buffer layer (102), a GaN channel layer (103) and an AlGaN barrier layer (105) on a substrate (101) in this order by a vapor deposition method;
forming an InGaN thin layer region on the surface of the AlGaN barrier layer (105) to form isolation regions of different device regions;
depositing a passivation layer (107) on the surfaces of the AlGaN barrier layer (105) and the InGaN thin layer region;
etching the ohmic contact holes of the device areas in each device area;
depositing ohmic metal in the ohmic contact hole;
patterning the ohmic metal and annealing at high temperature to form a source electrode and a drain electrode;
and manufacturing a gate electrode on a region where the gate is preset to be formed in each device region.
3. The method of claim 2, wherein forming an InGaN thin layer region on the surface of the AlGaN barrier layer (105) to form an isolation region for different device regions comprises the following steps:
depositing an InGaN insertion layer (106) on the surface of the AlGaN barrier layer (105);
and etching the InGaN insertion layer (106), and only reserving the InGaN thin layer in the boundary area of different device areas to form an isolation area with the InGaN insertion layer (106) reserved.
4. The method of claim 2, wherein forming an InGaN thin layer region on the surface of the AlGaN barrier layer (105) to form an isolation region for different device regions comprises the following steps:
depositing a layer of SiO on the surface of the AlGaN barrier layer (105)2As a growth barrier layer;
defining an InGaN growth area by growing the barrier layer through yellow light photoetching;
removing the growth barrier layer in the InGaN growth area by adopting dry etching or/and wet etching;
depositing an InGaN insertion layer (106);
and removing the growth barrier layer of the non-InGaN growth area by adopting wet etching to form an isolation area with the InGaN insertion layer (106) left.
5. The method of claim 3 or 4, wherein the GaN channel layer (103) is deposited to a thickness of 2-3 um.
6. The method of claim 5, wherein said AlGaN barrier layer (105) is deposited to a thickness of 20-30nm and has a composition of 5% -30% Al.
7. The method according to claim 6, characterized In that the InGaN insertion layer (106) is deposited with a thickness of 5-15nm and an In composition of 5% -30%.
8. The method according to claim 7, wherein the passivation layer (107) is selected from SiNx, SiO prepared by PECVD, LPCVD, ALD or Sputter deposition2、SiNO、Al2O3And AIN.
9. The GaN device for realizing isolation based on the InGaN insertion layer is characterized by comprising a substrate (101), a GaN buffer layer (102), a GaN channel layer (103) and an AlGaN barrier layer (105) which are sequentially arranged from bottom to top, wherein a plurality of independent device areas are formed on the AlGaN barrier layer (105), each device area is provided with an active electrode, a drain electrode and a gate electrode, a passivation layer (107) connected with the AlGaN barrier layer (105) covers between the electrodes, and the InGaN insertion layer (106) is arranged between the AlGaN barrier layer (105) and the passivation layer (107) in different device areas.
10. The GaN device of claim 9 wherein the AlGaN barrier layer (105) is deposited to a thickness of 20-30nm with an Al composition of 5% -30%; the deposition thickness of the InGaN insertion layer (106) is 5-15nm, and the In composition is 5% -30%.
CN201810771532.3A 2018-07-13 2018-07-13 Method for realizing GaN device isolation based on InGaN insertion layer Active CN109192698B (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CN201810771532.3A CN109192698B (en) 2018-07-13 2018-07-13 Method for realizing GaN device isolation based on InGaN insertion layer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CN201810771532.3A CN109192698B (en) 2018-07-13 2018-07-13 Method for realizing GaN device isolation based on InGaN insertion layer

Publications (2)

Publication Number Publication Date
CN109192698A CN109192698A (en) 2019-01-11
CN109192698B true CN109192698B (en) 2020-12-01

Family

ID=64936129

Family Applications (1)

Application Number Title Priority Date Filing Date
CN201810771532.3A Active CN109192698B (en) 2018-07-13 2018-07-13 Method for realizing GaN device isolation based on InGaN insertion layer

Country Status (1)

Country Link
CN (1) CN109192698B (en)

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849368A (en) * 1983-11-29 1989-07-18 Fujitsu Limited Method of producing a two-dimensional electron gas semiconductor device
JP2007311537A (en) * 2006-05-18 2007-11-29 National Institute Of Information & Communication Technology GaN-BASED FIELD EFFECT TRANSISTOR
US20100150194A1 (en) * 2008-12-15 2010-06-17 Opnext Japan, Inc. Nitride semiconductor optical element and manufacturing method thereof
CN103745993A (en) * 2014-01-22 2014-04-23 西安电子科技大学 Super-junction-based AlGaN/GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) high-voltage device and fabrication method thereof
CN105742383A (en) * 2016-02-25 2016-07-06 南京邮电大学 Suspended p-n junction quantum-well device and optical waveguide monolithic integrated system and fabrication method thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4849368A (en) * 1983-11-29 1989-07-18 Fujitsu Limited Method of producing a two-dimensional electron gas semiconductor device
JP2007311537A (en) * 2006-05-18 2007-11-29 National Institute Of Information & Communication Technology GaN-BASED FIELD EFFECT TRANSISTOR
US20100150194A1 (en) * 2008-12-15 2010-06-17 Opnext Japan, Inc. Nitride semiconductor optical element and manufacturing method thereof
CN103745993A (en) * 2014-01-22 2014-04-23 西安电子科技大学 Super-junction-based AlGaN/GaN MIS-HEMT (Metal-Insulator-Semiconductor High-Electron-Mobility Transistor) high-voltage device and fabrication method thereof
CN105742383A (en) * 2016-02-25 2016-07-06 南京邮电大学 Suspended p-n junction quantum-well device and optical waveguide monolithic integrated system and fabrication method thereof

Also Published As

Publication number Publication date
CN109192698A (en) 2019-01-11

Similar Documents

Publication Publication Date Title
US8450782B2 (en) Field effect transistor, method of manufacturing field effect transistor, and method of forming groove
US20160218204A1 (en) Enhancement Mode High Electron Mobility Transistor and Manufacturing Method Thereof
KR101285598B1 (en) Nitride baced heterostructure semiconductor device and manufacturing method thereof
JP5566670B2 (en) GaN-based field effect transistor
JP5367429B2 (en) GaN-based field effect transistor
KR20120125041A (en) High electron mobility transistor and method of manufacturing the same
KR101256466B1 (en) Nitride baced heterostructure semiconductor device and manufacturing method thereof
JP2009231458A (en) Field-effect transistor
CN111081763B (en) Normally-off HEMT device with honeycomb groove barrier layer structure below field plate and preparation method thereof
CN114899227A (en) Enhanced gallium nitride-based transistor and preparation method thereof
CN111384171B (en) High-channel mobility vertical UMOSFET device and preparation method thereof
CN103745992B (en) AlGaN/GaN MISHEMT high tension apparatus based on compound drain electrode and preparation method thereof
KR20120124101A (en) Nitride based heterostructure field effect transistor having high efficiency
JP2011210785A (en) Field-effect transistor and method for manufacturing the same
CN115732566A (en) UMOSFET device and method for improving performance of UMOSFET device
CN109192698B (en) Method for realizing GaN device isolation based on InGaN insertion layer
CN113394096B (en) HEMT device and self-isolation method and manufacturing method thereof
CN212542443U (en) Gallium nitride transistor structure and gallium nitride-based epitaxial structure
CN115692184A (en) P-AlGaN gate enhancement transistor based on selective wet etching process and preparation method
CN114883407A (en) HEMT based on Fin-FET gate structure and manufacturing method thereof
CN115472689A (en) High-electron-mobility transistor with super junction structure and preparation method thereof
CN114141871A (en) High-voltage-resistance enhanced HEMT device and preparation method thereof
CN107706238A (en) HEMT device and its manufacture method
TWI497721B (en) Enhanced gan transistor and the forming method thereof
CN115274845B (en) Concave Fin-MESFET gate structure HEMT and manufacturing method

Legal Events

Date Code Title Description
PB01 Publication
PB01 Publication
SE01 Entry into force of request for substantive examination
SE01 Entry into force of request for substantive examination
GR01 Patent grant
GR01 Patent grant