CN109189449B

CN109189449B - Multi-FPGA remote upgrading method based on CAN bus

Info

Publication number: CN109189449B
Application number: CN201811241881.0A
Authority: CN
Inventors: 全浩军; 所玉君; 崔建飞
Original assignee: Tianjin Jinhang Computing Technology Research Institute
Current assignee: Tianjin Jinhang Computing Technology Research Institute
Priority date: 2018-10-24
Filing date: 2018-10-24
Publication date: 2022-02-15
Anticipated expiration: 2038-10-24
Also published as: CN109189449A

Abstract

The invention discloses a multi-FPGA remote upgrading method based on a CAN bus, which comprises the steps of defining sub-IDs (identity) according to the number and priority of FPGAs (field programmable gate arrays), determining frame types, dividing ID domains, adding a CAN communication circuit for each FPGA, and finishing FPGA configuration chip partitioning and data integration programming; when the system runs, the FPGA is configured to be a CAN remote upgrading module function, a retrieval instruction sent by the upgrading server is responded, then the upgrading server sends a remote upgrading instruction for remote upgrading, and after the remote upgrading is finished, the FPGA is configured to be a normal function module. Compared with the traditional RS422 and RS485 bus mode and the local bus mode of adding the main control processor, the method avoids the great increase of hardware cost and enhances the reliability of the multi-FPGA remote upgrading system.

Description

Multi-FPGA remote upgrading method based on CAN bus

Technical Field

The invention belongs to the technical field of FPGA remote upgrading, and relates to a multi-FPGA remote upgrading method based on a CAN bus.

Background

Because the FPGA has the advantages of high integration level, strong parallelism and the like, the FPGA is widely applied to the fields of military affairs, medical treatment and consumer electronics. With the development of technologies such as deep learning and big data, the calculation amount is larger and larger, a single FPGA is far from meeting the calculation capability requirement of the system, and the multi-FPGA processing scheme is more and more emphasized by system developers.

The number of the FPGAs is increased to bring about the corresponding remote upgrading problem, the traditional multi-FPGA remote upgrading adopts the following two modes, one mode is based on an RS422 or RS485 bus, and the other mode is to increase a local bus mode adopted by a main control processor. The FPGA is connected in parallel through the RS422 or RS485 bus in a RS422 or RS485 bus mode, the remote upgrading function of multiple FPGAs can be realized when the system works normally, and once one node fails, the whole system is easy to break down and the reliability is poor. The local bus upgrading mode of the main control processor is added, so that the increase of the number of the FPGA is limited, and the hardware cost is greatly increased due to the introduction of the processor and the local bus decoding circuit.

Disclosure of Invention

Objects of the invention

The purpose of the invention is: the multi-FPGA remote upgrading method based on the CAN bus is provided, the hardware cost is prevented from being greatly increased, and the reliability of a multi-FPGA remote upgrading system is enhanced.

(II) technical scheme

In order to solve the technical problem, the invention provides a multi-FPGA remote upgrading method based on a CAN bus, which comprises the steps of defining sub-IDs (identity) according to the number and priority of FPGAs (field programmable gate arrays), determining frame types and dividing ID domains, then adding a CAN communication circuit for each FPGA, and finishing FPGA configuration chip partitioning and data integration programming; when the system runs, the FPGA is configured to be a CAN remote upgrading module function, a retrieval instruction sent by the upgrading server is responded, then the upgrading server sends a remote upgrading instruction for remote upgrading, and after the remote upgrading is finished, the FPGA is configured to be a normal function module. According to the method, due to the adoption of the connection mode of the CAN bus, each FPGA node CAN automatically detect errors and close the nodes if necessary, so that the whole system is not influenced, the reliability of the system is enhanced, and due to the fact that only the CAN communication circuit is added without adding an additional processor and a decoding circuit, the hardware cost is prevented from being greatly increased.

Aiming at various problems existing in the existing multi-FPGA remote upgrading method, the invention adopts the technical scheme that: a multi-FPGA remote upgrading method based on a CAN bus is characterized by comprising the following steps:

step 1, defining sub-IDs according to the number and priority of FPGAs; the number of the FPGAs is the number of the FPGAs which need to be upgraded at most in the system, and the FPGA priority is the FPGA upgrading priority when a plurality of FPGAs need to be upgraded; defining the sub-ID according to the FPGA number and the FPGA priority, wherein the sub-ID value starts from 0, the maximum value is equal to the FPGA number minus 1, and the smaller the sub-ID value is, the higher the priority is.

Step 2, determining the frame type and dividing ID fields; determining the frame type, namely selecting to use the standard data frame or the extended data frame according to the maximum value of the sub-ID, if the maximum value of the sub-ID is less than or equal to 15, selecting to use the standard data frame, and if not, using the extended data frame; dividing an ID area, namely dividing the ID area of a CAN bus data frame arbitration field into three parts, wherein the first part is defined by functions, occupies 3 binary bits, has a value range of 0 to 7, wherein the value 2 is used for sending fault data defined by a user, the value 4 is a retrieval instruction ID, the value 6 is an upgrading instruction ID, and the values 0, 1, 3, 5 and 7 are reserved for adding and using subsequent functions; the second part is a sub-ID, and the binary occupied digit of the sub-ID is the same as the maximum occupied digit of the sub-ID; the remaining part of the ID field is a third part representing the frame number, starting with 0, incrementing by 1, and restarting counting from 0 after reaching the maximum value;

step 3, adding a CAN communication circuit for each FPGA; the CAN communication circuit comprises a CAN protocol control chip, an optical coupler and an interface chip, wherein the CAN protocol control chip is directly connected with the FPGA and used for realizing CAN bus protocol analysis and data encapsulation; one end of the optocoupler is connected with the CAN protocol control chip, and the other end of the optocoupler is connected with the interface chip and used for realizing electrical isolation; the interface chip is connected with the CAN bus and provides a bus driving function; after a CAN communication circuit is added to each FPGA, the FPGA is connected in a bus type topological mode to form a CAN network, and a CAN interface is reserved for connecting an upgrading server; the upgrading server is a data transceiver with a CAN interface, is used for sending retrieval and remote upgrading instructions, is provided with a user interface, and CAN respond to user operation to realize upgrading control functions on a plurality of FPGAs.

Step 4, partitioning of the FPGA configuration chip and data integration programming are completed; partitioning the FPGA configuration chip, namely dividing the FPGA configuration chip into 4 areas in terms of logic use, wherein the first area is used for storing CAN remote upgrade module configuration data, the second area and the third area are respectively used for storing configuration data of a normal function module A and a normal function module B, and the fourth area is used for storing upgrade record data; the CAN remote upgrading module consists of 6 submodules, namely a master control submodule, a configuration chip read-write submodule, a reconstruction submodule, a parameter table, a buffer area and a CAN data transceiver, wherein the master control submodule is responsible for master control of remote upgrading and work scheduling of each submodule, the configuration chip read-write submodule realizes the read-write function of the FPGA configuration chip, the reconstruction submodule comprises watchdog logic and is used for realizing FPGA reconstruction, the FPGA CAN be configured to be the function of a normal function module A or a normal function module B under the triggering of timeout of the watchdog or other specified conditions, the parameter table submodule is used for storing data such as a sub-ID value, a timeout parameter and the like for the master control submodule to read, the buffer area is used for caching data received by a CAN bus, and the CAN data transceiver submodule is responsible for controlling a CAN communication circuit to complete the data transceiver function based on the CAN bus; the normal function module A and the normal function module B are both expected functions of the FPGA in a non-upgrading state, in order to ensure that the system CAN still normally work under the unexpected conditions of power failure and the like in the upgrading process, an A, B dual-module mode is adopted, the CAN remote upgrading module judges the previous upgrading condition through the upgrading recorded data of the fourth area, and the data covering the area corresponding to the module A or the area corresponding to the module B is selected; the upgrade record data comprises three parts of contents, wherein the first part records whether the latest upgrade covers the normal function module A or the normal function module B, the second part records whether the data of the normal function module A is complete, and the third part records whether the data of the normal function module B is complete; and data integration programming, namely compiling the logic functions of the CAN remote upgrading module, the normal function module A and the normal function module B into configuration data through software after the logic functions of the CAN remote upgrading module, the normal function module A and the normal function module B are realized, and programming the configuration data into a configuration chip of the FPGA after the logic functions are integrated, wherein the sub-ID values of each FPGA are different, so that the initialization data of the sub-modules of the parameter table are different.

Step 5, operating the system, wherein the FPGA is configured to a CAN remote upgrading module function; after the system is powered on and started, the FPGA automatically reads configuration data from a first area of a configuration chip, and the FPGA is configured to be the function of a CAN remote upgrading module; the CAN remote upgrading module firstly reads upgrading record data in a configuration chip and processes the upgrading record data according to the following conditions:

if the last upgrade is recorded to cover neither the normal function module A nor the normal function module B, it indicates that the remote upgrade has not been performed after the programming of the configuration chip is completed, and at this time, the module to be reconstructed and the module to be upgraded are both designated as the normal function module A.

If the last upgrade is recorded to cover the normal function module A, further judging whether the data of the normal function module A is complete, if A is complete, designating the module to be reconstructed as the normal function module A, designating the module to be upgraded as the normal function module B, if A is incomplete, further judging whether the data of the normal function module B is complete, if B is complete, designating the module to be reconstructed as the normal function module B, designating the module to be upgraded as the normal function module A, and if B is incomplete, designating both the module to be reconstructed and the module to be upgraded as the normal function module B, simultaneously generating fault data and waiting for subsequent transmission.

If the last upgrade is recorded to cover the normal function module B, further judging whether the data of the normal function module B is complete, if so, designating the module to be reconstructed as the normal function module B, designating the module to be upgraded as the normal function module A, if not, further judging whether the data of the normal function module A is complete, if so, designating the module to be reconstructed as the normal function module A, designating the module to be upgraded as the normal function module B, and if not, designating both the module to be reconstructed and the module to be upgraded as the normal function module A, simultaneously generating fault data and waiting for subsequent transmission.

After the module to be reconstructed and the module to be upgraded are determined, if the fault data is not generated, the CAN remote upgrading module reads the overtime parameter from the parameter table submodule and writes the overtime parameter and the configuration data information of the module to be reconstructed into the reconstruction submodule to enable the watchdog, and if the fault data is generated, the operation is not carried out.

Step 6, the upgrade server sends a retrieval instruction, and each FPGA responds; if remote upgrading is needed, before the system is operated in the step 5, the upgrading server accesses the CAN network through the CAN interface reserved in the step 3, and continuously sends remote frames with retrieval instruction IDs and sequentially increasing sub ID values from 0 in the starting process of the system, and each FPGA carries out the following processing after receiving the remote frames:

and the CAN remote upgrading module reads the sub-ID value in the parameter table sub-module, judges whether the sub-ID value is the same as the sub-ID value of the received remote frame or not, if the sub-ID value is different from the sub-ID value of the received remote frame, does not send the corresponding data frame, and otherwise sends the data frame with the same retrieval instruction ID and the sub-ID value of the CAN remote upgrading module.

When the data frame is transmitted, if the FPGA does not generate fault data in the step 5, the initial byte of the data field in the transmitted data frame is 0xFF, and the dog feeding operation is performed after the data frame is transmitted, otherwise, the data field is filled with 0x00+ fault data.

And the upgrading server receives the data frame fed back by the FPGA corresponding to the sub-ID value and feeds back the fault-free or fault information indicated by the data frame to the user through an interface, so that the user can select upgrading.

In order to ensure that the watchdog does not time out before the corresponding FPGA finishes upgrading, the remote frame sending period corresponding to each sub-ID value of the upgrading server is smaller than the watchdog timeout parameter of the CAN remote upgrading module in the FPGA corresponding to the sub-ID value.

And 7, the upgrading server sends a remote upgrading instruction to carry out remote upgrading. A user designates an FPGA (field programmable gate array) to be upgraded and corresponding upgrading data, an upgrading server divides the upgrading data into a plurality of data frames, numbers each data frame and sends out the data frames with upgrading instruction ID, sub-ID values, frame serial numbers and upgrading data according to the frame serial numbers in sequence; and after receiving the first upgrade data frame, the FPGA to be upgraded firstly modifies the upgrade record data in the configuration chip area IV, modifies the latest upgrade coverage area into the module area to be upgraded appointed in the step 5, and marks the data in the area as incomplete. Then, integrating the upgrading data according to the frame serial number, writing the data into the specified module area to be upgraded in the step 5, if a certain frame serial number is missing in the receiving process, according to the step 2, sending a fault data frame with the function defined as 2 and the frame serial number as the missing frame serial number, and retransmitting the frame with the serial number after the server receives the fault data frame; after all the upgrade data are sent, the upgrade server sends a retrieval instruction to the FPGA again, the frame number of the retrieval instruction is +1 of the remote upgrade data frame sent last time, the upgraded FPGA judges whether the last data frame with the upgrade data is received completely according to the sequence number, the data frame corresponding to the corresponding retrieval instruction is sent to the upgrade server, if the data frame is received completely, the first byte of the data field in the sent data frame is 0x5A, otherwise, the first byte is 0xA5, the server retransmits the last remote upgrade data frame and the remote frame of the retrieval instruction after receiving the data frame with the first byte 0xA5 data field, receives the returned data frame again and judges until the data frame with the first byte 0x5A data field is received, and informs the user of the completion of the upgrade.

If the upgraded FPGA does not generate fault data in the step 5, in the upgrading process, a watchdog feeding operation is performed every time a data frame with upgrading data is received to avoid overtime of a corresponding watchdog, and the remote upgrading data frame sending period of the upgrading server is smaller than the watchdog overtime parameter of the CAN remote upgrading module in the upgraded FPGA.

And 8, finishing remote upgrading, and configuring the FPGA as a normal functional module. After the server informs the user that the upgrade is finished, the server does not send any frame to the upgraded FPGA any more, and the upgraded FPGA marks the area of the module to be upgraded, which is appointed in the step 5 in the four upgrade record data of the configuration chip area, as complete after the upgrade is finished; if no fault data is generated in the step 5, no dog feeding operation is performed after the marking is finished, the FPGA automatically reconstructs the function of the module to be reconstructed appointed in the step 5, if the fault data is generated in the step 5, the main control sub-module informs the reconstruction sub-module to reconstruct immediately after the marking is finished, and the FPGA is configured as a normal function module.

(III) advantageous effects

Compared with the RS422 and RS485 bus mode and the local bus mode of adding the main control processor, the multi-FPGA remote upgrading method based on the CAN bus has the advantages that the connection mode of the CAN bus is adopted, the hardware cost is prevented from being greatly increased, the reliability of a multi-FPGA remote upgrading system is enhanced, in addition, the method does not need complex hardware connection in the implementation process, the number of the FPGAs to be upgraded CAN be dynamically changed after the system is built, and the method has strong practical value.

Drawings

Fig. 1 is a schematic diagram of functional connection when an FPGA is configured as a CAN remote upgrade module in a CAN bus-based multi-FPGA remote upgrade method of the present invention.

Fig. 2 is a branch schematic diagram of the multi-FPGA remote upgrade method based on the CAN bus, in which step 5 designates a module to be reconstructed and a module to be upgraded.

Detailed Description

In order to make the objects, contents and advantages of the present invention clearer, the following detailed description of the embodiments of the present invention will be made in conjunction with the accompanying drawings and examples.

Referring to fig. 1 and 2, the specific implementation steps of the multi-FPGA remote upgrade method based on the CAN bus of the present invention are as follows:

the FPGA and configuration chip of this example are selected from EP3C55 from Altera and EPCS128 from the same company, respectively, using Quartus II development environment, using ALTAMI _ PARALLEL, ALTREMATE _ UPDATE, ROM: the 1-PORT and the RAM are 2-PORT, 4 kinds of IP cores are shared, wherein the ALTASMI _ PARALLEL IP core is used for constructing a read-write submodule of the configuration chip and realizing the read-write of the EPCS128 of the configuration chip; the ALTREMATE _ UPDATE IP core is used for constructing a reconstruction submodule to realize the reconstruction function of the FPGA; ROM: the 1-PORT IP core is used for constructing a parameter table submodule; and the RAM 2-PORT IP core is used for constructing a buffer area submodule.

The specific application environment of this example is: the system has 8 FPGAs which need to be remotely upgraded, and the method comprises the following specific steps:

step 1, defining sub-IDs according to the number and priority of FPGAs; the number of the FPGAs is 8, the sub-ID values of the FPGAs are defined to be 0-7 according to priority ranking, and the smaller the sub-ID value is, the higher the priority is.

Step 2, determining the frame type and dividing ID fields; determining the frame type, and selecting to use a standard data frame because the maximum value of the sub-ID is 7 and is less than 15; dividing an ID area, namely dividing the ID area of a CAN bus data frame arbitration field into three parts, wherein the first part is defined by functions, occupies 3 binary bits, has a value range of 0 to 7, wherein the value 2 is used for sending fault data defined by a user, the value 4 is a retrieval instruction ID, the value 6 is an upgrading instruction ID, and the values 0, 1, 3, 5 and 7 are reserved for adding and using subsequent functions; the second part is a sub-ID and occupies 3 binary bits; the remaining 5 binary digits of the ID field are the third part, represent the frame number, range from 0 to 31, increment by 1, and restart counting from 0 after reaching 31;

Step 4, partitioning of the FPGA configuration chip and data integration programming are completed; partitioning the FPGA configuration chip, namely dividing the FPGA configuration chip into 4 areas in terms of logic use, wherein the first area is used for storing CAN remote upgrade module configuration data, the second area and the third area are respectively used for storing configuration data of a normal function module A and a normal function module B, and the fourth area is used for storing upgrade record data; the CAN remote upgrading module consists of 6 submodules, namely a master control submodule, a configuration chip read-write submodule, a reconstruction submodule, a parameter table, a buffer area and a CAN data transceiver, wherein the master control submodule is responsible for master control of remote upgrading and work scheduling of each submodule, the configuration chip read-write submodule realizes the read-write function of the FPGA configuration chip, the reconstruction submodule comprises watchdog logic and is used for realizing FPGA reconstruction, the FPGA CAN be configured to be the function of a normal function module A or a normal function module B under the triggering of timeout of the watchdog or other specified conditions, the parameter table submodule is used for storing data such as a sub-ID value, a timeout parameter and the like for the master control submodule to read, the buffer area is used for caching data received by a CAN bus, and the CAN data transceiver submodule is responsible for controlling a CAN communication circuit to complete the data transceiver function based on the CAN bus; the normal function module A and the normal function module B are both expected functions of the FPGA in a non-upgrading state, in order to ensure that the system CAN still normally work under the unexpected conditions of power failure and the like in the upgrading process, an A, B dual-module mode is adopted, the CAN remote upgrading module judges the previous upgrading condition through the upgrading recorded data of the fourth area, and the data covering the area corresponding to the module A or the area corresponding to the module B is selected; the upgrade record data comprises contents of three parts, wherein the first part uses 2 binary bits, wherein 00 represents that the latest upgrade covers neither the normal function module A nor the normal function module B, 01 represents that the latest upgrade covers the normal function module A, 10 represents that the latest upgrade covers the normal function module B, the second part uses 1 binary bit, 0 represents that the data of the normal function module A is incomplete, 1 represents that the data of the normal function module A is complete, and the like, the third part uses 1 binary bit, 0 represents that the data of the normal function module B is incomplete, and 1 represents that the data of the normal function module B is complete; and data integration programming, namely compiling the logic functions of the CAN remote upgrading module, the normal function module A and the normal function module B into configuration data through software after the logic functions of the CAN remote upgrading module, the normal function module A and the normal function module B are realized, and programming the configuration data into a configuration chip of the FPGA after the logic functions are integrated, wherein the sub-ID values of each FPGA are different, so that the initialization data of the sub-modules of the parameter table are different.

if the first part of the upgrade record data is 00, it indicates that the remote upgrade has not been performed after the configuration chip is programmed, and at this time, the module to be reconstructed and the module to be upgraded are both designated as a normal function module A.

If the first part of the upgrade record data is 01, further judging whether the second part of the upgrade record data is 1, if so, designating the module to be reconstructed as a normal function module A, designating the module to be upgraded as a normal function module B, if so, further judging whether the third part of the upgrade record data is 1, if so, designating the module to be reconstructed as a normal function module B, designating the module to be upgraded as a normal function module A, and if so, designating both the module to be reconstructed and the module to be upgraded as a normal function module B, simultaneously generating fault data and waiting for subsequent transmission.

If the first part of the upgrade record data is 10, further judging whether the third part of the upgrade record data is 1, if so, designating the module to be reconstructed as a normal function module B, designating the module to be upgraded as a normal function module A, if so, further judging whether the second part of the upgrade record data is 1, if so, designating the module to be reconstructed as the normal function module A, designating the module to be upgraded as the normal function module B, and if so, designating both the module to be reconstructed and the module to be upgraded as the normal function module A, and simultaneously generating fault data for subsequent transmission.

The above description is only a preferred embodiment of the present invention, and it should be noted that, for those skilled in the art, several modifications and variations can be made without departing from the technical principle of the present invention, and these modifications and variations should also be regarded as the protection scope of the present invention.

Claims

1. A multi-FPGA remote upgrading method based on a CAN bus is characterized by comprising the following steps:

step 1, defining sub-IDs according to the number and priority of FPGAs;

step 2, determining the frame type and dividing ID fields;

step 3, adding a CAN communication circuit for each FPGA;

step 4, partitioning of the FPGA configuration chip and data integration programming are completed;

step 5, operating the system, wherein the FPGA is configured to a CAN remote upgrading module function;

step 6, the upgrade server sends a retrieval instruction, and each FPGA responds;

step 7, the upgrading server sends a remote upgrading instruction to carry out remote upgrading;

in the step 1, the number of the FPGAs is the number of the FPGAs which need to be upgraded at most in the system, and the FPGA priority is the FPGA upgrading priority when a plurality of FPGAs need to be upgraded; defining sub-IDs according to the number of the FPGAs and the priority of the FPGAs, wherein the sub-IDs start from 0, the maximum value is equal to the number of the FPGAs minus 1, and the smaller the sub-ID value is, the higher the priority is;

in step 2, determining a frame type, that is, selecting to use a standard data frame or an extended data frame according to the maximum value of the sub-ID, if the maximum value of the sub-ID is less than or equal to 15, selecting to use the standard data frame, otherwise, using the extended data frame; dividing an ID area, namely dividing the ID area of a CAN bus data frame arbitration field into three parts, wherein the first part is defined by functions, occupies 3 binary bits, has a value range of 0 to 7, wherein the value 2 is used for sending fault data defined by a user, the value 4 is a retrieval instruction ID, the value 6 is an upgrading instruction ID, and the values 0, 1, 3, 5 and 7 are reserved for adding and using subsequent functions; the second part is a sub-ID, and the binary occupied digit of the sub-ID is the same as the maximum occupied digit of the sub-ID; the remaining part of the ID field is a third part representing the frame number, starting with 0, incrementing by 1, and restarting counting from 0 after reaching the maximum value;

in the step 3, the CAN communication circuit comprises a CAN protocol control chip, an optical coupler and an interface chip, wherein the CAN protocol control chip is connected with the FPGA and used for realizing CAN bus protocol analysis and data encapsulation; one end of the optocoupler is connected with the CAN protocol control chip, and the other end of the optocoupler is connected with the interface chip and used for realizing electrical isolation; the interface chip is connected with the CAN bus and provides a bus driving function; after a CAN communication circuit is added to each FPGA, the FPGA is connected in a bus type topological mode to form a CAN network, and a CAN interface is reserved for connecting an upgrading server; the upgrading server is a data transceiver with a CAN interface, is used for sending retrieval and remote upgrading instructions, is provided with a user interface, and responds to user operation to realize upgrading control functions on the plurality of FPGAs;

in the step 4, the FPGA configuration chip is partitioned into 4 areas in terms of logical use, a first area is used for storing configuration data of the CAN remote upgrade module, a second area and a third area are respectively used for storing configuration data of the normal function module a and the normal function module B, and a fourth area is used for storing upgrade record data; the CAN remote upgrading module judges the previous upgrading condition through the upgrading recorded data of the fourth area and selects the data covering the area corresponding to the normal function module A or the area corresponding to the normal function module B; the upgrade record data comprises three parts of contents, wherein the first part records whether the latest upgrade covers the normal function module A or the normal function module B, the second part records whether the data of the normal function module A is complete, and the third part records whether the data of the normal function module B is complete; and data integration programming, namely after the logic functions of the CAN remote upgrading module, the normal function module A and the normal function module B are realized, compiling the logic functions into configuration data through software, and programming the configuration data into a configuration chip of the FPGA after integration.

2. The CAN bus-based multi-FPGA remote upgrade method of claim 1, wherein in step 4, when the configuration data is burned into the configuration chip of the FPGA, the sub-ID value of each FPGA is different, and the initialization data of the parameter table sub-module is different.

3. The CAN bus based multi-FPGA remote upgrade method of claim 2, it is characterized in that in the step 4, the CAN remote upgrading module comprises 6 sub-modules of main control, read-write of configuration chip, reconstruction, parameter table, buffer area and CAN data receiving and transmitting, the main control sub-module is responsible for the main flow control of remote upgrading and the work scheduling of each sub-module, the read-write sub-module of the configuration chip realizes the read-write function of the FPGA configuration chip, the reconstruction sub-module comprises watchdog logic for realizing FPGA reconstruction, the FPGA is configured to be the function of a normal function module A or a normal function module B under the trigger of the overtime of the watchdog or other specified conditions, the parameter table submodule is used for storing a sub-ID value and an overtime parameter for the main control submodule to read, the buffer area is used for caching data received by the CAN bus, and the CAN data receiving and transmitting submodule is used for controlling the CAN communication circuit to complete the data receiving and transmitting function based on the CAN bus.

4. The CAN bus-based multi-FPGA remote upgrade method according to claim 3, wherein in said step 5, after the system is powered on and started, the FPGA automatically reads the configuration data from the first area of the configuration chip, and the FPGA is configured as a function of the CAN remote upgrade module; the CAN remote upgrading module firstly reads upgrading record data in a configuration chip and processes the upgrading record data according to the following conditions:

if the last upgrade is recorded to cover neither the normal function module A nor the normal function module B, the remote upgrade is not performed after the programming of the configuration chip is completed, and at the moment, the module to be reconstructed and the module to be upgraded are designated as the normal function module A;

if the last upgrade is recorded to cover the normal function module A, further judging whether the data of the normal function module A is complete, if A is complete, designating the module to be reconstructed as the normal function module A, designating the module to be upgraded as the normal function module B, if A is incomplete, further judging whether the data of the normal function module B is complete, if B is complete, designating the module to be reconstructed as the normal function module B, designating the module to be upgraded as the normal function module A, and if B is incomplete, designating both the module to be reconstructed and the module to be upgraded as the normal function module B, simultaneously generating fault data and waiting for subsequent transmission;

if the last upgrade is recorded to cover the normal function module B, further judging whether the data of the normal function module B is complete, if so, designating the module to be reconstructed as the normal function module B, designating the module to be upgraded as the normal function module A, if not, further judging whether the data of the normal function module A is complete, if so, designating the module to be reconstructed as the normal function module A, designating the module to be upgraded as the normal function module B, and if not, designating both the module to be reconstructed and the module to be upgraded as the normal function module A, simultaneously generating fault data and waiting for subsequent transmission;

5. The CAN-bus-based multi-FPGA remote upgrade method according to claim 4, wherein in step 6, if remote upgrade is required, before the system is operated in step 5, the upgrade server has accessed the CAN network through the CAN interface reserved in step 3, and continuously transmits a remote frame with a retrieval command ID and sequentially increasing sub-ID values from 0 during system start-up, and each FPGA performs the following processing after receiving the remote frame:

the CAN remote upgrading module reads the sub-ID value in the parameter table sub-module, judges whether the sub-ID value is the same as the sub-ID value of the received remote frame, if the sub-ID value is different from the sub-ID value of the received remote frame, the corresponding data frame is not sent, and if the sub-ID value is not the same as the sub-ID value of the received remote frame, the data frame with the retrieval instruction ID and the sub-ID value of the CAN remote upgrading module is sent;

when a data frame is sent, if the FPGA does not generate fault data in the step 5, the first byte of the data field in the sent data frame is 0xFF, and the dog feeding operation is carried out after the data frame is sent, otherwise, the data field is filled with 0x00+ fault data;

the upgrading server receives the data frame fed back by the FPGA corresponding to the sub-ID value, and feeds back the information of no fault or fault indicated by the data frame to the user through an interface for the user to select upgrading;

6. The CAN bus-based multi-FPGA remote upgrade method according to claim 5, wherein in said step 7, the user designates the FPGA to be upgraded and the corresponding upgrade data, the upgrade server divides the upgrade data into a plurality of data frames, numbers each data frame, and sends out the data frames with the upgrade command ID, the sub-ID value, the frame number and the upgrade data in sequence according to the frame number; after receiving a first upgrade data frame, the FPGA to be upgraded firstly modifies upgrade record data in a configuration chip area IV, modifies a latest upgrade coverage area into a module area to be upgraded appointed in the step 5, marks the data in the area as incomplete, then integrates the upgrade data according to a frame number, writes the data into the module area to be upgraded appointed in the step 5, if a certain frame number is missing in the receiving process, sends a fault data frame with the function defined as 2 and the frame number as the missing frame number according to the step 2, and retransmits the frame of the number after the server receives the fault data frame; after all the upgrade data are sent, the upgrade server sends a retrieval instruction to the FPGA again, the frame number of the retrieval instruction is +1 of the remote upgrade data frame sent last time, the upgraded FPGA judges whether the last data frame with the upgrade data is received completely according to the sequence number, the data frame corresponding to the corresponding retrieval instruction is sent to the upgrade server, if the data frame is received completely, the first byte of the data field in the sent data frame is 0x5A, otherwise, the first byte is 0xA5, the server retransmits the last remote upgrade data frame and the remote frame of the retrieval instruction after receiving the data frame with the first byte 0xA5 data field, receives the returned data frame again and judges until the data frame with the first byte 0x5A data field is received, and informs the user of the completion of the upgrade;

if the upgraded FPGA does not generate fault data in the step 5, in the upgrading process, a watchdog feeding operation is performed once every time a data frame with upgrading data is received to avoid overtime of a corresponding watchdog, and the remote upgrading data frame sending period of an upgrading server is smaller than a watchdog overtime parameter of a CAN remote upgrading module in the upgraded FPGA;

in step 8, after the server notifies the user that the upgrade is completed, the server does not send any frame to the upgraded FPGA any more, and the upgraded FPGA marks the module area to be upgraded specified in step 5 in the four upgrade record data of the configuration chip area as complete after the upgrade is completed; if no fault data is generated in the step 5, no dog feeding operation is performed after the marking is finished, the FPGA automatically reconstructs the function of the module to be reconstructed appointed in the step 5, if the fault data is generated in the step 5, the main control sub-module informs the reconstruction sub-module to reconstruct immediately after the marking is finished, and the FPGA is configured as a normal function module.