CN109166524B

CN109166524B - Display panel

Info

Publication number: CN109166524B
Application number: CN201811154428.6A
Authority: CN
Inventors: 郑贸熏; 洪嘉泽; 黄正翰; 陈勇志; 郑景升
Original assignee: AU Optronics Corp
Current assignee: AU Optronics Corp
Priority date: 2018-07-13
Filing date: 2018-09-30
Publication date: 2020-03-20
Anticipated expiration: 2038-09-30
Also published as: TWI673695B; TW202006691A; CN109166524A

Abstract

The embodiment of the invention provides a display panel. The display panel is provided with a peripheral area and a display area. The pixel string including multiple sub-pixels is arranged in the display area, each sub-pixel is electrically connected to a data line, and a first switch is arranged between the data line and the data driver. The external critical voltage compensation circuit is arranged in the peripheral area and is electrically connected with the data line through the second switch so as to sequentially compensate one of the sub-pixels. In the first period and the third period when the second switch is turned on, the external critical voltage compensation circuit provides the first reference voltage or the second reference voltage to the sub-pixel through the data line. In a second period and a fourth period when the second switch is turned on, the external critical voltage compensation circuit detects a first sensing current or a second sensing current flowing through the driving transistor of the sub-pixel through the data line and generates a first integral value or a second integral value.

Description

Display panel

Technical Field

The present invention relates to a display panel, and more particularly, to a display panel having an external threshold voltage compensation circuit.

Background

During the operation of the display, the Thin-Film Transistor (TFT) may have its threshold voltage varied due to process influence or other operation conditions, which results in uneven brightness of the display screen and also degrades the display quality. In general, the threshold voltage compensation circuit compensates for the variation of the threshold voltage of the thin film transistor, and the conventional threshold voltage compensation circuit is composed of a plurality of thin film transistors and a storage capacitor disposed in a pixel, which is called as an internal threshold voltage compensation circuit.

However, in the current trend of higher resolution, more pixels are required to be disposed on the display panel. Due to the limited space on the panel, the internal threshold voltage compensation circuit within the pixel must be used. In addition, the compensation time available for the internal threshold voltage compensation circuit within the pixel is related to the time for writing data into the pixel. Therefore, as the resolution becomes higher, the compensation time available for the internal threshold voltage compensation circuit in the pixel becomes relatively shorter.

Disclosure of Invention

In view of the above, the present invention provides an external threshold voltage compensation circuit disposed outside a pixel. To achieve the above objectives, embodiments of the present invention provide a display panel having a peripheral area (peripheralarea) and a display area (display area). The pixel string including multiple sub-pixels is arranged in the display area, each sub-pixel is electrically connected to a data line, and a first switch is arranged between the data line and the data driver. The external critical voltage compensation circuit is arranged in the peripheral area and is electrically connected with the data line through the second switch so as to sequentially compensate one of the sub-pixels. During the first period when the second switch is turned on, the external threshold voltage compensation circuit provides a first reference voltage to the sub-pixel through the data line. During a second period when the second switch is turned on, the external threshold voltage compensation circuit detects a first sensing current flowing through the driving transistor of the sub-pixel through the data line and generates a first integration value. In a third period when the second switch is turned on, the external threshold voltage compensation circuit provides a second reference voltage to the sub-pixel through the data line, wherein the first reference voltage and the second reference voltage are both less than or equal to a sum of a first supply voltage of a light emitting diode electrically connected to the sub-pixel and a turn-on voltage (turn-on voltage) of the light emitting diode, and the second reference voltage is not equal to the first reference voltage. During a fourth period when the second switch is turned on, the external threshold voltage compensation circuit detects a second sensing current flowing through the driving transistor of the sub-pixel through the data line and generates a second integration value.

For a better understanding of the nature and technical content of the present invention, reference should be made to the following detailed description of the invention and to the accompanying drawings, which are provided for purposes of illustration only and are not intended to limit the scope of the invention as defined by the appended claims.

Drawings

Fig. 1 is a functional block diagram of a display panel according to an embodiment of the present invention.

FIG. 2 is a circuit diagram of an external threshold voltage compensation circuit in the display panel of FIG. 1.

Fig. 3A to 3E are schematic diagrams illustrating the operation of the external threshold voltage compensation circuit of fig. 2 when compensating for the sub-pixel.

FIG. 4 is a timing diagram illustrating the sub-pixel compensation performed by the external threshold voltage compensation circuit of FIG. 2.

FIG. 5 is a schematic diagram of the external threshold voltage compensation circuit of FIG. 2 according to another embodiment.

Fig. 6A to 6C are schematic views illustrating the operation of the sub-pixels in the display panel of fig. 1 during the display period.

FIG. 7 is a timing diagram of a sub-pixel in the display panel of FIG. 1 during a display period.

FIG. 8 is a circuit diagram of a sub-pixel in the display panel of FIG. 1 according to another embodiment.

Wherein the reference numerals are as follows:

1: display panel

10: peripheral zone

20: display area

11: data driver

12: scan driver

13: sensing driver

14: time sequence controller

15[0] to 15[ m ]: external critical voltage compensation circuit

151: operational amplifier

153: feedback unit

155: analog-to-digital converter

157: memory device

159: data update unit

DATA, DATAc: displaying data

CINT: capacitor with a capacitor element

SW1[0] -SW 1[ m ]: first switch

SW2[0] -SW 1[ m ]: second switch

SW 3: third switch

SW 4: the fourth switch

SW 5: fifth switch

VREF 1: a first reference voltage

VREF 2: second reference voltage

I1: a first sensing current

I2: second sensing current

Δ O1: first integral value

Δ O2: second integral value

21[0] to 21[ m ]: pixel string

22[0] to 22[ n ]: sub-pixel

DL [0] to DL [ m ]: data line

An OLED: light emitting diode

TD: driving transistor

CST, CST': storage capacitor

T1-T3, T1 '-T2': switching transistor

OVDD, OVSS: supply voltage

P1, P2, P3: node point

EM [0] to EM [ n ]: light emission control signal

S [0] to S [ n ]: scanning signal

R < 0 > -R < n >: sensing signal

Detailed Description

Hereinafter, the present invention will be described in detail by illustrating various embodiments of the present invention through the accompanying drawings. The inventive concept may, however, be embodied in many different forms and should not be construed as limited to the exemplary embodiments set forth herein. Moreover, in the drawings, like reference numerals may be used to designate like elements.

In particular, the display panel provided by the embodiment of the present invention may refer to any type of display panel. In other words, the present invention is not limited to the specific implementation of the display panel, and those skilled in the art should be able to design the display panel according to actual needs or applications. For the sake of convenience of the following description, the present embodiment will be described with reference to an Active Matrix Organic Light Emitting Diode (AMOLED) display panel. For example, referring to fig. 1, fig. 1 is a functional block diagram of a display panel according to an embodiment of the present invention.

As shown in fig. 1, the display panel 1 has a peripheral region 10 and a display region 20. As known in the art, the peripheral region 10 generally includes a data driver 11, a scan driver 12, a sensing driver 13 and a timing controller 14. In addition, a plurality of pixel strings, such as pixel string 21[0] to pixel string 21[ m ], are disposed on the display region 20, and each pixel string includes a plurality of sub-pixels, such as sub-pixel 22[0] to sub-pixel 22[ n ]. In this embodiment, m and n may be any positive integer greater than 1. In summary, since the present invention does not limit the resolution of the display panel 1, those skilled in the art should be able to design m and n according to actual requirements or applications.

However, for the sake of convenience of the following description, the present embodiment will be described by only discussing a single pixel string, for example, the pixel string 21[0 ]. It should be understood that each sub-pixel 22[0] 22[ n ] of the pixel string 21[0] is electrically connected to the data line DL [0] and receives display data (not shown) from the data driver 11 via the data line DL [0 ]. In the present embodiment, a first switch SW1[0] is provided between the data line DL [0] and the data driver 11. In addition, an external threshold voltage compensation circuit 15[0] is disposed in the peripheral region 10 and electrically connected to the data line DL [0] through a second switch SW2[0] for sequentially compensating one of the sub-pixels 22[0] to 22[ n ].

Based on the above disclosure, it should be understood by those skilled in the art that each sub-pixel 22[0] to 22[ n ] has an internal threshold voltage compensation circuit in the prior art design, but the display panel 1 of the present embodiment may have a plurality of sub-pixels in the same row (column), that is, the sub-pixels 22[0] to 22[ n ] of the pixel string 21[0] share the same external threshold voltage compensation circuit 15[0], and the external threshold voltage compensation circuit 15[0] is disposed in the peripheral region 10, that is, the routing region between the display region 20 and the data driver 11, so that the present embodiment can greatly simplify the number of transistor elements required for each sub-pixel 22[0] to 22[ n ], so as to further improve the layout (layout) flexibility of the display region 20 and facilitate achieving higher resolution.

On the other hand, in the present embodiment, the first switch SW1[0] and the second switch SW2[0] are not turned on at the same time. That is, the compensation time used by the external threshold voltage compensation circuit 15[0] of the present embodiment is not related to the time for writing data into the sub-pixels 22[0] to 22[ n ]. Therefore, even when the resolution of the display panel 1 is increased, for example, the data lines and the scan lines of the display panel 1 are increased, the compensation time allocated by the external threshold voltage compensation circuit 15[0] is not decreased compared to the compensation time of the internal threshold voltage compensation circuit disposed in the sub-pixel due to the increased resolution. For example, in the present invention, the use condition of an embodiment may be that the first switch SW1[0] is turned off and the second switch SW2[0] is turned on by the control during each time the display panel 1 is turned on and the black screen before the normal picture is not displayed, so that the external compensation circuit 15[0] sequentially compensates for each of the sub-pixels 22[0] to 22[ n ], but the present invention is not limited thereto. The external compensation circuit 15[0] may perform the threshold voltage compensation setting in advance when the display panel 1 is not integrated with the display device or the mobile device.

Next, for convenience of the following description, the present embodiment will be described by only considering an example in which the external threshold voltage compensation circuit 15[0] compensates the sub-pixel 22[0 ]. Referring to fig. 2, fig. 2 is a circuit diagram of an external threshold voltage compensation circuit in the display panel of fig. 1. In fig. 2, the same elements as those in fig. 1 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein. In the present embodiment, the external threshold voltage compensation circuit 15[0] may include an operational amplifier 151 and a feedback unit 153. The inverting input terminal (inverting input) of the operational amplifier 151 is electrically connected to the second switch SW2[0], the non-inverting input terminal (non-inverting input) of the operational amplifier 151 selectively receives the first reference voltage VREF1 or the second reference voltage VREF2, and the output terminal of the operational amplifier 151 outputs the first integral value Δ O1 or the second integral value Δ O2 (see fig. 3B and fig. 3D).

The feedback unit 153 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier 151, and is composed of a passive element (passive component) and a third switch SW3 connected in parallel. In this embodiment, the passive element may be, for example, a capacitor CINT, but the invention is not limited thereto. For example, in other embodiments, the passive component may also be a resistor RFB (not shown), for example. In summary, the present invention is not limited to the specific implementation of the passive components, and those skilled in the art should be able to design the passive components according to actual needs or applications. However, in order to allow the non-inverting input terminal of the operational amplifier 151 to selectively receive the first reference voltage VREF1 or the second reference voltage VREF2, in practice, the external threshold voltage compensation circuit 15[0] may further include a fourth switch SW4 and a fifth switch SW 5.

As shown in FIG. 2, the fourth switch SW4 is electrically connected between the non-inverting input of the operational amplifier 151 and the first reference voltage VREF1, and the fifth switch SW5 is electrically connected between the non-inverting input of the operational amplifier 151 and the second reference voltage VREF 2. In the present embodiment, the sub-pixel 22[0] may include, for example, a light emitting diode OLED, a driving transistor TD, a storage capacitor CST, and switching transistors T1 to T3. The driving transistor TD of the sub-pixel 22[0] has a first terminal receiving the supply voltage OVDD, a second terminal coupled to the anode of the light emitting diode OLED through a node P2, and a gate terminal coupled to the data line DL [0] through a node P3. The switch transistor T1 is connected in series between the node P3 and the data line DL [0], and has a gate terminal receiving the scan signal S [0], a first terminal electrically connected to the node P3, and a second terminal electrically connected to the data line DL [0], and is turned on or off according to the scan signal S [0 ].

The switch transistor T2 has a gate terminal receiving the sensing signal R [0], a first terminal electrically connected to the data line DL [0], and a second terminal electrically connected to the node P2, and is turned on or off according to the sensing signal R [0 ]. The switch transistor T3 is connected in series between the second terminal of the driving transistor TD and the node P2, and has a gate terminal receiving the emission control signal EM [0], a first terminal electrically connected to the second terminal of the driving transistor TD, and a second terminal electrically connected to the node P2, and is turned on or off according to the emission control signal EM [0 ]. The storage capacitor CST is electrically connected between the node P3 and the first terminal of the driving transistor TD.

In the present embodiment, the driving transistor TD and the switching transistors T1 to T3 may be all P-type low temperature polysilicon thin film transistors (P-type LTPS TFTs), for example, but the invention is not limited thereto. In summary, since the operation principle of the sub-pixel 22[0] is well known to those skilled in the art, the details thereof are not repeated herein. Next, referring to fig. 3A to 3D and fig. 4 together, fig. 3A to 3D are schematic diagrams illustrating operations of the external threshold voltage compensation circuit of fig. 2 when compensating for the sub-pixel, and fig. 4 is a schematic timing diagram illustrating operations of the external threshold voltage compensation circuit of fig. 2 when compensating for the sub-pixel. Parts in fig. 3A to 3D that are the same as those in fig. 2 are denoted by the same reference numerals, and details thereof are not described in detail herein.

First, as shown in FIG. 3A and FIG. 4, in the first period (1) when the second switch SW2[0] is turned on, the external threshold voltage compensation circuit 15[0] provides the first reference voltage VREF1 to the sub-pixel 22[0] through the data line DL [0 ]. Next, as shown in FIG. 3B and FIG. 4, during the second period (2) when the second switch SW2[0] is turned on, the external threshold voltage compensation circuit 15[0] detects the first sensing current I1 flowing through the driving transistor TD of the sub-pixel 22[0] via the data line DL [0] and generates the first integrated value Δ O1.

Obviously, based on the above teachings, those skilled in the art should understand that the external threshold voltage compensation circuit 15[0] is an integrator (integrator). Therefore, during the first period (1) when the second switch SW2[0] is turned on, i.e. the first reset period (first reset) of the integrator, the present embodiment controls the third switch SW3 and the fourth switch SW4 to be turned on, the fifth switch SW5 to be turned off, the switching transistor T3 of the sub-pixel 22[0] to be turned off by the emission control signal EM [0], and the switching transistor T1 and the switching transistor T2 of the sub-pixel 22[0] to be turned on by the scan signal S [0] and the sensing signal R [0] respectively, so that the nodes P1, P2 and P3 can commonly have the voltage of the first reference voltage VREF 1.

In contrast, during the second period (2) when the second switch SW2[0] is turned on, i.e., during the first reading (first read) of the integrator, the present embodiment controls to continuously turn on the fourth switch SW4 and turn off the third switch SW3, then controls to turn on the switch transistor T3 and the switch transistor T2 of the sub-pixel 22[0] respectively by the emission control signal EM [0] and the sensing signal R [0], and controls to turn off the switch transistor T1 of the sub-pixel 22[0] by the scanning signal S [0], so that the external threshold voltage compensation circuit 15[0] can generate the first integrated value Δ O1 in response to the first sensing current I1 flowing through the self-driving transistor TD.

Generally, since the driving voltage of the driving transistor TD, i.e. the voltage difference between the supply voltage OVDD and the node P3 is fixed at this time, the first sensing current I1 is also fixed and flows back to the inverting input terminal of the operational amplifier 151 by passing through the driving transistor TD, the switching transistor T3, the node P2, the switching transistor T2, the node P1 and the second switch SW2[0 ]. Then, by controlling the flowing time Δ tRD of the sensing current, the external threshold voltage compensation circuit 15[0], i.e., the first integrated value Δ O1 generated by the integrator, can be expressed as Δ O1 (-I1 × Δ tRD)/CST. It should be understood that Δ tRD is also referred to as integration time, but the invention is not limited to the specific implementation of the value thereof, and those skilled in the art should be able to design the value according to the actual requirement or application. Since the operation principle of the integrator is well known to those skilled in the art, the details thereof are not repeated herein.

Then, as shown in FIG. 3C and FIG. 4, in the third period (3) when the second switch SW2[0] is turned on, the external threshold voltage compensation circuit 15[0] provides the second reference voltage VREF2 to the sub-pixel 22[0] through the data line DL [0 ]. It should be noted that, as described above, since the compensation mechanism is activated during the black period immediately before the display panel 1 is turned on and does not display the normal image, in order to ensure that the light emitting diode OLED of the sub-pixel 22[0] is not lighted, the first reference voltage VREF1 and the second reference voltage VREF2 of the present embodiment are both less than or equal to the sum of the supply voltage OVSS of the light emitting diode OLED electrically connected to the sub-pixel 22[0] and the conduction voltage of the light emitting diode OLED, and the second reference voltage VREF2 is not equal to the first reference voltage VREF 1. Furthermore, as shown in FIG. 3D and FIG. 4, during the fourth period (4) when the second switch SW2[0] is turned on, the external threshold voltage compensation circuit 15[0] detects the second sensing current I2 flowing through the driving transistor TD of the sub-pixel 22[0] through the data line DL [0] and generates the second integrated value Δ O2.

That is, in the third period (3) when the second switch SW2[0] is turned on, i.e., the second reset period of the integrator, the present embodiment controls the third switch SW3 and the fifth switch SW5 to be turned on, the fourth switch SW4 to be turned off, the switching transistor T3 of the sub-pixel 22[0] to be turned off by the emission control signal EM [0], and the switching transistor T1 and the switching transistor T2 of the sub-pixel 22[0] to be turned on by the scan signal S [0] and the sense signal R [0] respectively, so that the nodes P1, P2 and P3 can commonly have the voltage of the second reference voltage VREF 2.

In contrast, during the fourth period (4) when the second switch SW2[0] is turned on, i.e., the second reading period of the integrator, the present embodiment controls to continuously turn on the fifth switch SW5 and turn off the third switch SW3, then controls to turn on the switch transistor T3 and the switch transistor T2 of the sub-pixel 22[0] respectively by the emission control signal EM [0] and the sensing signal R [0], and controls to turn off the switch transistor T1 of the sub-pixel 22[0] by the scanning signal S [0], so that the external threshold voltage compensation circuit 15[0] can generate the second integrated value Δ O2 in response to the second sensing current I2 flowing through the self-driving transistor TD.

Similarly, the external threshold voltage compensation circuit 15[0], i.e., the second integrated value Δ O2 generated by the integrator, can be expressed as Δ O2 (-I2 × Δ tRD)/CST. Then, in order to make the external threshold voltage compensation circuit 15[0] compensate for each of the sub-pixels 22[1] to 22[ n ] immediately after, after the first integrated value Δ O1 and the second integrated value Δ O2 related to the sub-pixel 22[0] are obtained, the switching transistor T3, the switching transistor T1 and the switching transistor T2 of the sub-pixel 22[0] are respectively controlled to be turned off by the emission control signal EM [0], the scan signal S [0] and the sensing signal R [0], as shown in FIG. 3E. That is, as shown in FIG. 4, for the next sub-pixel 22[1] in the same row as the sub-pixel 22[0], the external threshold voltage compensation circuit 15[0] is used to perform the above operation again, so as to obtain the first integrated value Δ O1 and the second integrated value Δ O2 related to the next sub-pixel 22[1], and so on, and the details of the compensation for each of the sub-pixels 22[1] -22 [ n performed by the external threshold voltage compensation circuit 15[0] are the same as those of the previous embodiments, so that the detailed description thereof is omitted.

The division result of the first integrated value Δ O1 and the second integrated value Δ O2 for each sub-pixel 22[0] to 22[ n ] is the division result of the first sensing current I1 and the second sensing current I2 for each sub-pixel 22[0] to 22[ n ]. Therefore, for each sub-pixel 22[0] -22 [ n ], the threshold voltage Vth can be expressed as the following equation (1). Wherein K represents a process factor, but the present invention is not limited to the specific implementation manner of the value thereof, and those skilled in the art should be able to design the value according to the actual requirement or application.

In short, as can be seen from the above, the external threshold voltage compensation circuit 15[0] of the present embodiment can obtain the threshold voltage value Vth for each of the sub-pixels 22[0] to 22[ n ]. Finally, to further illustrate the details of the implementation of the external threshold voltage compensation circuit 15[0], the present invention further provides an embodiment of the external threshold voltage compensation circuit 15[0 ]. Referring to fig. 5, fig. 5 is a schematic diagram of an external threshold voltage compensation circuit of fig. 2 according to another embodiment. In fig. 5, the same elements as those in fig. 2 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein.

As shown in FIG. 5, the external threshold voltage compensation circuit 15[0] may further include an analog-to-digital converter 155, a memory 157, and a data update unit 159. The foregoing elements may be implemented by hardware circuits, or implemented by hardware circuits and firmware or software, but the present invention is not limited thereto. In addition, the above components may be integrated or separately arranged, and the invention is not limited thereto.

In the present embodiment, the analog-to-digital converter 155 is electrically connected to the operational amplifier 151, and for the sub-pixel to be compensated, for example, the sub-pixel 22[0], the analog-to-digital converter 155 is used to convert the first integrated value Δ O1 and the second integrated value Δ O2 into a first digital compensation value and a second digital compensation value (not shown), respectively. The memory 157 is electrically connected to the analog-to-digital converter 155, and for the compensated sub-pixel 22[0], the memory 157 is used to store the first and second digital compensation values. The DATA update unit 159 is electrically connected between the memory 157 and the DATA driver 11, and for the compensated sub-pixel 22[0], the DATA update unit 159 is configured to receive the display DATA, generate a compensation signal corresponding to the sub-pixel 22[0] according to the first digital compensation value and the second digital compensation value, and provide the updated display DATA DATAc to the sub-pixel 22[0] according to the compensation signal and the display DATA during the display period of the sub-pixel 22[0 ]. It should be noted that the data update unit 159 may be provided independently as shown in fig. 5, or the data update unit 159 may be a logic circuit integrated in the data driver 11 or the timing controller (not shown), that is, the data update unit 159 may be implemented by a logic circuit such as an adder, but the invention is not limited thereto.

It should be understood that the "compensation signal for the sub-pixel 22[0] described herein can refer to the threshold voltage Vth of the sub-pixel 22[0], but the invention is not limited thereto, and the compensation signal for the sub-pixel 22[0] can be designed differently according to the user's requirement. In addition, the "display period of the sub-pixel 22[0] described herein can also refer to a period in which the first switch SW1[0] is turned on and the second switch SW2[0] is turned off. In other words, the external threshold voltage compensation circuit 15[0] according to the embodiment of the present invention enables the DATA driver 11 to adjust the display DATA according to the threshold voltage value Vth of the sub-pixel 22[0] during the period of writing DATA into the sub-pixel 22[0], i.e. the display period of the sub-pixel 22[0], so that the driving current IOLED output by the driving transistor TD of the sub-pixel 22[0] when the light emitting diode OLED emits light is not affected by the variation of the threshold voltage value Vth, and thus the aforesaid existing problems of uneven brightness or poor display quality are solved.

For example, if the example of the sub-pixel 22[0] is also used for illustration, please refer to fig. 6A to 6C and fig. 7 together, where fig. 6A to 6C are schematic diagrams of the operation of the sub-pixel in the display panel of fig. 1 during the display period, and fig. 7 is a schematic diagram of the timing sequence of the sub-pixel in the display panel of fig. 1 during the display period. Parts in fig. 6A to 6C that are the same as those in fig. 2 are denoted by the same reference numerals, and details thereof are not described in detail herein.

As shown in FIG. 6A and FIG. 7, in the first period (1') where the first switch SW1[0] is turned on, i.e. the reset period of the sub-pixel 22[0], the switch transistor T3 of the sub-pixel 22[0] is turned off by the emission control signal EM [0] and the switch transistor T1 and the switch transistor T2 of the sub-pixel 22[0] are turned on by the scan signal S [0] and the sense signal R [0] respectively, so that the nodes P1, P2 and P3 can have the voltage of the voltage VINT (not shown) in common. In contrast, as shown in FIG. 6B and FIG. 7, during the second period (2') when the first switch SW1[0] is turned on, i.e. the data writing period of the sub-pixel 22[0], the switch transistor T3 and the switch transistor T2 of the sub-pixel 22[0] are turned off by the light-emitting control signal EM [0] and the sensing signal R [0], respectively, and the switch transistor T1 of the sub-pixel 22[0] is turned on by the scanning signal S [0], so that the voltage VINT is still present at the node P2, but the nodes P1 and P3 receive the display data DATAc [0] of the sub-pixel 22[0 ].

Finally, as shown in fig. 6C and 7, in the third period (3') where the first switch SW1[0] is turned on, i.e. the light emitting period of the light emitting diode OLED of the sub-pixel 22[0], in the present embodiment, the switching transistor T3 of the sub-pixel 22[0] is controlled to be turned on by the light emitting control signal EM [0], and the switching transistor T1 and the switching transistor T2 of the sub-pixel 22[0] are respectively controlled to be turned off by the scanning signal S [0] and the sensing signal R [0], so that the driving transistor TD outputs the driving current IOLED to make the light emitting diode OLED emit light. Obviously, the driving current IOLED outputted by the driving transistor TD of the sub-pixel 22[0] when the light emitting diode OLED emits light can be simplified and expressed as the following equation (2). However, since the display principle of the sub-pixel 22[0] is well known to those skilled in the art, the details thereof will not be described herein.

On the other hand, if the example of the sub-pixel 22[0] is also used for illustration, please refer to fig. 8, and fig. 8 is a circuit diagram of another embodiment of the sub-pixel in the display panel of fig. 1. In fig. 8, the same elements as those in fig. 2 are denoted by the same reference numerals, and therefore, the details thereof will not be described herein. As shown in FIG. 8, the sub-pixel 22[0] may also include, for example, a light emitting diode OLED, a driving transistor TD, a storage capacitor CST ' and switching transistors T1 ' through T2 '. The driving transistor TD in fig. 8 may be turned on or off according to the emission control signal EM [0 ]. The switch transistor T1' has a gate terminal receiving the scan signal S [0], a first terminal electrically connected to the node P3, and a second terminal electrically connected to the data line DL [0], and is turned on or off according to the scan signal S [0 ].

The switch transistor T2' has a gate terminal receiving the sensing signal R [0], a first terminal electrically connected to DL [0], and a second terminal electrically connected to the node P2, and is turned on or off according to the sensing signal R [0 ]. The storage capacitor CST' is electrically connected between the node P3 and the first terminal of the driving transistor TD. In the present embodiment, the switch transistors T1 'and T2' may be both P-type ltps tfts, for example, but the invention is not limited thereto. Compared with the sub-pixel 22[0] of FIG. 2, the sub-pixel 22[0] of FIG. 8 reduces the layout area by reducing one TFT. Since the remaining operation details of the sub-pixel 22[0] of FIG. 8 are substantially similar to those described in the previous embodiments, further description is omitted here.

In summary, the display panel provided in the embodiments of the present invention may have a plurality of sub-pixels in a same row share a same external threshold voltage compensation circuit, and the external threshold voltage compensation circuit is disposed in the peripheral region of the display panel, but not disposed in the display region of the display panel, so that the embodiments of the present invention can simplify the number of elements required for each sub-pixel, thereby improving layout flexibility of the display region, and facilitating to achieve a higher required resolution, and even when the resolution of the display panel is higher, the compensation time used by the external threshold voltage compensation circuit of the present embodiment is not relatively reduced. In addition, the external threshold voltage compensation circuit of the present embodiment enables the data driver to adjust the display data according to the threshold voltage of the sub-pixel during the period of writing the data into the sub-pixel, so that the driving current output by the driving transistor of the sub-pixel when the driving transistor of the sub-pixel emits light is not affected by the variation of the threshold voltage, and the existing problems of uneven brightness or poor display quality are solved.

The above description is only an embodiment of the present invention, and is not intended to limit the claims of the present invention.

Claims

1. A display panel having a peripheral region and a display region, wherein a pixel string is disposed in the display region, the pixel string comprises a plurality of sub-pixels, each sub-pixel is electrically connected to a data line, a first switch is disposed between the data line and a data driver, an external threshold voltage compensation circuit is disposed in the peripheral region and electrically connected to the data line through a second switch for sequentially compensating one of the sub-pixels, wherein:

during a first period when the second switch is turned on, the external threshold voltage compensation circuit provides a first reference voltage to the sub-pixel through the data line;

during a second period when the second switch is turned on, the external threshold voltage compensation circuit detects a first sensing current flowing through a driving transistor of the sub-pixel through the data line and generates a first integral value;

during a third period when the second switch is turned on, the external threshold voltage compensation circuit provides a second reference voltage to the sub-pixel through the data line, the first reference voltage and the second reference voltage are both less than or equal to the sum of a first supply voltage of a light emitting diode electrically connected to the sub-pixel and a turn-on voltage of the light emitting diode, and the second reference voltage is not equal to the first reference voltage;

during a fourth period when the second switch is turned on, the external threshold voltage compensation circuit detects a second sensing current flowing through the driving transistor of the sub-pixel through the data line and generates a second integral value; and

during a display period, the first switch is turned on.

2. The display panel of claim 1, wherein the first switch and the second switch are not turned on at the same time.

3. The display panel of claim 1, wherein the external threshold voltage compensation circuit comprises:

an operational amplifier having an inverting input terminal electrically connected to the second switch, a non-inverting input terminal selectively receiving the first or the second reference voltage, and an output terminal outputting the first or the second integral value; and

a feedback unit electrically connected between the inverting input terminal and the output terminal of the operational amplifier, wherein the feedback unit is composed of a passive element and a third switch connected in parallel, the third switch is turned on during the first period and the third period when the second switch is turned on, and the third switch is turned off during the second period and the fourth period when the second switch is turned on.

4. The display panel of claim 3, wherein the external threshold voltage compensation circuit further comprises:

a fourth switch electrically connected between the non-inverting input terminal of the operational amplifier and the first reference voltage, and turning on the fourth switch during the first period and the second period when the second switch is turned on, and turning off the fourth switch during the third period and the fourth period when the second switch is turned on; and

a fifth switch electrically connected between the non-inverting input terminal of the operational amplifier and the second reference voltage, and turning off the fifth switch during the first period and the second period when the second switch is turned on, and turning on the fifth switch during the third period and the fourth period when the second switch is turned on.

5. The display panel of claim 4, wherein the driving transistor of the sub-pixel has a first terminal receiving a second supply voltage, a second terminal coupled to an anode of the light emitting diode via a first node, and a gate terminal coupled to the data line via a second node.

6. The display panel of claim 5, wherein the sub-pixel further comprises:

a first switch transistor, which is connected in series between the second node and the data line, has a gate terminal receiving a scan signal, a first terminal electrically connected to the second node, and a second terminal electrically connected to the data line, and is turned on or off according to the scan signal;

a second switch transistor having a gate terminal receiving a sensing signal, a first terminal electrically connected to the data line, and a second terminal electrically connected to the first node and turned on or off according to the sensing signal;

a third switching transistor, connected in series between the second terminal of the driving transistor and the first node, having a gate terminal receiving a light emission control signal, a first terminal electrically connected to the second terminal of the driving transistor, and a second terminal electrically connected to the first node, and turned on or off according to the light emission control signal; and

and the storage capacitor is electrically connected between the second node and the first end of the driving transistor.

7. The display panel of claim 6, wherein the light emission control signal turns off the third switching transistor of the sub-pixel, the scan signal and the sensing signal turn on the first switching transistor and the second switching transistor of the sub-pixel, respectively, during the first period and the third period in which the second switch is turned on, such that the first node and the second node can commonly have the voltage of the first reference voltage or the second reference voltage, and the light emission control signal and the sensing signal turn on the third switching transistor and the second switching transistor of the sub-pixel, respectively, during the second period and the fourth period in which the second switch is turned on, the scan signal turns off the first switching transistor of the sub-pixel, such that the external threshold voltage compensation circuit can generate the first integration value or the second integration value in response to the first sensing current or the second sensing current flowing through the driving transistor The value is obtained.

8. The display panel of claim 6, wherein the driving transistor of the sub-pixel is turned on or off according to the emission control signal, and the sub-pixel further comprises:

a second switch transistor having a gate terminal receiving a sensing signal, a first terminal electrically connected to the data line, and a second terminal electrically connected to the first node and turned on or off according to the sensing signal; and

9. The display panel of claim 3, wherein the external threshold voltage compensation circuit further comprises:

an analog-to-digital converter electrically connected to the operational amplifier for converting the first integral value and the second integral value into a first digital compensation value and a second digital compensation value, respectively;

a memory connected to the A/D converter for storing the first and second digital compensation values; and

and a data update unit electrically connected between the memory and the data driver, the data update unit being configured to receive a display data, generate a compensation signal corresponding to the sub-pixel according to the first digital compensation value and the second digital compensation value, and provide an updated display data to the sub-pixel according to the compensation signal and the display data during the display period.