CN109166524A - Display panel - Google Patents
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- CN109166524A CN109166524A CN201811154428.6A CN201811154428A CN109166524A CN 109166524 A CN109166524 A CN 109166524A CN 201811154428 A CN201811154428 A CN 201811154428A CN 109166524 A CN109166524 A CN 109166524A
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- data line
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- 230000002093 peripheral effect Effects 0.000 claims abstract description 13
- 230000005611 electricity Effects 0.000 claims description 6
- 238000001514 detection method Methods 0.000 claims description 5
- 238000010586 diagram Methods 0.000 description 14
- 238000000034 method Methods 0.000 description 4
- 239000010409 thin film Substances 0.000 description 4
- 239000013078 crystal Substances 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 229920001621 AMOLED Polymers 0.000 description 2
- 239000003990 capacitor Substances 0.000 description 2
- 230000006870 function Effects 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 230000006399 behavior Effects 0.000 description 1
- 238000007323 disproportionation reaction Methods 0.000 description 1
- 230000003760 hair shine Effects 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 229920005591 polysilicon Polymers 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The embodiment of the invention provides a display panel. The display panel is provided with a peripheral area and a display area. The pixel string including multiple sub-pixels is arranged in the display area, each sub-pixel is electrically connected to a data line, and a first switch is arranged between the data line and the data driver. The external critical voltage compensation circuit is arranged in the peripheral area and is electrically connected with the data line through the second switch so as to sequentially compensate one of the sub-pixels. In the first period and the third period when the second switch is turned on, the external critical voltage compensation circuit provides the first reference voltage or the second reference voltage to the sub-pixel through the data line. In a second period and a fourth period when the second switch is turned on, the external critical voltage compensation circuit detects a first sensing current or a second sensing current flowing through the driving transistor of the sub-pixel through the data line and generates a first integral value or a second integral value.
Description
Technical field
The present invention relates to a kind of display panels, and especially a kind of with external critical voltage compensating circuit (threshold
Voltage compensation circuit) display panel.
Background technique
In the operational process of display, thin film transistor (TFT) (Thin-Film Transistor, TFT) may be because of processing procedure
It influences or other operating conditions changes, and cause its critical voltage variation, cause to show that picture brightness is uneven, and related reduction
Display quality.In general, the prior art is understood through threshold voltage compensation come the critical voltage of compensation film transistor
Variation, and common threshold voltage compensation is the several thin film transistor (TFT)s and storage capacitance institute structure by being set in pixel
At, that is, claim it as internal threshold voltage compensation.
However, under the higher trend of resolution requirements now, pixel more need to set on display panel.Due to
Space on panel is limited, therefore often also must just be accepted or rejected to the inside threshold voltage compensation in pixel.It removes
Except this, the compensation time that the inside threshold voltage compensation in pixel can be used, but with data writing pixel when
Between it is related.Therefore, when resolution ratio is got higher, the compensation time that the inside threshold voltage compensation in pixel can be used is also
It is opposite to tail off.
Summary of the invention
In view of this, the purpose of the present invention is to provide a kind of external critical voltage compensating circuits being set to outside pixel.
In order to achieve the above object, the embodiment of the present invention provides a kind of display panel, the display panel has peripheral region (peripheral
) and viewing area (display area) area.Wherein, the pixel string comprising multiple sub-pixels is set to viewing area, and each son
Pixel is all electrically connected at data line, has first switch between data line and data driver.External critical voltage compensating circuit is then
It is set to peripheral region, and by being electrically connected to data line via second switch, to be used to sequentially in these sub-pixels
One compensates.In the first period of second switch conducting, external critical voltage compensating circuit provides first by data line
Reference voltage so far sub-pixel.In the second phase of second switch conducting, external critical voltage compensating circuit is examined by data line
First sensing electric current of driving transistor of the flow measurement through this sub-pixel, and generate first integral value.In the of second switch conducting
During three, external critical voltage compensating circuit provides the second reference voltage so far sub-pixel by data line, wherein the first reference
Voltage and the second reference voltage are smaller than to be equal to the first supply voltage and hair that are electrically connected the so far light emitting diode of sub-pixel
The summation of the conducting voltage (turn-on voltage) of optical diode, and the second reference voltage is not equal to the first reference voltage.In
Between the fourth phase of second switch conducting, external critical voltage compensating circuit is brilliant by the driving that data line detection flows through this sub-pixel
Second sensing electric current of body pipe, and generate second integral value.
Be further understood that feature and technology contents of the invention to be enabled, please refer to below in connection with it is of the invention specifically
Bright and attached drawing, but these explanations are intended merely to illustrate the present invention with attached drawing, rather than claim of the invention is made any
Limitation.
Detailed description of the invention
Fig. 1 is the function box schematic diagram of display panel provided by the embodiment of the present invention.
Fig. 2 is the circuit diagram of the external critical voltage compensating circuit in the display panel of Fig. 1.
Fig. 3 A~Fig. 3 E be the external critical voltage compensating circuit of Fig. 2 operation signal when being compensated for sub-pixel
Figure.
Fig. 4 be the external critical voltage compensating circuit of Fig. 2 time diagram when being compensated for sub-pixel.
Fig. 5 is the external critical voltage compensating circuit of Fig. 2 in the schematic diagram of another embodiment.
Fig. 6 A~Fig. 6 C is operation schematic diagram of the sub-pixel during display in the display panel of Fig. 1.
Fig. 7 is time diagram of the sub-pixel during display in the display panel of Fig. 1.
Fig. 8 is sub-pixel in the display panel of Fig. 1 in the circuit diagram of another embodiment.
Wherein, the reference numerals are as follows:
1: display panel
10: peripheral region
20: viewing area
11: data driver
12: scanner driver
13: sensing driver
14: sequence controller
15 [0]~15 [m]: external critical voltage compensating circuit
151: operational amplifier
153: feedback unit
155: analog-digital converter
157: memory
159: data updating unit
DATA, DATAc: display data
CINT: capacitor
SW1 [0]~SW1 [m]: first switch
SW2 [0]~SW1 [m]: second switch
SW3: third switch
SW4: the four switch
SW5: the five switch
VREF1: the first reference voltage
VREF2: the second reference voltage
I1: the first sensing electric current
I2: the second sensing electric current
Δ O1: first integral value
Δ O2: second integral value
21 [0]~21 [m]: pixel string
22 [0]~22 [n]: sub-pixel
DL [0]~DL [m]: data line
OLED: light emitting diode
TD: driving transistor
CST, CST ': storage capacitance
T1~T3, T1 '~T2 ': switching transistor
OVDD, OVSS: supply voltage
P1, P2, P3: node
EM [0]~EM [n]: LED control signal
S [0]~S [n]: scanning signal
R [0]~R [n]: sensing signal
Specific embodiment
It hereinafter, will be by Detailed description of the invention various embodiments of the present invention come the present invention is described in detail.However, of the invention
Concept may embody in many different forms, and should not be construed as limited by exemplary embodiments set forth herein.In addition,
Same reference numbers can be used to indicate similar element in the accompanying drawings.
Specifically, display panel provided by the embodiment of the present invention, also refers to any kind of display panel.It changes
Yan Zhi, the present invention are not intended to limit the specific implementation of display panel, and technician in the art should can be according to practical need
It asks or applies to carry out relevant design.But following explanation for convenience, the present embodiment will be with active-matrix organic light-emitting diodes
(AMOLED) display panel is managed to explain.For example, referring to Fig. 1, Fig. 1 is display surface provided by the embodiment of the present invention
The function box schematic diagram of plate.
As shown in Figure 1, display panel 1 has peripheral region 10 and viewing area 20.And according to the prior art it is found that peripheral region 10
Generally include data driver 11, scanner driver 12, sensing driver 13 and sequence controller 14.In addition, on viewing area 20
Multiple pixel strings are then provided with, such as pixel string 21 [0] arrives pixel string 21 [m], and each pixel string includes multiple sub-pixels, example
As sub-pixel 22 [0] arrives sub-pixel 22 [n].In the present embodiment, m and n is any positive integer that may respectively be greater than 1.It is total and
Yan Zhi, since the present invention is not intended to limit the resolution ratio of display panel 1, technician in the art should can be according to reality
Demand or application are come the design that carries out m and n.
However, following explanation, the present embodiment will be only first to inquire into single a pixel string, such as pixel string 21 for convenience
[0] example is illustrated.It should be understood that each sub-pixel 22 [0]~22 [n] of pixel string 21 [0] are all electrically connected
In data line DL [0], and receives via data line DL [0] and (do not show from the provided display data of data driver 11
Out).It and is in the present embodiment, between data line DL [0] and data driver 11 with first switch SW1 [0].In addition, one
External critical voltage compensating circuit 15 [0] is then set to peripheral region 10, and by being electrically connected to via second switch SW2 [0]
Data line DL [0], to be used to sequentially compensate one of these sub-pixel 22 [0]~22 [n].
Enlightenment according to the above, for technician in the art it would be appreciated that arriving, prior art design is to allow
Each sub-pixel 22 [0]~22 [n] all have individually internal threshold voltage compensation, but the display panel 1 of the present embodiment is set
Meter can be the multiple sub-pixels allowed in same a line (column), i.e. sub-pixel 22 [0]~22 [n] of pixel string 21 [0] are all total
With same external critical voltage compensating circuit 15 [0], and this external threshold voltage compensation 15 [0] is set to peripheral region 10
It is interior, that is, the cabling area between viewing area 20 and data driver 11, therefore, the present embodiment can significantly simplify each sub-pixel
Transistor unit number needed for 22 [0]~22 [n] to promote layout (layout) elasticity of viewing area 20 in turn, and has
Help realize the resolution ratio of higher demand.
On the other hand, it should be noted that the first switch SW1 [0] and second switch SW2 [0] of the present embodiment are different
When be connected.That is, the compensation time that the external critical voltage compensating circuit 15 [0] of the present embodiment uses, not with number
Time according to write-in sub-pixel 22 [0]~22 [n] is related.Therefore, even if when the resolution ratio of display panel 1 increases, such as increase
Add the data line and scan line of display panel 1, the compensation time that external critical voltage compensating circuit 15 [0] can distribute will not be because
Resolution ratio increases and the compensation time compared to the inside threshold voltage compensation being set in sub-pixel tails off.Citing comes
It says, the service condition of an embodiment disclosed in this invention, which can be just to be switched on every time in display panel 1, has had not yet been displayed normal picture
During blank screen in front, control cut-off first switch SW1 [0], and conducting second switch SW2 [0] is controlled, to allow external compensation
Circuit 15 [0] compensates come each sequentially for these sub-pixel 22 [0]~22 [n], but the present invention is not also to be limited
System.In addition, external compensation circuit 15 [0] can also be pre- advanced when display panel 1 is not integrated with display device or mobile device
Row critical voltage compensation making.
Then, for the purposes of convenient following explanation, the present embodiment will be only first to inquire into external critical voltage compensating circuit
15 [0] the example that compensates for sub-pixel 22 [0] be illustrated.Referring to Figure 2 together, Fig. 2 is the display surface of Fig. 1
The circuit diagram of external critical voltage compensating circuit in plate.Wherein, in Fig. 2 identical with Fig. 1 element in part with identical
Figure number mark, therefore no longer add that its details is described in detail in this.In the present embodiment, external critical voltage compensating circuit 15 [0]
Including operational amplifier 151 and feedback unit 153.The inverting input terminal (inverting input) of operational amplifier 151 is electrically connected
It is connected to second switch SW2 [0], the non-inverting input (non-inverting input) of operational amplifier 151 is then selectively
The first reference voltage VREF1 or the second reference voltage VREF2 is received, and the output end of operational amplifier 151 then exports the first product
Score value Δ O1 or second integral value Δ O2 (please referring to Fig. 3 B and Fig. 3 D).
Feedback unit 153 is electrically connected between the inverting input terminal and output end of operational amplifier 151, and it is via mutual
Passive element (passive component) and third switch SW3 in parallel is formed.In the present embodiment, the passive member
Part may be, for example, capacitor CINT, but the present invention is not limited system.For example, in other embodiments, described passive
Element also may be, for example, resistance RFB (not shown).To sum up, the present invention is not intended to limit the specific implementation side of the passive element
Formula, technician in the art should can carry out relevant design according to actual demand or application.However, in order to allow operation to put
The non-inverting input of big device 151 optionally receives the first reference voltage VREF1 or the second reference voltage VREF2, therefore,
In implementation, external critical voltage compensating circuit 15 [0] may also include the 4th switch SW4 and the 5th switch SW5.
As shown in Fig. 2, the 4th switch SW4 is electrically connected to the non-inverting input and first of operational amplifier 151 with reference to electricity
Between pressing VREF1, and the 5th switch SW5 is then electrically connected to the non-inverting input and the second reference voltage of operational amplifier 151
Between VREF2.In addition, in the present embodiment, sub-pixel 22 [0] can for example including light emitting diode OLED, driving transistor TD, deposit
Storage holds CST and switching transistor T1~T3.The driving transistor TD of sub-pixel 22 [0] is that supply voltage is received with first end
OVDD, second end are passed through by the anode and gate terminal for being coupled to light emitting diode OLED via node P2 via node P3
It is coupled to data line DL [0].Switching transistor T1 is then series between node P3 to data line DL [0], and it is with gate terminal
Reception scanning signal S [0], first end is electrically connected to node P3 and second end is electrically connected to data line DL [0], and according to
Scanning signal S [0] and on or off.
There is switching transistor T2 gate terminal reception sensing signal R [0], first end to be electrically connected to data line DL [0], and
Second end is electrically connected to node P2, and the on or off according to sensing signal R [0].Switching transistor T3 is then series at drive
The second end of dynamic transistor TD is between node P2, and it with gate terminal receives LED control signal EM [0], first end is electrically connected
Be connected to driving transistor TD second end and second end be electrically connected to node P2, and according to LED control signal EM [0] and
On or off.Storage capacitance CST is then electrically connected to node P3 and drives between the first end of transistor TD.
In the present embodiment, above-mentioned driving transistor TD and switching transistor T1~T3 can all be, for example, that p-type low temperature is more
Polycrystal silicon film transistor (P-type LTPS TFT), but the present invention is not limited system.To sum up, due to sub-pixel 22
[0] operation logic has been known to technician in the art, thus related above-mentioned detail content in this also just no longer
Add to repeat.It then, is the external critical voltage compensating circuit of Fig. 2 also referring to Fig. 3 A~Fig. 3 D and Fig. 4, Fig. 3 A~Fig. 3 D
Operation schematic diagram when being compensated for sub-pixel, and Fig. 4 is then the external critical voltage compensating circuit institute of Fig. 2 for son
Time diagram when pixel compensates.Wherein, in Fig. 3 A~Fig. 3 D identical with Fig. 2 element in part with identical figure number mark
Show, therefore no longer adds that its details is described in detail in this.
Firstly, in the first period (1) of second switch SW2 [0] conducting, external critical voltage is mended as shown in Fig. 3 A and Fig. 4
Repaying circuit 15 [0] is that the first reference voltage VREF1 is provided by data line DL [0] to sub-pixel 22 [0].Secondly, such as Fig. 3 B and
Shown in Fig. 4, in the second phase (2) of second switch SW2 [0] conducting, external critical voltage compensating circuit 15 [0] then passes through data
Line DL [0] detection flows through the first sensing electric current I1 of the driving transistor TD of sub-pixel 22 [0], and generates first integral value Δ
O1。
It is apparent that enlightenment according to the above, technician in the art is it would be appreciated that arrive, external critical electricity
Pressing compensation circuit 15 [0] is an integrator (integrator).Therefore, in the first period of second switch SW2 [0] conducting
(1), i.e., during the first resetting (first reset) of the integrator, the present embodiment then controls conducting third switch SW3 and the 4th
Switch SW4, and end the 5th switch SW5, opening for sub-pixel 22 [0] is then ended by LED control signal EM [0] control
Transistor T3 is closed, and brilliant by the switch that scanning signal S [0] and sensing signal R [0] control conducting sub-pixel 22 [0] respectively
Body pipe T1 and switching transistor T2, so that can be jointly with the voltage of the first reference voltage VREF1 on node P1, P2 and P3.
Relatively, in the second phase (2) of second switch SW2 [0] conducting, i.e. the first of the integrator reads (first
Readout during), the present embodiment then controls the 4th switch SW4 of constant conduction, and ends third switch SW3, then passes through hair
Optical control signal EM [0] and sensing signal R [0] controls the switching transistor T3 and switch crystal of conducting sub-pixel 22 [0] respectively
Pipe T2, and by the switching transistor T1 of scanning signal S [0] control cut-off sub-pixel 22 [0], so that external critical voltage is mended
Repay circuit 15 [0] can respond flow through from driving transistor TD first sensing electric current I1 and generate first integral value Δ O1.
Generally, because at this moment driving the driving voltage of transistor TD, that is, supply the electricity of voltage OVDD and node P3
Pressure difference is fixed, so the first sensing electric current I1 is also fixed, and it passes through via driving transistor TD, switch crystal
Pipe T3, node P2, switching transistor T2, node P1 and second switch SW2 [0] and the anti-phase input for flowing back to operational amplifier 151
End.Then, delivery time Δ tRD of the present embodiment by control sensing electric current, external critical voltage compensating circuit 15 [0], i.e.,
The first integral value Δ O1 that integrator can be generated can be expressed as Δ O1=(- I1* Δ tRD)/CST.It should be understood that institute
It states Δ tRD also just to refer to for the time of integration, but the present invention is not intended to limit the specific implementation of its numerical value, in the art skill
Art personnel should can carry out relevant design according to actual demand or application.Since the operation logic of integrator has been the art
Known to middle technical staff, therefore related above-mentioned detail content is also just no longer added to repeat in this.
Then, as shown in Fig. 3 C and Fig. 4, during the third of second switch SW2 [0] conducting (3), external critical voltage is mended
Repaying circuit 15 [0] is that the second reference voltage VREF2 is provided by data line DL [0] to sub-pixel 22 [0].It should be noted that
As described in previous contents, since compensation mechanism at this moment is black before the just booting of display panel 1 does not show normal pictures
Actuation during screen, therefore, in order to ensure not allowing the light emitting diode OLED of sub-pixel 22 [0] shinny, so the of the present embodiment
One reference voltage VREF1 and the second reference voltage VREF2 is smaller than to be equal to the light emitting diode for being electrically connected to sub-pixel 22 [0]
The summation of the conducting voltage of the supply voltage OVSS and light emitting diode OLED of OLED, and the second reference voltage VREF2 is not equal to
First reference voltage VREF1.It is external between the fourth phase of second switch SW2 [0] conducting (4) furthermore as shown in Fig. 3 D and Fig. 4
Threshold voltage compensation 15 [0] then flows through the second of the driving transistor TD of sub-pixel 22 [0] by data line DL [0] detection
Electric current I2 is sensed, and generates second integral value Δ O2.
That is, during the third of second switch SW2 [0] conducting (3), i.e., during the second resetting of the integrator,
The present embodiment then controls conducting third switch SW3 and the 5th switch SW5, and ends the 4th switch SW4, then passes through the control that shines
The switching transistor T3 of signal EM [0] control cut-off sub-pixel 22 [0] processed, and pass through scanning signal S [0] and sensing signal R
[0] the switching transistor T1 and switching transistor T2 for controlling conducting sub-pixel 22 [0] respectively, so that energy on node P1, P2 and P3
The enough common voltage with the second reference voltage VREF2.
Relatively, between the fourth phase of second switch SW2 [0] conducting (4), i.e., during the second of the integrator is read, this
Embodiment then controls five switch SW5 of constant conduction, and ends third switch SW3, then by LED control signal EM [0] and
Sensing signal R [0] controls the switching transistor T3 and switching transistor T2 of conducting sub-pixel 22 [0] respectively, and passes through scanning
The switching transistor T1 of signal S [0] control cut-off sub-pixel 22 [0], so that external critical voltage compensating circuit 15 [0] can return
It should flow through from the second sensing electric current I2 of driving transistor TD and generate second integral value Δ O2.
Similarly, the second integral value Δ O2 that external critical voltage compensating circuit 15 [0], i.e. integrator can be generated
It is expressed as Δ O2=(- I2* Δ tRD)/CST.Then, in order to make external critical voltage compensating circuit 15 [0] and then right again
Compensated in each of sub-pixel 22 [1]~22 [n], therefore, when obtained with sub-pixel 22 [0] it is related first product
After score value Δ O1 and second integral value Δ O2, the present embodiment then passes through LED control signal EM [0], scanning signal S [0] and sensing
Signal R [0] controls switching transistor T3, switching transistor T1 and the switching transistor T2 of cut-off sub-pixel 22 [0] respectively, such as schemes
Shown in 3E.That is, as shown in figure 4, for the next sub-pixel 22 [1] gone together with sub-pixel 22 [0], external critical
Voltage compensating circuit 15 [0] will then be used to re-start aforesaid operations again, be obtained whereby to the in relation to next sub-pixel 22 [1]
One integrated value Δ O1 and second integral value Δ O2, and so on, and related external critical voltage compensating circuit 15 [0] is further continued for
Elaboration when compensating for each of sub-pixel 22 [1]~22 [n] is also as described in previous embodiment, therefore in this
Just no longer add to repeat.
The division result of the first integral value Δ O1 and second integral value Δ O2 of each sub-pixel 22 [0]~22 [n], can
The division result for sensing the sensing of electric current I1 and second electric current I2 for the first of each sub-pixel 22 [0]~22 [n].Therefore, for
For each sub-pixel 22 [0]~22 [n], critical voltage value Vth can be expressed as shown in equation (1).Wherein, K
Processing procedure coefficient is represented, but the present invention is not intended to limit the specific implementation of its numerical value, technician in the art Ying Keyi
Relevant design is carried out according to actual demand or application.
To sum up, from the foregoing it can be that the external critical voltage compensating circuit 15 [0] of the present embodiment just can obtain
To the critical voltage value Vth in relation to each sub-pixel 22 [0]~22 [n].Finally, in order to further explain about external critical
Realization details when voltage compensating circuit 15 [0] compensates, the present invention further provides its external critical voltage compensating circuits
A kind of embodiment of 15 [0].Referring to Fig. 5, Fig. 5 is external critical voltage compensating circuit the showing in another embodiment of Fig. 2
It is intended to.Wherein, part element identical with Fig. 2 is indicated in Fig. 5 with identical figure number, therefore no longer adds that its details is described in detail in this.
As shown in figure 5, external critical voltage compensating circuit 15 [0] may also include analog-digital converter 155, memory
157 and data updating unit 159.Wherein, above-mentioned each element, which can be through hardware circuit, realizes, or passes through hardware electricity
Road firmware or software of arranging in pairs or groups realizes, but the present invention is not limited thereto system.In addition to this, above-mentioned each element can be integration or
It is to be provided separately, and the present invention is also not limited system.
In the present embodiment, analog-digital converter 155 is electrically connected to operational amplifier 151, and is directed to and compensates
Sub-pixel, such as sub-pixel 22 [0], analog-digital converter 155 be then used to respectively by its first integral value Δ O1 and
Second integral value Δ O2 is converted into the first digital compensation value and the second digital compensation value (not shown).Memory 157 is electrically connected
In analog-digital converter 155, and for the sub-pixel 22 [0] compensated, memory 157 be then used to store its
One and the second digital compensation value.Data updating unit 159 is electrically connected between memory 157 and data driver 11, and is directed to
For the sub-pixel 22 [0] compensated, data updating unit 159 is then used to receive display data DATA, and according to aforementioned
First digital compensation value and the second digital compensation value generate the thermal compensation signal for corresponding to sub-pixel 22 [0], and in sub-pixel 22
[0] during display, updated display data DATAc is provided to sub-pixel 22 according to thermal compensation signal and display data DATA
[0].It is independently arranged or data updating unit as shown in Figure 5 it is noted that the data updating unit 159 can be
159 can be the logic circuit being integrated in data driver 11 or sequence controller (not shown), that is, data updating unit
159 can be realized with logic circuits such as adders, but the present invention is also not limited system.
It should be understood that " thermal compensation signal of sub-pixel 22 [0] " as described herein can refer to is exactly sub-pixel 22 [0]
Critical voltage value Vth, but the present invention is also not limited system, and the thermal compensation signal of sub-pixel 22 [0] can also be according to user
Demand has different designs.In addition, as described herein can also refer to first switch SW1 " during the display of sub-pixel 22 [0] "
[0] conducting and second switch SW2 [0] end during.In other words, external critical voltage provided by the embodiment of the present invention is mended
Repaying circuit 15 [0] will be enabled through during data are written to sub-pixel 22 [0], i.e., during the display of sub-pixel 22 [0], so that
Data driver 11 can adjust display data DATA according to the critical voltage value Vth of sub-pixel 22 [0], to allow sub-pixel
The driving current IOLED that the driving transistor TD of 22 [0] is exported when making light emitting diode OLED shine by it without being faced
Voltage value Vth variation in boundary is influenced, and solves aforementioned brightness disproportionation or the undesirable existing issue of display quality whereby.
For example, if being equally with the example of sub-pixel 22 [0] come if explaining, A~Fig. 6 C referring to Figure 6 together
And Fig. 7, Fig. 6 A~Fig. 6 C are operation schematic diagram of the sub-pixel during display in the display panel of Fig. 1, and Fig. 7 is then Fig. 1
Display panel in time diagram of the sub-pixel during display.Wherein, part member identical with Fig. 2 in Fig. 6 A~Fig. 6 C
Part is indicated with identical figure number, therefore no longer adds that its details is described in detail in this.
As shown in Fig. 6 A and Fig. 7, in the first period (1 ') of first switch SW1 [0] conducting, the i.e. weight of sub-pixel 22 [0]
During setting, the present embodiment then passes through the switching transistor T3 of LED control signal EM [0] control cut-off sub-pixel 22 [0], and
Control the switching transistor T1 and switch crystal of conducting sub-pixel 22 [0] respectively by scanning signal S [0] and sensing signal R [0]
Pipe T2, so that can be jointly with the voltage of voltage VINT (not shown) on node P1, P2 and P3.Relatively, such as Fig. 6 B and Fig. 7
It is shown, in the second phase (2 ') of first switch SW1 [0] conducting, i.e. the data address period of sub-pixel 22 [0], the present embodiment
Then control respectively by LED control signal EM [0] and sensing signal R [0] the switching transistor T3 for ending sub-pixel 22 [0] and
Switching transistor T2, and by the switching transistor T1 of scanning signal S [0] control conducting sub-pixel 22 [0], so that node P2
On still with the voltage of voltage VINT, but node P1 and P3 then receive the display data DATAc [0] of sub-pixel 22 [0].
Finally, as shown in Fig. 6 C and Fig. 7, during the third of first switch SW1 [0] conducting (3 '), i.e. sub-pixel 22 [0]
The luminous period of light emitting diode OLED, the present embodiment then pass through LED control signal EM [0] control conducting sub-pixel 22 [0]
Switching transistor T3, and control the switch for ending sub-pixel 22 [0] respectively by scanning signal S [0] and sensing signal R [0]
Transistor T1 and switching transistor T2, so that driving transistor TD output driving current IOLED to allow light emitting diode OLED to send out
Light.It is apparent that the driving current that the driving transistor TD of sub-pixel 22 [0] is exported when making light emitting diode OLED shine
IOLED, which can simplify, to be expressed as shown in equation (2).However, since the displaying principle of sub-pixel 22 [0] has been this technology
Technical staff institute is existing in field, therefore related above-mentioned detail content is also just no longer added to repeat in this.
On the other hand, if being equally with the example of sub-pixel 22 [0] come if explaining, referring to Fig. 8, Fig. 8 is Fig. 1
Display panel in sub-pixel in the circuit diagram of another embodiment.Wherein, in Fig. 8 identical with Fig. 2 element in part with
Identical figure number mark, therefore no longer add that its details is described in detail in this.As shown in figure 8, sub-pixel 22 [0] can also be for example including luminous
Diode OLED, driving transistor TD, storage capacitance CST ' and switching transistor T1 '~T2 '.It should be noted that the drive of Fig. 8
Dynamic transistor TD can be according to LED control signal EM [0] and on or off.Switching transistor T1 ' then has grid termination
Receipts scanning signal S [0], first end is electrically connected to node P3 and second end is electrically connected to data line DL [0], and according to scanning
Signal S [0] and on or off.
There is switching transistor T2 ' gate terminal reception sensing signal R [0], first end to be electrically connected to DL [0] and second
End is electrically connected to node P2, and the on or off according to sensing signal R [0].Storage capacitance CST ' is then electrically connected to node
Between the first end of P3 and driving transistor TD.In the present embodiment, above-mentioned switching transistor T1 ' and T2 ' also can all be, for example, P
Type low-temperature polysilicon film transistor, but the present invention is not limited system.For sub-pixel 22 [0] compared to Fig. 2, Fig. 8
Sub-pixel 22 [0] by reduce a thin film transistor (TFT), to lower layout area.Due to remaining behaviour of the sub-pixel 22 [0] of Fig. 8
It is generally similar to operation described in previous embodiment to make details, therefore does not repeat separately herein.
In conclusion display panel provided by the embodiment of the present invention, it can be the multiple sub-pixels allowed in same a line all
Same external critical voltage compensating circuit is shared, and this external threshold voltage compensation is set to the peripheral region of display panel
It is interior, rather than be set in the viewing area of display panel, therefore, member needed for the embodiment of the present invention will simplify each sub-pixel
Part number to promote the layout elasticity of viewing area in turn, and helps to realize the resolution ratio of higher demand, and even if when aobvious
When showing that the resolution ratio of panel is got higher, the compensation time that the external critical voltage compensating circuit of the present embodiment can be used will not phase
To tailing off.In addition, the external critical voltage compensating circuit of the present embodiment will by during data are written to sub-pixel so that
Data driver can adjust display data according to the critical voltage of sub-pixel, so that the driving transistor of sub-pixel be allowed to make
The driving current exported when lumination of light emitting diode solves aforementioned bright whereby without being influenced by its critical voltage variation
Degree unevenness or the undesirable existing issue of display quality.
The above description is only an embodiment of the present invention, not to limit to claim of the invention.
Claims (9)
1. a kind of display panel has a peripheral region and a viewing area, wherein a pixel string is set to the viewing area, the pixel
String includes multiple sub-pixels, and each sub-pixel is all electrically connected at a data line, between the data line and a data driver
With a first switch, an external critical voltage compensating circuit is set to the peripheral region, and by via second switch electricity
It is connected to the data line, to be used to sequentially compensate one of described sub-pixel, in which:
In a first period of second switch conducting, which provides one first by the data line
Reference voltage is to the sub-pixel；
In a second phase of second switch conducting, which flows through this by data line detection
One first sensing electric current of one driving transistor of sub-pixel, and generate a first integral value；
During a third of second switch conducting, which provides one second by the data line
For reference voltage to the sub-pixel, first reference voltage and second reference voltage are smaller than to be equal to be electrically connected to the sub-pixel
A light emitting diode one first supply voltage and the light emitting diode a conducting voltage summation, and this second with reference to electricity
Pressure is not equal to first reference voltage；
Between a fourth phase of second switch conducting, which flows through this by data line detection
One second sensing electric current of the driving transistor of sub-pixel, and generate a second integral value；And
During a display, first switch conducting.
2. display panel as described in claim 1, wherein the first switch is not simultaneously turned on the second switch.
3. display panel as described in claim 1, wherein the external critical voltage compensating circuit includes:
One operational amplifier, with an inverting input terminal is electrically connected to the second switch, a non-inverting input selectively connects
Receive this first or second reference voltage and an output end export this first or the second integral value；And
One feedback unit is electrically connected between the inverting input terminal and the output end of the operational amplifier, wherein the feedback unit
It is the first period for being formed via a passive element parallel with one another and third switch, and being connected in the second switch
And third switch is connected during the third, ending between second phase and the fourth phase of second switch conducting should
Third switch.
4. display panel as claimed in claim 3, wherein the external critical voltage compensating circuit further include:
One the 4th switch, is electrically connected between the non-inverting input and first reference voltage of the operational amplifier, and in
The first period and the second phase of second switch conducting and the 4th switch is connected, in second switch conducting this
End the 4th switch during three and between the fourth phase；And
One the 5th switch, is electrically connected between the non-inverting input and second reference voltage of the operational amplifier, and in
The first period and the second phase of second switch conducting and end the 5th switch, in second switch conducting this
The 5th switch is connected during three and between the fourth phase.
5. display panel as claimed in claim 4, wherein the driving transistor of the sub-pixel is that there is a first end to receive
One second supply voltage, a second end are by being coupled to the anode and a grid of the light emitting diode via a first node
Extremely by being coupled to the data line via a second node.
6. display panel as claimed in claim 5, wherein the sub-pixel further include:
One first switch transistor is series at the second node between the data line, receives a scanning letter with a gate terminal
Number, a first end is electrically connected to the second node and a second end is electrically connected to the data line, and according to the scanning signal
And on or off；
There is one second switch transistor one sensing signal of gate terminal reception, a first end to be electrically connected to the data line, and
One second end is electrically connected to the first node, and the on or off according to the sensing signal；
One third switching transistor is series at the second end of the driving transistor between the first node, has a grid
One LED control signal of end reception, a first end is electrically connected to the second end of the driving transistor and a second end is electrically connected
It is connected to the first node, and the on or off according to the LED control signal；And
One storage capacitance is electrically connected between the second node and the first end of the driving transistor.
7. display panel as claimed in claim 6, wherein in the first period and the third phase of second switch conducting
Between, which is the third switching transistor to end the sub-pixel, the scanning signal and the sensing signal
Then be respectively turned on the first switch transistor and the second switch transistor of the sub-pixel so that the first node and this second
Can then have first reference voltage or the voltage of second reference voltage on node jointly, and in second switch conducting
Between the second phase and the fourth phase, the LED control signal and the sensing signal are to be respectively turned on the third of the sub-pixel to open
Close transistor and the second switch transistor, which then to end the first switch transistor of the sub-pixel, makes
The first sensing electric current or second sense flowed through from the driving transistor can be responded by obtaining the external critical voltage compensating circuit
It surveys electric current and generates the first integral value or the second integral value.
8. display panel as claimed in claim 5, wherein the driving transistor of the sub-pixel is believed according to the light emitting control
Number and on or off, and the sub-pixel further include:
One first switch transistor is series at the second node between the data line, receives a scanning letter with a gate terminal
Number, a first end is electrically connected to the second node and a second end is electrically connected to the data line, and according to the scanning signal
And on or off；
There is one second switch transistor one sensing signal of gate terminal reception, a first end to be electrically connected to the data line, and
One second end is electrically connected to the first node, and the on or off according to the sensing signal；And
One storage capacitance is electrically connected between the second node and the first end of the driving transistor.
9. display panel as claimed in claim 3, wherein the external critical voltage compensating circuit further include:
One analog-digital converter is electrically connected to the operational amplifier, the analog-digital converter be then used to respectively by this first
Integrated value and the second integral value are converted into one first digital compensation value and one second digital compensation value；
One memory is electrically connected to the analog-digital converter, which is then used to store the first digital compensation value and should
Second digital compensation value；And
One data updating unit is electrically connected between the memory and the data driver, which is then used to receive
One display data, and according to the first digital compensation value and the second digital compensation value, generate and correspond to the one of the sub-pixel
Thermal compensation signal, and during the display, a updated display data are provided extremely according to the thermal compensation signal and the display data
The sub-pixel.
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| TW107124248 | 2018-07-13 | ||
| TW107124248A TWI673695B (en) | 2018-07-13 | 2018-07-13 | Display panel |
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| CN109166524A true CN109166524A (en) | 2019-01-08 |
| CN109166524B CN109166524B (en) | 2020-03-20 |
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| WO2023108796A1 (en) * | 2021-12-16 | 2023-06-22 | Tcl华星光电技术有限公司 | Pixel driving circuit and display panel |
| WO2023240465A1 (en) * | 2022-06-14 | 2023-12-21 | 京东方科技集团股份有限公司 | Display panel and display device |
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Also Published As
| Publication number | Publication date |
|---|---|
| TWI673695B (en) | 2019-10-01 |
| CN109166524B (en) | 2020-03-20 |
| TW202006691A (en) | 2020-02-01 |
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