CN109150172B

CN109150172B - VCO starting circuit

Info

Publication number: CN109150172B
Application number: CN201810983003.XA
Authority: CN
Inventors: 孙嘉斌; 贾一平; 刘雨婷; 胡凯; 张超; 陈倩; 孙晓哲
Original assignee: Jinan Guokexin Microelectronics Technology Co ltd
Current assignee: Jinan Guokexin Microelectronics Technology Co ltd
Priority date: 2018-08-27
Filing date: 2018-08-27
Publication date: 2023-12-22
Anticipated expiration: 2038-08-27
Also published as: CN109150172A

Abstract

The invention discloses a VCO starting circuit, which comprises a VCO starting indicating circuit, a VCO bias generating circuit and a ring-shaped VCO circuit, wherein the output end EN of the VCO starting indicating circuit is connected with the input end EN of the VCO bias generating circuit, the output end INIT_ENB of the VCO starting indicating circuit is connected with the input end INIT_ENB of the VCO bias generating circuit, the output end ENB of the VCO starting indicating circuit is connected with the input end ENB of the VCO bias generating circuit, the input end V1 of the VCO starting indicating circuit is connected with the input end V1 of the VCO bias generating circuit, the output end NBS of the VCO bias generating circuit is connected with the input end NBS of the ring-shaped VCO circuit, the output end PBS of the VCO bias generating circuit is connected with the input end PBS of the ring-shaped VCO circuit, and the input end PBS of the starting indicating circuit. The invention can quickly pre-prepare the bias voltage of the VCO.

Description

VCO starting circuit

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to a VCO starting circuit.

Background

With the development of System on Chip (SoC) technology, a phase locked loop (Phase Locked Loop, PLL) that provides a System clock has become an important component of the SoC, and a CMOS Voltage controlled oscillator (Voltage-controlled Oscillator, VCO) is a mainstream design form of an internal oscillator of the PLL due to the advantage of frequency controllability. VCO is an electronic circuit that adjusts the output oscillation frequency by inputting a control voltage, and is characterized by being able to be used as a frequency-adjustable signal source, and is widely used in modern integrated circuit designs.

As shown in fig. 1, the conventional differential VCO bias generating circuit mainly comprises a differential amplifier 101 and a V1 buffer unit 102, wherein the V1 buffer unit 102 is formed by half circuits of a VCO differential delay unit. Assuming that the V1 voltage is slowly increased from 0, inputting from the positive input terminal of the differential amplifier 101, and outputting a control signal NBS, wherein the NBS is fed back to the reverse input terminal of the amplifier 101 to form negative feedback, so that the NBS follows the V1 voltage; at the same time, the NBS input V1 buffer unit 102 generates another control signal PBS, and when the change of V1 causes the NBS, PBS to reach a specific value, the VCO amplifies the disturbance and noise in the loop to meet the small signal 'barkhausen' oscillation condition, and the VCO starts to oscillate. However, the continuous development of the technology requires that the VCO has a fast start-up speed, and also needs to ensure that the VCO is not affected by the process, voltage and temperature, so as to enhance the stability and reliability of the VCO.

Disclosure of Invention

The invention aims to provide a VCO starting circuit for enabling a voltage-controlled oscillator to rapidly start.

The technical solution for realizing the purpose of the invention is as follows: a VCO starting circuit comprises a VCO starting indicating circuit, a VCO bias generating circuit and a ring-shaped VCO circuit, wherein an output end EN of the VCO starting indicating circuit is connected with an input end EN of the VCO bias generating circuit, an output end INIT_ENB of the VCO starting indicating circuit is connected with an input end INIT_ENB of the VCO bias generating circuit, an output end ENB of the VCO starting indicating circuit is connected with an input end ENB of the VCO bias generating circuit, an input end V1 of the VCO starting indicating circuit is connected with an input end V1 of the VCO bias generating circuit, an output end NBS of the VCO bias generating circuit is connected with an input end NBS of the ring-shaped VCO circuit, an output end PBS of the VCO bias generating circuit is connected with an input end PBS of the ring-shaped VCO circuit, and an input end PBS of the starting indicating circuit.

Compared with the prior art, the invention has the remarkable advantages that: the bias voltage of the VCO can be prefabricated quickly; 2) Under the condition that the VCO bias voltage meets the oscillation condition, the invention adds larger-amplitude disturbance to the VCO loop to promote the VCO to start oscillation; 3) The invention gives a state indication signal when the VCO starts to vibrate; 4) The invention gives a status indication signal when the VCO frequency approaches the limit.

Drawings

Fig. 1 is a circuit diagram of a conventional differential VCO bias generation circuit.

Fig. 2 is a circuit diagram of a VCO start-up indication circuit of the present invention.

Fig. 3 is a circuit diagram of a VCO bias generation circuit of the present invention.

Fig. 4 is a block diagram of the VCO start-up circuit of the present invention.

Figure 5 is a block diagram of the structure of the ring VCO circuit of the present invention.

Detailed Description

The principles and aspects of the present invention are further described below with reference to the drawings and the detailed description.

The invention discloses a VCO starting circuit, which comprises a VCO starting indicating circuit 201, a VCO bias generating circuit 301 and a ring-shaped VCO circuit 402, wherein the output end EN of the VCO starting indicating circuit 201 is connected with the input end EN of the VCO bias generating circuit 301, the output end INIT_ENB of the VCO starting indicating circuit 201 is connected with the input end INIT_ENB of the VCO bias generating circuit 301, the output end ENB of the VCO starting indicating circuit 201 is connected with the input end ENB of the VCO bias generating circuit 301, the input end V1 of the VCO starting indicating circuit 201 is connected with the input end V1 of the VCO bias generating circuit 301, the output end NBS of the VCO bias generating circuit 301 is connected with the input end NBS of the ring-shaped VCO circuit 402, the output end PBS of the VCO bias generating circuit 301 is connected with the input end PBS of the ring-shaped VCO circuit 402, and the input end PBS of the VCO starting indicating circuit 201.

As shown in fig. 2, the VCO start-up indication circuit 201 includes a first inverter 101, a second inverter 102, a third inverter 106, a buffer 104, a first nand gate 103, a second nand gate 107, a nor gate 105, a comparator 108, a first transistor MP1, a second transistor MP2, a third transistor MN1, a fourth transistor MN2, a fifth transistor MN3, and a sixth transistor MN4. The input end EN_I of the VCO start-up indication circuit 201 is connected with the input end of the inverter 101, the output end of the VCO start-up indication circuit 201 is used as the output end ENB of the VCO start-up indication circuit 201, and is connected with the input end ENB of the VCO bias generation circuit 301, the input end of the inverter 102 and the gates of N tubes MN3 and MN4 below the circuit; the output of inverter 102 is VCO indicative of the output EN of start-up circuit 201 and is coupled to one input of nand gate 103. The output EN of VCO indication start-up circuit 201 is connected to the input EN of VCO bias generation circuit 301. The input terminal PBS of the VCO start-up indication circuit 201 is connected to the gates of MP1 and MP2, and the sources of MP1 and MP2 are connected to high potential. The VCO indicates that input V1 of start-up circuit 201 is connected to the gates of MN1, MN2, one input of nand gate 107 and one input of comparator 108. MN1, MN2 source to ground, MN1 drain to MP1 drain, and another input net01 of comparator 108. The output net02 of the comparator 108 is connected to the other input of the nand gate 107 and to the drain of the MN3, the source of the MN3 being grounded. The MN2 drain is connected to the MP2, MN4 drains, and the input net04 of the inverter 106. The output end net03 of the NAND gate 107 in the VCO start-up indication circuit 201 is connected to one input end of the NOR gate 105, the other input end of the NOR gate 105 is the output end net05 of the inverter 106, and the output of the NOR gate 105 is the output end VCO_MAX of the VCO start-up indication circuit 201; meanwhile, net05 is connected to the input of buffer 104 and the other input of nand gate 103, and the output of buffer 104 is vco_start, which is the output of VCO indication START circuit 201; the output of NAND gate 103 is the output INIT_ENB of VCO indication enabled circuit 201, which is coupled to the input INIT_ENB of VCO bias generating circuit 301.

In one embodiment, in the VCO start-up indication circuit 201, the first transistor MP1 and the second transistor MP2 are PMOSE transistors, and the third transistor MN1, the fourth transistor MN2, the fifth transistor MN3, and the sixth transistor MN4 are NMOS transistors.

In one embodiment, in the VCO start-up indication circuit 201, the first inverter 101, the second inverter 102, and the third inverter 106 are TTL not gates.

As shown in fig. 3, the VCO bias generating circuit 301 includes a seventh transistor MP3, an eighth transistor MP4, a ninth transistor MP5, a tenth transistor MP6, an eleventh transistor MP7, a twelfth transistor MP8, a thirteenth transistor MN5, a fourteenth transistor MN6, a fifteenth transistor MN7, a sixteenth transistor MN8, a seventeenth transistor MN9, and an eighteenth transistor MN10. The input end ENB of the VCO bias generating circuit 301 is connected to the gate of MN7, the source end of MN7 is grounded, the drain ends of MN6 and MN10 are connected to the gates of MN6, MP4 and MP5, and the drain end net02 of MN 5; MN6, eighteenth transistor MN10 source ground. MP4, MP5 source terminal high potential, MP5 grid terminal VCO bias generation circuit 301 input terminal INIT_ENB; in the VCO bias generating circuit 301, MP6/MP7/MN8/MN9/MN10/MP3/MN5 form a differential amplifying circuit, the MN10 drain net01 is connected to the source ends of MN8 and MN9, and the MN8 drain is connected to the gates net03 of MP6 and MP7 and the drain of MP 6; the gate of MN9 is connected with the input end V1 of the VCO bias generating circuit 301, and the source ends of MP6 and MP7 are connected with high potential; the drain terminal of MP7 is connected with the gates of MP3 and MP4 and the drain terminals of MN9 and MP8, and is used as the output terminal PBS of the VCO bias generating circuit 301, and the PBS is connected back to the input terminal PBS of the VCO indication starting circuit 201; in the VCO bias generating circuit 301, the MP3 source terminal is connected to the high potential, the drain terminal is connected to the drain terminal and gate of MN5, and the gate of MN8, and is used as the output terminal NBS of the VCO bias generating circuit 301; the source of MN5 is grounded.

In one embodiment, in the VCO bias generating circuit 301, the seventh transistor MP3, the eighth transistor MP4, the ninth transistor MP5, the tenth transistor MP6, the eleventh transistor MP7, and the twelfth transistor MP8 are PMOS transistors, and the thirteenth transistor MN5, the fourteenth transistor MN6, the fifteenth transistor MN7, the sixteenth transistor MN8, the seventeenth transistor MN9, and the eighteenth transistor MN10 are NMOS transistors.

As shown in fig. 4, the output terminals NBS and PBS of the VCO start-up circuit 401 are input into the ring VCO circuit 402, and control the oscillation frequency of the ring VCO circuit 402 as a bias voltage. The ring VCO circuit 402 includes a plurality of delay cells, with the outputs OL, OR of the previous delay cell connected to the inputs IL, IR of the next delay cell, respectively, and the outputs OL, OR of the last delay cell connected to the inputs IL, IR of the first delay cell, respectively.

The operating principle of the VCO start-up circuit is as follows:

when en_i=0, the circuit is in a reset state. In fig. 2, via inverter 101, enb=1, MN3, MN4 input signal is high, the pipe is on, net02, net04 level is pulled low to 0, output net03 of nand gate 107 is set to 1, and output vco_max of nor gate 105 is set to 0. The net04 signal is output 1 via inverter 106 and vco_start is output 1 via buffer 104. ENB via inverter 102 outputs en=0, setting the output BIAS of nand gate 103 to 1.

In fig. 3, since en=0, mp6 input voltage is 0, the tube is open, pbs=1. Init_enb=1, mp3 input voltage 1, pipe cut-off; enb=1, mn3 input voltage of 1, tube on, net02 signal pulled down to 0, mn6 input voltage of 0, tube off; at this time, no matter how the V1 value is changed, NBS is not changed.

When en_i=1, in fig. 2, enb=0, MN3, MN4 input signal is 0 via inverter 101, and the pipe is cut off. Pbs=1, MP1, MP2 input voltage 1, tube cut-off. ENB via inverter 102, en=1.

At this time, the circuit is in an initial state, v1=0, that is, the gate input signals of MN1, MN2 are 0, and the pipe is turned off; the output net03 of the nand gate 107 is set to 1 and the output vco_max of the nor gate 105 is set to 0.

When V1 rises to the threshold of MN1, MN2, MN1 and MN2 tubes are on, MP1 and MP2 remain off, net01 signal is pulled low to 0, and net04 remains 0. The comparator 108 output net02 is 1, the output net03 of the nand gate 107 remains 0, and the vco_max output is 1. The net04 signal goes through the inverter 106, the net05 signal goes to 1, and the output INIT_ENB of the NAND gate 103 goes to 0; the net05 signal passes through the buffer 104 and vco_start remains at 1.

In fig. 3, when en=1, the MP6 input signal is 1, and the pipe is cut off; enb=0, the mn3 input voltage is 0, the tube is turned off, and both the amplifying circuit and the bias circuit are enabled. At this point, init_enb=0, the mp3 gate input signal is 0, the pipe is turned on, and the net02 point voltage is pulled up. The increase of net02 voltage increases the current of MN6, improves the bandwidth of the amplifying circuit, and accelerates each transistor of the whole amplifying circuit to enter a saturation region. When V1 increases, the PBS signal is pulled down with acceleration, the MP1 tube is gradually opened, and the NBS signal is gradually pulled up.

In fig. 2, the width-to-length ratio of MP2 is much larger than MN2, when PBS falls to a certain value, the net04 point level is flipped from 0 to 1, which is related to MP2 and MN2 parameter design, the net05 signal is 0 via inverter 106, en=1, and the output init_enb is changed from 0 to 1 via nand gate 103.

At this time, in fig. 3, since init_enb is changed from 0 to 1, the MP3 transistor is turned off instantaneously, so that the bias current of the amplifier is reduced instantaneously, and at the moment of MP3 turn-off, it is V1 that is raised to the vicinity of the threshold value of the transistor, and both the transistors of the amplifier and VCO have entered the saturation region, and the NBS and PBS voltages output from the amplifier also change instantaneously due to the change of the bias current. The instantaneous change of NBS and PBS introduces a larger-amplitude disturbance into the oscillation loop of the VCO, so that the VCO meeting the 'Barkhausen' oscillation condition can amplify the disturbance to form an oscillation signal, and the whole VCO can start to oscillate smoothly. At this time, net05 in fig. 2 outputs a vco_start signal from 1 to 0 via the buffer 104, and can be used as an indication signal for starting oscillation of the VCO.

In fig. 2, since the MP1 tube size is much larger than the MN1 size, the PBS will continuously drop during the rise of V1, turning MP1 on at some point, the net01 signal being pulled high to a higher level is related to MP1 and MN1 parameters. The output net02 of the comparator 108 is inverted from 1 to 0 after power-up, the output net03 of the nand gate 107 is kept at 1, and the vco_max is kept at 0 via the nor gate 105.

When the V1 level is high enough, V1 will exceed net01 point voltage, comparator 108 output signal net02 will flip, comparator 108 output will change from 0 to 1, and nand gate 107 output net03 signal will change from 1 to 0. Since the net04 signal is 1, the net05 signal is 0 via the NAND gate 106, and the output VCO_MAX is changed from 0 to 1 via the NOR gate 105, indicating that the VCO bias voltage has reached a limit and that the output clock is approaching the highest output frequency.

According to the invention, the bias voltage of the VCO can be prefabricated rapidly, and under the condition that the bias voltage of the VCO meets the oscillation condition, a larger-amplitude disturbance is added to the VCO loop to promote the VCO to start oscillation.

Claims

1. The VCO starting circuit is characterized by comprising a VCO starting indicating circuit (201), a VCO bias generating circuit (301) and a ring-shaped VCO circuit (402), wherein an output end EN of the VCO starting indicating circuit (201) is connected with an input end EN of the VCO bias generating circuit (301), an output end INIT_ENB of the VCO starting indicating circuit (201) is connected with an input end INIT_ENB of the VCO bias generating circuit (301), an output end ENB of the VCO starting indicating circuit (201) is connected with an input end ENB of the VCO bias generating circuit (301), an input end V1 of the VCO starting indicating circuit (201) is connected with an input end V1 of the VCO bias generating circuit (301), an output end NBS of the VCO bias generating circuit (301) is connected with an input end PBS of the ring-shaped VCO circuit (402), and an output end PBS of the VCO bias generating circuit (301) is connected with an input end PBS of the ring-shaped VCO circuit (402);

the VCO start indicating circuit (201) comprises a first inverter (101), a second inverter (102), a third inverter (106), a buffer (104), a first NAND gate (103), a second NAND gate (107), a NOR gate (105), a comparator (108), a first transistor (MP 1), a second transistor (MP 2), a third transistor (MN 1), a fourth transistor (MN 2), a fifth transistor (MN 3) and a sixth transistor (MN 4), wherein an input end EN_I of the VCO start indicating circuit (201) is connected with an input end of the first inverter (101), an output end of the VCO start indicating circuit (201) is used as an output end ENB of the VCO start indicating circuit, and the output end ENB of the VCO start indicating circuit is connected with an input end ENB of the VCO bias generating circuit (301), and the input end of the second inverter (102) and gates of the fifth transistor (MN 3) and the sixth transistor (MN 4); the output of the second inverter (102) is the output end EN of the VCO starting indicating circuit (201) and is simultaneously connected to one input end of the first NAND gate (103), and the output end EN of the VCO starting indicating circuit (201) is connected to the input end EN of the VCO bias generating circuit (301); the input end PBS of the VCO start indication circuit (201) is connected to the gates of the first transistor (MP 1) and the second transistor (MP 2), and the sources of the first transistor (MP 1) and the second transistor (MP 2) are connected with high potential; an input end V1 of the VCO start indicating circuit (201) is connected with the gates of the third transistor (MN 1) and the fourth transistor (MN 2), one input end of the second NAND gate (107) and one input end of the comparator (108); the source end of the third transistor (MN 1) and the source end of the fourth transistor (MN 2) are grounded, the drain end of the third transistor (MN 1) is connected with the drain end of the first transistor (MP 1), the other input end of the comparator (108), the output end of the comparator (108) is connected with the other input end of the second NAND gate (107) and the drain end of the fifth transistor (MN 3), and the source end of the fifth transistor (MN 3) is grounded; the drain end of the fourth transistor (MN 2) is connected with the drain ends of the second transistor (MP 2) and the sixth transistor (MN 4), and the input end of the third inverter (106); the output end of the second NAND gate (107) in the VCO start indicating circuit (201) is connected to one input end of the NOR gate (105), the other input end of the NOR gate (105) is the output end of the third inverter (106), and the output end of the NOR gate (105) is the output end VCO_MAX of the VCO start indicating circuit (201); meanwhile, net05 is connected to the input end of the buffer (104) and the other input end of the first NAND gate (103), and the output end of the buffer (104) is the output end VCO_START of the VCO START indication circuit (201); the output end of the first NAND gate (103) is the output end INIT_ENB of the VCO starting indicating circuit (201) and is connected to the input end INIT_ENB of the VCO bias generating circuit (301);

the VCO bias generating circuit (301) includes a seventh transistor (MP 3), an eighth transistor (MP 4), a ninth transistor (MP 5), a tenth transistor (MP 6), an eleventh transistor (MP 7), a twelfth transistor (MP 8), a thirteenth transistor (MN 5), a fourteenth transistor (MN 6), a fifteenth transistor (MN 7), a sixteenth transistor (MN 8), a seventeenth transistor (MN 9), and an eighteenth transistor (MN 10), an input end ENB of the VCO bias generating circuit (301) is connected to a gate of the fifteenth transistor (MN 7), a source of the fifteenth transistor (MN 7) is grounded, a drain is connected to gates of the fourteenth transistor (MN 6), the eighteenth transistor (MN 10), and drain ends net02 of the fourteenth transistor (MN 6), the eighth transistor (MP 4), and the ninth transistor (MP 5); a fourteenth transistor (MN 6), an eighteenth transistor (MN 10) having a source terminal connected to ground; the source end of the eighth transistor (MP 4) and the source end of the ninth transistor (MP 5) are connected with a high potential, and the grid end of the ninth transistor (MP 5) is connected with the input end INIT_ENB of the VCO bias generating circuit (301); in the VCO bias generating circuit (301), a tenth transistor (MP 6), an eleventh transistor (MP 7), a sixteenth transistor (MN 8), a seventeenth transistor (MN 9), an eighteenth transistor (MN 10), a seventh transistor (MP 3) and a thirteenth transistor (MN 5) form a differential amplifying circuit, a drain terminal net01 of the eighteenth transistor (MN 10) is connected with a source terminal of the sixteenth transistor (MN 8) and a seventeenth transistor (MN 9), and a drain terminal of the sixteenth transistor (MN 8) is connected with a drain terminal of the tenth transistor (MP 6), a gate terminal net03 of the eleventh transistor (MP 7) and a drain terminal of the tenth transistor (MP 6); a seventeenth transistor (MN 9) is connected with an input end V1 of the VCO bias generating circuit (301), and sources of a tenth transistor (MP 6) and an eleventh transistor (MP 7) are connected with a high potential; the drain terminal of the eleventh transistor (MP 7) is connected with the gates of the seventh transistor (MP 3) and the eighth transistor (MP 4) and the drain terminals of the seventeenth transistor (MN 9) and the twelfth transistor (MP 8), and is used as an output terminal PBS of the VCO bias generating circuit (301), and the PBS is connected back to the input terminal PBS of the VCO start indicating circuit (201); in the VCO bias generating circuit (301), a source terminal of a seventh transistor (MP 3) is connected with a high potential, a drain terminal of a thirteenth transistor (MN 5) is connected with a gate terminal and a gate terminal, and a gate terminal of a sixteenth transistor (MN 8) is connected as an output terminal NBS of the VCO bias generating circuit (301); the thirteenth transistor (MN 5) has its source grounded.

2. VCO start-up circuit according to claim 1, characterized in that the ring VCO circuit (402) comprises a number of delay cells, the output OL, OR of a previous delay cell being connected to the input IL, IR of a next delay cell, respectively, and the output OL, OR of a last delay cell being connected to the input IL, IR of a first delay cell, respectively.

3. The VCO start-up circuit according to claim 1, characterized in that in the VCO start-up indication circuit (201), the first transistor (MP 1), the second transistor (MP 2) are PMOS transistors, and the third transistor (MN 1), the fourth transistor (MN 2), the fifth transistor (MN 3), the sixth transistor (MN 4) are NMOS transistors.

4. The VCO start-up circuit according to claim 1, wherein in the VCO bias generation circuit (301), a seventh transistor (MP 3), an eighth transistor (MP 4), a ninth transistor (MP 5), a tenth transistor (MP 6), an eleventh transistor (MP 7), a twelfth transistor (MP 8) are PMOSE transistors, a thirteenth transistor (MN 5), a fourteenth transistor (MN 6), a fifteenth transistor (MN 7), a sixteenth transistor (MN 8), a seventeenth transistor (MN 9), and an eighteenth transistor (MN 10) are NMOSE transistors.

5. The VCO start-up circuit according to claim 1, characterized in that in the VCO start-up indication circuit (201), the first inverter (101), the second inverter (102), the third inverter (106) are TTL not gates.