CN109150140B - Differential relative delay regulator - Google Patents
Differential relative delay regulator Download PDFInfo
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- CN109150140B CN109150140B CN201810756437.6A CN201810756437A CN109150140B CN 109150140 B CN109150140 B CN 109150140B CN 201810756437 A CN201810756437 A CN 201810756437A CN 109150140 B CN109150140 B CN 109150140B
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
- H03K5/133—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals using a chain of active delay devices
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K2005/00013—Delay, i.e. output pulse is delayed after input pulse and pulse length of output pulse is dependent on pulse length of input pulse
- H03K2005/00019—Variable delay
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Abstract
The invention belongs to the technical field of integrated circuit delayers, and particularly relates to a differential type relative delay regulator. The invention provides a differential relative delay adjuster, which comprises a first delay adjusting channel and a second delay adjusting channel; the two channels have the same structure and are formed by sequentially cascading an input phase controller, a transmission delay regulator and an output phase controller; under the control of the same delay adjusting code and a pair of phase control bits with opposite logic values, the two channels generate a pair of output delay signals after the same input signals to be delayed are subjected to respective delay processing. The size of the relative delay adjustment granularity of the delay adjustment code between the two output delay signal jumping edges is equal to the absolute value of the difference of the transmission delay adjustment granularity of the transmission delay adjuster rising edge and the transmission delay adjustment granularity of the transmission delay adjuster falling edge in the channel. The invention reduces the relative delay adjustment granularity and improves the relative delay adjustment precision.
Description
Technical Field
The invention belongs to the technical field of integrated circuit delayers, and particularly relates to a differential type relative delay regulator.
Background
The delay chain is a module used for delaying a signal for a certain time in a digital circuit, the digital adjusting delay chain has the advantages of simple structure, good process compatibility and the like due to the digitalization characteristic, and the digital adjusting transmission delay chain based on the logic gate delay further meets the requirement of an automatic design process due to the fact that the digital adjusting transmission delay chain adopts a standard unit design on the basis of digitalization.
A known not-gate based transmission delay regulator is shown in fig. 1, wherein a dashed line box is a delay regulating unit which comprises a not-gate and two tri-state not-gates; after the delay adjusting units are cascaded, the NOT gate forms a delay chain; the delay adjusting code S < N:1> is a one-hot code (or called a one-bit effective code, wherein only one bit is an effective level), and a signal on one node of the delay chain can be selected as an output by controlling each stage of the tristate NOT gate, so that an output signal (OUT) with a certain transmission delay relative to an input signal (IN) is generated. In this configuration, the granularity of the adjustment of the delay adjustment code to the transmission delay is equal to the sum of the transmission delays of one not gate and one tri-state not gate. Fig. 2 shows the simulation result of the transmission delay adjustment characteristic of the structure: as the effective level in the 7-bit one-hot code S <7:1> is gradually moved from low level to high level, the transmission delay of the rising edge and the transmission delay of the falling edge both increase linearly, the slope of the transmission delay is the adjustment granularity of the transmission delay, so that the adjustment granularity of the transmission delay of the rising edge and the transmission delay of the falling edge are DR =69.3ps and DF =53.9ps respectively.
In the design of the delay adjuster, it is sometimes not necessary to implement the delay in transmission (i.e., the delay of the output signal relative to the input signal), but it can also be implemented in relative delay (i.e., the delay between two or more output delay signals generated by the same input signal). The two-phase non-overlapping clock is an example, and the two-phase non-overlapping clock utilizes relative delay to generate a pair of non-overlapping clocks, and is widely applied to the fields of time sequence optimization, switched capacitor circuits, low-power-consumption digital circuits and the like. Since the non-overlap time is sensitive to non-ideal factors such as process, voltage, temperature, parasitic parameters, etc., the non-overlap time needs to be adjusted to compensate for the non-ideal factors in order to ensure the circuit functions properly or perform performance optimization. However, in the known dual-phase tunable non-overlapping clock circuit (US 7352222: "clock generator with programmable non-overlapping-clock-edge capability"), the non-overlapping time is still realized by adjusting the transmission delay; as shown in fig. 2, the transmission delay adjustment granularity based on the gate delay is typically several tens of ps, so it is difficult to adjust the relative delay more finely in a manner of adjusting the transmission delay.
The known relative delay regulator has the following disadvantages: the granularity of adjustment is limited by the gate-level transmission delay and is difficult to further reduce.
Disclosure of Invention
The invention aims to provide a differential relative delay regulator to solve the problem that the regulation granularity of the known relative delay regulator is limited by the transmission delay of a logic gate and is difficult to further reduce.
The differential relative delay adjuster provided by the invention comprises two delay adjusting channels with the same structure; under the control of the same delay adjusting code and a pair of phase control bits with opposite logic values, the two channels generate a pair of output delay signals after the same input signals to be delayed are subjected to respective delay processing. The size of the relative delay adjustment granularity of the delay adjustment code between the two output delay signal jumping edges is equal to the absolute value of the difference of the transmission delay adjustment granularity of the transmission delay adjuster rising edge and the transmission delay adjustment granularity of the transmission delay adjuster falling edge in the channel. The invention reduces the relative delay adjustment granularity and improves the relative delay adjustment precision.
The differential relative delay adjuster, as shown in fig. 3, comprises a first delay adjusting channel (100) and a second delay adjusting channel (200);
(1) the first delay adjusting channel (100) is formed by sequentially cascading an input phase controller (101), a transmission delay adjuster (103) and an output phase controller (102); the second delay adjusting channel (200) is formed by sequentially cascading an input phase controller (201), a transmission delay adjuster (203) and an output phase controller (202); the two delay adjustment channels (100 and 200) are identical in structure: namely, the input phase controller (101) is the same as the input phase controller (201), the transmission delay adjuster (103) is the same as the transmission delay adjuster (203), and the output phase controller (102) is the same as the output phase controller (202);
(2) the first delay adjustment path (100) and the second delay adjustment path (200) have the same input to-be-delayed signal (CLK 0) and generate a first output delayed signal (CLK 1) and a second output delayed signal (CLK 2), respectively;
(3) the phase selection terminals (C) of a pair of input/output phase controllers (101 and 102) in the first delay adjustment channel (100) are connected to a first phase control bit (PC 1), and the phase selection terminals (C) of a pair of input/output phase controllers (201 and 202) in the second delay adjustment channel (200) are connected to a second phase control bit (PC 2);
(4) transmission delay adjusters (103 and 203) in the two delay adjusting channels (100 and 200), whose delay adjusting terminals (T < N:1 >) are connected to the same delay adjusting code (DC < N:1 >); the transmission delay adjustment granularity of the transmission delay adjuster (103 and 203) on the rising edge is DR and the transmission delay adjustment granularity of the falling edge is DF by the delay adjustment code (DC < N:1 >).
In the above scheme, the phase controller (101, or 102, or 201, or 202) transmits the signal of its input terminal (I) to its output terminal (O) in-phase or in reverse phase under the control of the phase selection terminal (C); the phase control bit (PC 1 or PC 2) controls a pair of input/output phase controllers (101 and 102, or 201 and 202) to configure the delay adjusting channel (100 or 200) in which the phase control bit is located into two working modes:
(1) in the first delay adjusting channel (100), when a pair of input/output phase controllers (101 and 102) are in-phase transmission, the first delay adjusting channel (100) in which the first delay adjusting channel is located works in an in-phase delay mode; in the second delay adjusting channel (200), when a pair of input/output phase controllers (201 and 202) are in-phase transmission, the second delay adjusting channel (200) in which the input/output phase controllers are located works in an in-phase delay mode;
(2) in the first delay adjusting channel (100), when a pair of input and output phase controllers (101 and 102) are in reverse phase transmission, the first delay adjusting channel (100) in which the first delay adjusting channel is located works in a reverse phase delay mode; in the second delay adjusting channel (200), when a pair of input and output phase controllers (201 and 202) are in reverse phase transmission, the second delay adjusting channel (200) in which the input and output phase controllers are located works in a reverse phase delay mode.
In the above scheme, the first phase control bit (PC 1) and the second phase control bit (PC 2) have opposite logic states, and the two delay adjustment paths (100 and 200) are configured to operate in different modes:
(1) when the first delay adjusting path (100) and the second delay adjusting path (200) work in an in-phase delay mode and a reverse delay mode respectively, the relative delay adjusting granularity (dR) of the rising edge and the relative delay adjusting granularity (dF) of the falling edge of the first output delay signal (CLK 1) relative to the second output delay signal (CLK 2) satisfy the relation 1:
relation 1:
；
(2) when the first delay adjusting path (100) and the second delay adjusting path (200) respectively work in an anti-phase delay mode and an in-phase delay mode, the relative delay adjusting granularity (dR) of the rising edge and the relative delay adjusting granularity (dF) of the falling edge of the first output delay signal (CLK 1) relative to the second output delay signal (CLK 2) satisfy the relation 2:
relation 2:
。
the invention has the beneficial effects that: the granularity of relative delay adjustment is reduced, and the precision of relative delay adjustment is improved.
Drawings
Fig. 1 is a known not-gate based transmission delay adjuster structure.
Fig. 2 is a simulation result of the propagation delay adjusting characteristic of a known not-gate based digitally adjusted propagation delay chain.
Fig. 3 is a differential type relative delay adjuster of the present invention.
FIG. 4 is a diagram of an embodiment of a phase controller in a differential phase delay regulator of the present invention.
Fig. 5 is a simulation result of the relative delay adjusting characteristic of the differential type relative delay adjuster of the present invention.
Detailed Description
For the purpose of facilitating understanding, the invention will be described in detail below with reference to specific drawings and embodiments. It should be noted that fig. 3 to 5 are merely examples of the embodiments of the present invention, and the specific embodiments and details within the scope of the claims of the present invention are not limited to fig. 3 to 5. It will be appreciated by those skilled in the art that the embodiments of fig. 3-5 of the present invention are capable of being modified and varied in accordance with the teachings herein without departing from the scope of the present invention.
FIG. 3 is a differential type relative delay adjuster of the present invention, including a first delay adjusting path (100) and a second delay adjusting path (200); the two delay adjusting channels (100 and 200) have the same structure and are formed by sequentially cascading an input phase controller (101 or 201), a transmission delay adjuster (103 or 203) and an output phase controller (102 or 202); the first delay adjustment path (100) and the second delay adjustment path (200) have the same input to-be-delayed signal (CLK 0) and generate a first output delayed signal (CLK 1) and a second output delayed signal (CLK 2), respectively; the phase selection terminals (C) of a pair of input/output phase controllers (101 and 102) in the first delay adjustment channel (100) are connected to a first phase control bit (PC 1), and the phase selection terminals (C) of a pair of input/output phase controllers (201 and 202) in the second delay adjustment channel (200) are connected to a second phase control bit (PC 2); transmission delay adjusters (103 and 203) in the two delay adjusting channels (100 and 200), whose delay adjusting terminals (T < N:1 >) are connected to the same delay adjusting code (DC < N:1 >); the transmission delay adjustment granularity of the transmission delay adjuster (103 and 203) on the rising edge is DR and the transmission delay adjustment granularity of the falling edge is DF by the delay adjustment code (DC < N:1 >).
FIG. 4 is a diagram of one embodiment of a phase controller in a differential phase delay regulator of the present invention, including an inverter and an alternative selector; the signal of the input end (I) is respectively connected to two input ends of the alternative selector directly or through an inverter and is selected by a phase selection end (C): when C =0, the phase controller transmits the input end (I) signal to the output end (O) in phase; when C =1, the phase controller transmits the input end (I) signal to the output end (O) in reverse phase. The input phase controllers (101 and 201) and the output phase controllers (102 and 202) may employ phase controllers of the same structure.
Fig. 5 is a simulation result of the variation of the relative delay with the delay adjustment code in one embodiment of the differential type relative delay adjuster of the present invention. In this embodiment, the transmission delay adjuster is a known transmission delay adjuster as shown in fig. 1 (at this time, the delay adjusting end T < N:1> is S < N:1 >), and the phase controller is a circuit structure as shown in fig. 4; meanwhile, a pair of phase control bits PC1=0 and PC2=1 configure the first delay adjusting channel (100) and the second delay adjusting channel (200) into an in-phase delay operation mode and an anti-phase delay operation mode, respectively. Then, substituting the resulting rising and falling edge propagation delay adjustment granularity (DR =69.3ps and DF =53.9 ps) in fig. 2 into relation 1, then: the theoretical value of the relative delay adjustment granularity of the rising edge of the first output delayed signal (CLK 1) relative to the second output delayed signal (CLK 2) is:
the theoretical values of the relative delay adjustment granularity of the falling edge are as follows:
wherein the granularity is a negative sign indicating a lead; from the simulation result of the relative delay adjustment characteristic in fig. 5, the slope is calculated to obtain that the relative delay adjustment granularity of the rising edge and the falling edge is dR =15.2ps and dF = -15.3ps, respectively, and the simulation result is substantially consistent with the theoretical value.
Claims (3)
1. A differential type relative delay adjuster, comprising a first delay adjusting path (100) and a second delay adjusting path (200); wherein:
(1) the first delay adjusting channel (100) is formed by sequentially cascading an input phase controller (101), a transmission delay adjuster (103) and an output phase controller (102); the second delay adjusting channel (200) is formed by sequentially cascading an input phase controller (201), a transmission delay adjuster (203) and an output phase controller (202); the two delay adjustment channels (100 and 200) are identical in structure:
(2) the first delay adjustment path (100) and the second delay adjustment path (200) have the same input to-be-delayed signal (CLK 0) and generate a first output delayed signal (CLK 1) and a second output delayed signal (CLK 2), respectively;
(3) the phase selection terminals (C) of a pair of input/output phase controllers (101 and 102) in the first delay adjustment channel (100) are connected to a first phase control bit (PC 1), and the phase selection terminals (C) of a pair of input/output phase controllers (201 and 202) in the second delay adjustment channel (200) are connected to a second phase control bit (PC 2); the first phase control bit (PC 1) and the second phase control bit (PC 2) are opposite in logic value;
(4) transmission delay adjusters (103 and 203) in the two delay adjusting channels (100 and 200), whose delay adjusting terminals (T < N:1 >) are connected to the same delay adjusting code (DC < N:1 >); the transmission delay adjustment granularity of the transmission delay adjuster (103 and 203) on the rising edge is DR and the transmission delay adjustment granularity of the falling edge is DF by the delay adjustment code (DC < N:1 >).
2. A differential-type relative delay regulator according to claim 1, wherein said phase controller (101, or 102, or 201, or 202) is controlled by said phase selection terminal (C) to transmit the signal at its input terminal (I) in-phase or in-phase with the signal at its output terminal (O); the phase control bit (PC 1 or PC 2) controls a pair of input/output phase controllers (101 and 102, or 201 and 202) to configure the delay adjusting channel (100 or 200) in which the phase control bit is located into two working modes:
(1) in the first delay adjusting channel (100), when a pair of input/output phase controllers (101 and 102) are in-phase transmission, the first delay adjusting channel (100) in which the first delay adjusting channel is located works in an in-phase delay mode; in the second delay adjusting channel (200), when a pair of input/output phase controllers (201 and 202) are in-phase transmission, the second delay adjusting channel (200) in which the input/output phase controllers are located works in an in-phase delay mode;
(2) in the first delay adjusting channel (100), when a pair of input and output phase controllers (101 and 102) are in reverse phase transmission, the first delay adjusting channel (100) in which the first delay adjusting channel is located works in a reverse phase delay mode; in the second delay adjusting channel (200), when a pair of input and output phase controllers (201 and 202) are in reverse phase transmission, the second delay adjusting channel (200) in which the input and output phase controllers are located works in a reverse phase delay mode.
3. A differential-type relative delay regulator as claimed in claim 2, wherein said first phase control bit (PC 1) and said second phase control bit (PC 2) have opposite logic states, and wherein said two delay regulation paths (100 and 200) are configured to operate in different modes:
(1) when the first delay adjusting path (100) and the second delay adjusting path (200) work in an in-phase delay mode and a reverse delay mode respectively, the relative delay adjusting granularity (dR) of the rising edge and the relative delay adjusting granularity (dF) of the falling edge of the first output delay signal (CLK 1) relative to the second output delay signal (CLK 2) satisfy the relation 1:
relation 1:
；
(2) when the first delay adjusting path (100) and the second delay adjusting path (200) respectively work in an anti-phase delay mode and an in-phase delay mode, the relative delay adjusting granularity (dR) of the rising edge and the relative delay adjusting granularity (dF) of the falling edge of the first output delay signal (CLK 1) relative to the second output delay signal (CLK 2) satisfy the relation 2:
relation 2:
。
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| CN1542585A (en) * | 2002-11-18 | 2004-11-03 | 尔必达存储器株式会社 | Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them |
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| US8907709B1 (en) * | 2013-08-08 | 2014-12-09 | Realtek Semiconductor Corporation | Delay difference detection and adjustment device and method |
| CN205015669U (en) * | 2015-10-10 | 2016-02-03 | 深圳市建恒测控股份有限公司 | Delay line circuit |
| CN207234746U (en) * | 2017-09-28 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of circuit structure for the automatic programmed delay for realizing digital display circuit |
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| JP2007243735A (en) * | 2006-03-09 | 2007-09-20 | Elpida Memory Inc | Dll circuit and semiconductor device comprising the same |
| JP5143370B2 (en) * | 2006-03-23 | 2013-02-13 | 富士通セミコンダクター株式会社 | Delay control circuit |
| EP2831603B1 (en) * | 2012-03-30 | 2019-11-13 | Intel Corporation | On-die all-digital delay measurement circuit |
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Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1542585A (en) * | 2002-11-18 | 2004-11-03 | 尔必达存储器株式会社 | Delay producing method, delay adjusting method based on the same, and delay producing circuit and delay adjusting circuit applied with them |
| CN101345518A (en) * | 2007-07-10 | 2009-01-14 | 南亚科技股份有限公司 | Delay circuit |
| US8907709B1 (en) * | 2013-08-08 | 2014-12-09 | Realtek Semiconductor Corporation | Delay difference detection and adjustment device and method |
| CN205015669U (en) * | 2015-10-10 | 2016-02-03 | 深圳市建恒测控股份有限公司 | Delay line circuit |
| CN207234746U (en) * | 2017-09-28 | 2018-04-13 | 郑州云海信息技术有限公司 | A kind of circuit structure for the automatic programmed delay for realizing digital display circuit |
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