CN109148614A - Silicon heterojunction solar battery and preparation method thereof - Google Patents
Silicon heterojunction solar battery and preparation method thereof Download PDFInfo
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- CN109148614A CN109148614A CN201710456695.8A CN201710456695A CN109148614A CN 109148614 A CN109148614 A CN 109148614A CN 201710456695 A CN201710456695 A CN 201710456695A CN 109148614 A CN109148614 A CN 109148614A
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 title claims abstract description 37
- 229910052710 silicon Inorganic materials 0.000 title claims abstract description 37
- 239000010703 silicon Substances 0.000 title claims abstract description 37
- 238000002360 preparation method Methods 0.000 title abstract description 9
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 153
- 229910045601 alloy Inorganic materials 0.000 claims abstract description 136
- 239000000956 alloy Substances 0.000 claims abstract description 136
- 229910052751 metal Inorganic materials 0.000 claims abstract description 79
- 239000002184 metal Substances 0.000 claims abstract description 79
- 230000007704 transition Effects 0.000 claims abstract description 77
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 claims abstract description 50
- 239000000758 substrate Substances 0.000 claims abstract description 31
- 229910021419 crystalline silicon Inorganic materials 0.000 claims abstract description 22
- 239000010949 copper Substances 0.000 claims description 36
- 238000000034 method Methods 0.000 claims description 34
- 229910052802 copper Inorganic materials 0.000 claims description 19
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 15
- 238000005275 alloying Methods 0.000 claims description 15
- 238000000151 deposition Methods 0.000 claims description 14
- 239000000126 substance Substances 0.000 claims description 11
- 238000000137 annealing Methods 0.000 claims description 10
- 230000008021 deposition Effects 0.000 claims description 10
- 239000013078 crystal Substances 0.000 claims description 8
- 229910003310 Ni-Al Inorganic materials 0.000 claims description 7
- 229910052804 chromium Inorganic materials 0.000 claims description 7
- 229910052759 nickel Inorganic materials 0.000 claims description 7
- 229910052719 titanium Inorganic materials 0.000 claims description 7
- 229910052721 tungsten Inorganic materials 0.000 claims description 7
- 229910017755 Cu-Sn Inorganic materials 0.000 claims description 6
- 229910017927 Cu—Sn Inorganic materials 0.000 claims description 6
- 229910000846 In alloy Inorganic materials 0.000 claims description 6
- 229910002065 alloy metal Inorganic materials 0.000 claims description 6
- 229910052782 aluminium Inorganic materials 0.000 claims description 6
- 229910052796 boron Inorganic materials 0.000 claims description 6
- 229910052733 gallium Inorganic materials 0.000 claims description 6
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 6
- 229910052737 gold Inorganic materials 0.000 claims description 6
- 239000010931 gold Substances 0.000 claims description 6
- 229910052738 indium Inorganic materials 0.000 claims description 6
- 229910052750 molybdenum Inorganic materials 0.000 claims description 6
- 229910052698 phosphorus Inorganic materials 0.000 claims description 6
- 229910052725 zinc Inorganic materials 0.000 claims description 6
- 229910052749 magnesium Inorganic materials 0.000 claims description 5
- 229910052709 silver Inorganic materials 0.000 claims description 5
- 238000005229 chemical vapour deposition Methods 0.000 claims description 4
- 238000001704 evaporation Methods 0.000 claims description 3
- 230000008020 evaporation Effects 0.000 claims description 3
- 238000005268 plasma chemical vapour deposition Methods 0.000 claims description 3
- 238000004544 sputter deposition Methods 0.000 claims description 3
- 229910052755 nonmetal Inorganic materials 0.000 claims 1
- 230000000694 effects Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 10
- 239000000853 adhesive Substances 0.000 description 6
- 230000001070 adhesive effect Effects 0.000 description 6
- 239000003963 antioxidant agent Substances 0.000 description 5
- 230000003078 antioxidant effect Effects 0.000 description 5
- 235000006708 antioxidants Nutrition 0.000 description 5
- 230000015572 biosynthetic process Effects 0.000 description 5
- 230000008859 change Effects 0.000 description 5
- 229910052718 tin Inorganic materials 0.000 description 5
- 229910052789 astatine Inorganic materials 0.000 description 4
- 150000001875 compounds Chemical class 0.000 description 4
- 238000010586 diagram Methods 0.000 description 4
- 239000007772 electrode material Substances 0.000 description 4
- 239000010408 film Substances 0.000 description 4
- 229910000510 noble metal Inorganic materials 0.000 description 4
- 238000007747 plating Methods 0.000 description 4
- 239000002002 slurry Substances 0.000 description 4
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 3
- 238000009792 diffusion process Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 229910052739 hydrogen Inorganic materials 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
- 238000005984 hydrogenation reaction Methods 0.000 description 3
- 230000006872 improvement Effects 0.000 description 3
- 238000002955 isolation Methods 0.000 description 3
- 238000004519 manufacturing process Methods 0.000 description 3
- 238000002161 passivation Methods 0.000 description 3
- 230000008569 process Effects 0.000 description 3
- 230000002829 reductive effect Effects 0.000 description 3
- 238000004062 sedimentation Methods 0.000 description 3
- 229910052715 tantalum Inorganic materials 0.000 description 3
- 238000010521 absorption reaction Methods 0.000 description 2
- 230000002411 adverse Effects 0.000 description 2
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
- 230000007797 corrosion Effects 0.000 description 2
- 238000005260 corrosion Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000010790 dilution Methods 0.000 description 2
- 239000012895 dilution Substances 0.000 description 2
- 230000005611 electricity Effects 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 230000000670 limiting effect Effects 0.000 description 2
- 150000002739 metals Chemical class 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 229910052760 oxygen Inorganic materials 0.000 description 2
- 239000001301 oxygen Substances 0.000 description 2
- 238000001259 photo etching Methods 0.000 description 2
- 230000008439 repair process Effects 0.000 description 2
- 238000005245 sintering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 229910001128 Sn alloy Inorganic materials 0.000 description 1
- 125000004429 atom Chemical group 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000003153 chemical reaction reagent Substances 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 230000002708 enhancing effect Effects 0.000 description 1
- 230000007613 environmental effect Effects 0.000 description 1
- 230000003628 erosive effect Effects 0.000 description 1
- 230000006870 function Effects 0.000 description 1
- 125000004435 hydrogen atom Chemical group [H]* 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 239000012528 membrane Substances 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 238000005036 potential barrier Methods 0.000 description 1
- 230000001681 protective effect Effects 0.000 description 1
- 238000005215 recombination Methods 0.000 description 1
- 230000006798 recombination Effects 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 238000007650 screen-printing Methods 0.000 description 1
- 239000000243 solution Substances 0.000 description 1
- 229910052723 transition metal Inorganic materials 0.000 description 1
- 150000003624 transition metals Chemical class 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000003466 welding Methods 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/02—Details
- H01L31/0224—Electrodes
- H01L31/022408—Electrodes for devices characterised by at least one potential jump barrier or surface barrier
- H01L31/022425—Electrodes for devices characterised by at least one potential jump barrier or surface barrier for solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
- H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier
- H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type
- H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
- H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by at least one potential-jump barrier or surface barrier the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer or HIT® solar cells; solar cells
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
- H01L31/20—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials
- H01L31/202—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof such devices or parts thereof comprising amorphous semiconductor materials including only elements of Group IV of the Periodic System
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E10/00—Energy generation through renewable energy sources
- Y02E10/50—Photovoltaic [PV] energy
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
Abstract
The invention discloses silicon heterojunction solar batteries and preparation method thereof.Wherein, which includes: n-type crystalline silicon substrate layer；The hydrogenated amorphous silicon buffer layer of lightly doped n-type, hydrogenated amorphous silicon buffer layer are formed in the upper and lower both side surface of substrate layer；The hydrogenated amorphous silicon emitter layer of heavily-doped p-type, hydrogenated amorphous silicon emitter layer are formed on the surface of the hydrogenated amorphous silicon buffer layer in side；Highly doped n-type amorphous silicon hydride back surface field layer, amorphous silicon hydride back surface field layer are formed on the surface of the hydrogenated amorphous silicon buffer layer in the other side；Including transparent conducting oxide layer, including transparent conducting oxide layer are formed on the surface of hydrogenated amorphous silicon emitter layer and amorphous silicon hydride back surface field layer；Metal grid lines electrode layer, metal grid lines electrode layer include: alloy transition layer, and alloy transition layer is formed on including transparent conducting oxide layer, amorphous silicon hydride back surface field layer and hydrogenated amorphous silicon emitter layer at least one layer surface；Cupric electrical conductivity alloy layer, cupric electrical conductivity alloy layer are formed on the surface of alloy transition layer.
Description
Technical field
The present invention relates to area of solar cell, in particular to the silicon heterogenous sun for including copper alloy electrode
Battery and preparation method thereof.
Background technique
In the conventional solar cell based on crystal silicon, the preparation of electrode generallys use silk-screen printing Ag slurry then high temperature (﹥
700 DEG C) mode of sintering forms the good Ohmic contact between Ag and substrate Si, used in slurry be that high temperature Ag is starched.
However, this method, which is formed by electrode, has the characteristics that material expensive, line width are wider and line is high limited, and limit more
The application of thin silicon wafer just becomes one of the limiting factor for further decreasing battery cost and improving efficiency.
In amorphous silicon/silicon/crystalline silicon heterojunction solar cell, due to forming p-n junction, thus film using amorphous silicon membrane
Formation temperature determines the highest preparation process temperature of battery, is typically only capable at 200 DEG C or so.It is low in order to meet hetero-junction solar cell
The requirement of temperature preparation, when make electrode, a kind of method is using low temperature Ag slurry, however this slurry is formed by after sintering
Electrode has significant raised series resistance, is unfavorable for the promotion of battery efficiency.Another solution is using base metal
Cu replace Ag.The cost of Cu is very low and conductivity and Ag are close, is a kind of very promising material.But in humidity
In environment, Cu is easily oxidized and corrodes, and is substantially increased resistance, strength reduction.Therefore, Cu electrode usually requires to carry out on surface
It is coated with and protects it from erosion.The Cu electrode generally used is to form Ni/ by the methods of chemical plating/plating/photoinduction plating
The laminated metal layer of Cu/Sn, W metal can stop diffusion of the Cu into silicon as barrier layer, and Sn be covered in Cu layer surface can
To play the role of protecting Cu not oxidized while facilitate welding.This electrode has thinner grid line and lower contact electricity
Resistance, but the problem poor there is also the adhesive force of laminated metal layer and substrate Si, and the barrier layer of single-element such as Ni, Ta,
The usually resistivity such as Ti, Cr is higher, can be improved electric conductivity if the alloy for forming Cu, while the alloying of Cu is also beneficial to change
The anti-oxidant corrosion resistance of kind fine copper.
Existing solar cell has much room for improvement as a result,.
Summary of the invention
The present invention is directed at least solve one of the technical problems existing in the prior art.For this purpose, one object of the present invention
It is to propose a kind of silicon heterojunction solar battery (be hereinafter also referred to as " solar cell "), passes through alloyed metal (AM) grid line
Electrode layer not only can effectively reduce cell series resistance, but also be conducive to improve the anti-oxidant performances such as anticorrosive of electrode, enhancing
Stability of the battery in application environment.
According to an aspect of the present invention, the present invention provides a kind of silicon heterojunction solar batteries.Reality according to the present invention
Example is applied, which includes:
N-type crystalline silicon substrate layer；
The hydrogenated amorphous silicon buffer layer of lightly doped n-type, the hydrogenated amorphous silicon buffer layer of lightly doped n-type are formed in the substrate
In the upper and lower both side surface of layer；
The hydrogenated amorphous silicon emitter layer of heavily-doped p-type, the hydrogenated amorphous silicon emitter layer of heavily-doped p-type are formed in side
On the surface of the hydrogenated amorphous silicon buffer layer of lightly doped n-type；
Highly doped n-type amorphous silicon hydride back surface field layer, the highly doped n-type amorphous silicon hydride back surface field layer are formed in other side institute
On the surface for stating the hydrogenated amorphous silicon buffer layer of lightly doped n-type；
Including transparent conducting oxide layer, the including transparent conducting oxide layer are formed in the heavily-doped p-type amorphous silicon hydride hair
On the surface of emitter layer and the highly doped n-type amorphous silicon hydride back surface field layer；
Metal grid lines electrode layer, the metal grid lines electrode layer include:
Alloy transition layer, the alloy transition layer are formed in the including transparent conducting oxide layer, highly doped n-type hydrogenation
On at least one layer of surface of amorphous silicon back surface field layer and the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type；
Cupric electrical conductivity alloy layer, the cupric electrical conductivity alloy layer are formed on the surface of the alloy transition layer.
Solar cell according to an embodiment of the present invention, metal grid lines electrode layer are to be formed by alloying metal, and alloy is golden
The main component of category is copper, therefore significantly reduces the use of the noble metals such as Ag while keeping lower resistivity, and
A degree of alloying can effectively improve the anti-oxidant performances such as anticorrosive of single metal, enhance battery in application environment
Stability, wherein alloy transition layer not only can increase electrode in the adhesive force, improvement battery material and electrode material of battery surface
Between thermal expansion coefficient matching degree etc., can also be played by the position that doped chemical contacts battery with electrode part mix
Miscellaneous effect, reduces the series resistance of emitter or back surface field and grid line, improves battery fill factor and battery effect to realize
The effect of rate.
In addition, solar cell according to the above embodiment of the present invention, can also have the following additional technical features:
According to an embodiment of the invention, the doping concentration of the lightly doped n-type hydrogenated amorphous silicon layer is 108-1017/cm3。
According to an embodiment of the invention, the alloy transition layer contain selected from Cu, Mo, W, Ti, Ni, Cr, Al, Mg, Ta,
At least two metals in Sn, Zn and Ag, it is preferable that the alloy transition layer contains Ni-Cu-Sn alloy, Ni-Cu-In alloy
Or Ni-Al alloy.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer contain Cu and selected from Mo, W, Ti, Ni, Cr, Al, Mg,
At least one of Ta, Sn, Zn and Ag metal.
According to an embodiment of the invention, the alloy transition layer can also be further containing the member in B, P, Ga and In
Element.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer can also be further containing in B, P, Ga and In
At least one element.
According to an embodiment of the invention, the copper content of the cupric electrical conductivity alloy layer is by nearly alloy transition layer end to far
Alloy transition layer end is incremented by gradient, and the copper content at nearly alloy transition layer end is 85%-99%wt, the remote conjunction
The copper content at golden transition zone end is 99%-100%wt.
According to an embodiment of the invention, the resistivity of the metal grid lines electrode layer is not more than 1.5 × 10-5Ω·cm。
According to an embodiment of the invention, the n-type crystalline silicon substrate layer with a thickness of 50-200 μm.
According to an embodiment of the invention, the hydrogenated amorphous silicon buffer layer of lightly doped n-type with a thickness of 1-15nm.
According to an embodiment of the invention, the hydrogenated amorphous silicon emitter layer of heavily-doped p-type with a thickness of 5-25nm.
According to an embodiment of the invention, the highly doped n-type amorphous silicon hydride back surface field layer with a thickness of 5-25nm.
According to an embodiment of the invention, the including transparent conducting oxide layer with a thickness of 50-300nm.
According to an embodiment of the invention, the alloy transition layer with a thickness of 5-300nm.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer with a thickness of 1-100 μm.
According to another aspect of the present invention, the present invention provides a kind of sides for preparing silicon heterojunction solar battery above-mentioned
Method.According to an embodiment of the invention, this method comprises:
N-type crystalline silicon substrate layer is provided；
The hydrogenated amorphous silicon buffer layer of lightly doped n-type is formed in the upper and lower both side surface of the n-type crystalline silicon substrate layer；
Heavily-doped p-type amorphous silicon hydride hair is formed on the surface of the hydrogenated amorphous silicon buffer layer of the lightly doped n-type described in side
Emitter layer；
Highly doped n-type amorphous silicon hydride is formed on the surface of the hydrogenated amorphous silicon buffer layer of the lightly doped n-type described in the other side
Back surface field layer；
In the table of the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type and the highly doped n-type amorphous silicon hydride back surface field layer
Including transparent conducting oxide layer is respectively formed on face；And
In the including transparent conducting oxide layer, the highly doped n-type amorphous silicon hydride back surface field layer and the heavily-doped p-type hydrogen
Change and form metal grid lines electrode layer on at least one layer of surface of amorphous silicon emitter layer, wherein the metal grid lines electrode layer
Contain alloy transition layer and cupric electrical conductivity alloy layer.
The method according to an embodiment of the present invention for preparing solar cell above-mentioned, the solar cell being prepared have alloy
The main component of metal grid lines electrode layer, the electrode layer is copper, therefore is significantly reduced while keeping lower resistivity
The use of the noble metals such as Ag, and a degree of alloying can effectively improve the anti-oxidant performances such as anticorrosive of single metal,
Enhance stability of the battery in application environment, wherein alloy transition layer not only can increase electrode battery surface adhesive force,
Improve the matching degree etc. of the thermal expansion coefficient between battery material and electrode material, it can also be by doped chemical to battery and electricity
The position of pole contact plays the role of locally adulterating, and the series resistance of emitter and grid line is reduced, to realize raising battery
The effect of fill factor and battery efficiency.
In addition, the method according to the above embodiment of the present invention for preparing solar cell, can also have following additional skill
Art feature:
According to an embodiment of the invention, the hydrogenated amorphous silicon buffer layer of the N-shaped, heavily-doped p-type amorphous silicon hydride hair
Emitter layer and the highly doped n-type amorphous silicon hydride back surface field layer are using plasma enhanced chemical vapor sedimentation, hot-wire chemical
What vapor deposition, microwave plasma CVD or electron cyclotron resonance chemical vapor deposition were formed.
According to an embodiment of the invention, the alloy transition layer is formed using physical vaporous deposition, it is preferable that institute
Stating physical vaporous deposition is evaporation deposition method and sputtering method.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer is formed using galvanoplastic.
According to an embodiment of the invention, the method for forming the metal grid lines electrode layer includes: in the electrically conducting transparent oxygen
At least one layer of surface of compound layer, the amorphous silicon hydride back surface field layer and the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type
Upper deposit alloy metal, to form alloy transition layer；It is formed on the surface of the alloy transition layer using photoresistance film predetermined
The mask layer of pattern；The cupric electrical conductivity alloy layer is formed on the surface of the alloy transition layer, and the cupric conduction is closed
Layer gold and the mask layer are arranged in a crossed manner；The alloy transition layer of the mask layer and mask layer covering is removed, to be formed
Metal grid lines electrode layer intermediate；The metal grid lines electrode layer intermediate is made annealing treatment, to obtain the metal
Gate line electrode layer.
According to an embodiment of the invention, the alloying metal is Ni-Cu-Sn alloy or Ni-Cu-In alloy.
According to an embodiment of the invention, the including transparent conducting oxide layer is nearly amorphous silicon hydride back surface field layer end or institute
State the including transparent conducting oxide layer at hydrogenated amorphous silicon emitter layer end.
According to an embodiment of the invention, the method for forming the metal grid lines electrode layer includes: that removal part is described transparent
Conductive oxide layer, to form the including transparent conducting oxide layer with predetermined pattern, wherein the including transparent conducting oxide layer
For the including transparent conducting oxide layer of the nearly hydrogenated amorphous silicon emitter layer；In the electrically conducting transparent with predetermined pattern
Deposit alloy metal on the surface of oxide skin(coating) and the hydrogenated amorphous silicon emitter layer, to form alloy transition layer；Institute
It states and forms mask layer on the surface of the alloy transition layer above including transparent conducting oxide layer；Emit in the amorphous silicon hydride
The cupric electrical conductivity alloy layer is formed on the surface of the alloy transition layer of pole layer top, to form metal grid lines electrode layer
Intermediate, wherein the cupric electrical conductivity alloy layer and the mask layer are arranged in a crossed manner；Remove the mask layer and the mask layer
The alloy transition layer of covering, to form metal grid lines electrode layer intermediate；The metal grid lines electrode layer intermediate is carried out
Annealing, to obtain the metal grid lines electrode layer.
According to an embodiment of the invention, the alloying metal is Ni-Al alloy.
Additional aspect and advantage of the invention will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 shows the structural schematic diagram of solar cell according to an embodiment of the invention；
Fig. 2 shows the structural schematic diagram of solar cell according to an embodiment of the invention；
Fig. 3 shows the pilot process schematic diagram of the method according to an embodiment of the invention for preparing solar cell；
Fig. 4 shows the flow diagram of the method according to an embodiment of the invention for preparing solar cell.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, and for explaining only the invention, and is not considered as limiting the invention.
In the description of the present invention, term " longitudinal direction ", " transverse direction ", "upper", "lower", "front", "rear", "left", "right", " perpendicular
Directly ", the orientation or positional relationship of the instructions such as "horizontal", "top", "bottom" is to be based on the orientation or positional relationship shown in the drawings, and is only
For ease of description the present invention rather than require the present invention that must be constructed and operated in a specific orientation, therefore should not be understood as pair
Limitation of the invention.
It should be noted that term " first ", " second " are used for description purposes only, it is not understood to indicate or imply phase
To importance or implicitly indicate the quantity of indicated technical characteristic.Define " first " as a result, the feature of " second " can be with
Explicitly or implicitly include one or more of the features.Further, in the description of the present invention, unless otherwise saying
Bright, the meaning of " plurality " is two or more.
According to an aspect of the present invention, the present invention provides a kind of silicon heterojunction solar batteries.With reference to Fig. 1 and 2, according to
The solar cell is explained in the embodiment of the present invention, which includes: n-type crystalline silicon substrate layer 100, gently mixes
The hydrogenated amorphous silicon buffer layer 200 of miscellaneous N-shaped, the hydrogenated amorphous silicon emitter layer 300 of heavily-doped p-type, highly doped n-type amorphous silicon hydride back
Field layer 400, including transparent conducting oxide layer 500 and metal grid lines electrode layer 600.Solar cell according to an embodiment of the present invention, gold
Belonging to gate line electrode layer is to be formed by alloying metal, and the main component of alloying metal is copper, therefore keeping lower resistivity
While significantly reduce the use of the noble metals such as Ag, and a degree of alloying can effectively improve the anti-of single metal
The performances such as anticorrosive are aoxidized, enhance stability of the battery in application environment, wherein alloy transition layer not only can increase electrode and exist
The adhesive force of battery surface improves the matching degree of thermal expansion coefficient between battery material and electrode material etc., can also pass through
The position that doped chemical contacts battery with electrode plays the role of locally adulterating, and reduces the series resistance of emitter and grid line,
To realize the effect for improving battery fill factor and battery efficiency.
It is explained below with reference to silicon heterojunction solar battery of the Fig. 1 and 2 to the embodiment of the present invention, specific as follows:
N-type crystalline silicon substrate layer 100: according to an embodiment of the invention, the other structures that the substrate layer 100 is solar cell mention
For the carrier of attachment.
According to an embodiment of the invention, the substrate layer 100 with a thickness of 50-200 μm.
The hydrogenated amorphous silicon buffer layer 200 of lightly doped n-type: according to an embodiment of the invention, the lightly doped n-type amorphous silicon hydride
Buffer layer 200 is formed in the upper and lower both side surface of substrate layer 100.Hydrogenated amorphous silicon buffer layer can be by introducing hydrogen as a result,
Dangling bonds in silicon thin film of the atom to repair deposition reduce the defects of lattice, thus, this is substituted using hydrogenated amorphous silicon layer
Under the premise of sign amorphous silicon can guarantee good interface passivation effect as passivation layer, make the permissible thickness of hydrogenated amorphous silicon layer
It spends range to increase, so that preparation process window be made to broaden, reduces battery manufacture difficulty, and series resistance can be significantly improved, mention
High battery performance.
According to an embodiment of the invention, the doping concentration of the lightly doped n-type hydrogenated amorphous silicon layer is 108-1017/cm3。
According to an embodiment of the invention, the hydrogenated amorphous silicon buffer layer 200 of the lightly doped n-type with a thickness of 1-15nm.Due to
Hydrogenated amorphous silicon buffer layer can integrate passivation effect and reduce potential barrier, and the thickness of hydrogenated amorphous silicon buffer layer allows appropriate increase
Add, so as to reduce technology difficulty.
The hydrogenated amorphous silicon emitter layer 300 of heavily-doped p-type: according to an embodiment of the invention, the heavily-doped p-type is hydrogenated amorphous
Silicon emitter layer 300 is formed on the surface of the hydrogenated amorphous silicon buffer layer 200 of side lightly doped n-type, that is to say, that non-hydrogenating
The hydrogenated amorphous silicon emitter layer 300 of heavily-doped p-type is formed on a surface in 200 two outer surfaces of crystal silicon buffer layer.
According to an embodiment of the invention, the hydrogenated amorphous silicon emitter layer 300 of the heavily-doped p-type with a thickness of 5-25nm.Weight
The hydrogenated amorphous silicon emitter layer of doped p type can be used for forming p-n junction built in field with n-type crystalline silicon substrate layer.As emitter,
Since the p layer of high carrier concentration has a stronger absorption for short wavelength light, and to adulterate the internal flaw to be formed more by the B of p-type, makes
It is compound in fault location to being easy that the photon of absorption is formed by hole, causes the loss of short wavelength light, so heavily-doped p-type hydrogenation is non-
Amorphous silicon in crystal silicon emitter layer had not only needed sufficiently high doping concentration, but also needed thickness small as far as possible.On the other hand,
If the thickness of the hydrogenated amorphous silicon emitter layer of heavily-doped p-type is too small, the hydrogenated amorphous silicon emitter layer of heavily-doped p-type may be made
The carrier in a big chunk region influences the output of electric current due to being located near p-n junction and by dilution, and by light by first
It adulterates N-shaped hydrogenated amorphous silicon layer to be arranged between the hydrogenated amorphous silicon emitter layer of heavily-doped p-type and n-type crystalline silicon substrate, Ke Yiyou
Effect reduces being influenced by dilution effect for carrier, to further increase the performance of battery.
Highly doped n-type amorphous silicon hydride back surface field layer 400: according to an embodiment of the invention, the amorphous silicon hydride back surface field layer 400
It is formed on the surface of the hydrogenated amorphous silicon buffer layer 200 of other side lightly doped n-type.That is, in hydrogenated amorphous silicon buffer layer
Highly doped n-type amorphous silicon hydride back surface field layer 400 is formed on another surface in two outer surfaces.
The electric field formed between highly doped n-type amorphous silicon hydride back surface field layer and n-type crystalline silicon substrate layer as a result, can help to carry
Stream is efficiently transferred to conductive layer, and is arranged between highly doped n-type amorphous silicon hydride back surface field layer and n-type crystalline silicon substrate layer
The hydrogenated amorphous silicon buffer layer of lightly doped n-type can reduce Carrier recombination, to improve the performance of battery.
According to an embodiment of the invention, the highly doped n-type amorphous silicon hydride back surface field layer 300 with a thickness of 5-25nm.As a result,
Carrier in the compound significant decrease of battery surface, solar cell it is more efficient.
Including transparent conducting oxide layer 500: according to an embodiment of the invention, the including transparent conducting oxide layer 500 is formed in weight
On the surface of the hydrogenated amorphous silicon emitter layer 300 of doped p type and highly doped n-type amorphous silicon hydride back surface field layer 400.
Wherein, it is emphasized that, which can be formed in hydrogenated amorphous silicon emitter layer
300 and amorphous silicon hydride back surface field layer 400 all surfaces on, that is, hydrogenated amorphous silicon emitter layer 300 is completely covered and hydrogenates non-
The surface of crystal silicon back surface field layer 400 can also be formed in hydrogenated amorphous silicon emitter layer 300 and amorphous silicon hydride back surface field layer 400
In part of the surface, i.e., the part of the surface of hydrogenated amorphous silicon emitter layer 300 and amorphous silicon hydride back surface field layer 400 is only covered, it is remaining
Part can then be covered by transition metal layer.
Metal grid lines electrode layer 600: according to an embodiment of the invention, the metal grid lines electrode layer 600 includes: alloy transition
Layer 610 and cupric electrical conductivity alloy layer 620, wherein alloy transition layer 610 is formed in including transparent conducting oxide layer 500, hydrogenated amorphous
On at least one layer of surface of silicon back surface field layer 400 and the hydrogenated amorphous silicon emitter layer 300 of heavily-doped p-type, cupric electrical conductivity alloy layer
620 are formed on the surface of alloy transition layer 610.Wherein, it should be noted that the alloy transition layer 610 of solar cell can be with
Separately it is formed in including transparent conducting oxide layer 500 or amorphous silicon hydride back surface field layer 400 or heavily-doped p-type amorphous silicon hydride
On emitter layer 300, it can also be respectively formed on arbitrary two layers therein or three layers.Alloy transition layer is not only as a result,
It can increase the matching degree of thermal expansion coefficient of the electrode between the adhesive force, improvement battery material and electrode material of battery surface
Deng can also play the role of locally adulterating by the position that doped chemical contacts battery with electrode, reduce emitter and grid
The series resistance of line, to realize the effect for improving battery fill factor and battery efficiency, cupric electrical conductivity alloy layer is being kept
The use of the noble metals such as Ag is significantly reduced while lower resistivity, and a degree of alloying can effectively improve
The anti-oxidant performances such as anticorrosive of single metal, enhance the environmental stability of electrode.
According to an embodiment of the invention, the including transparent conducting oxide layer 500 with a thickness of 50-300nm.
According to an embodiment of the invention, the alloy transition layer 610 contain selected from Cu, Mo, W, Ti, Ni, Cr, Al, Mg, Ta,
At least two metals in Sn, Zn and Ag.Preferred embodiment in accordance with the present invention, alloy transition layer 610 are closed containing Ni-Cu-Sn
Gold, Ni-Cu-In alloy or Ni-Al alloy, wherein the Ni in alloy, which can be provided, forms good adhesive force, Ni-Cu- with silicon
Cu in Sn or Ni-Cu-In alloy can reduce the resistivity of alloy electrode and provide the basal layer of subsequent plating, Ni-Cu-
Sn in Sn alloy can form Ohmic contact with tin-doped indium oxide, after the annealed diffusion of group iii elements Al in Ni-Al alloy,
Can be formed with the hydrogenated amorphous silicon emitter layer of p-type it is good contact, reduce resistivity.Further, implementation according to the present invention
Example, the Sn of Cu the and 15-25 mass % of the Ni of Ni-Cu-Sn alloy mass containing 30-50 %, 35-55 mass %, Ni-Cu-In are closed
The In of Cu the and 15-25 mass % of the Ni of gold mass containing 30-50 %, 35-55 mass %, the Al of Ni-Al alloy mass containing 3-6 %
With the Ni of 94-97 mass %.Above-mentioned alloy has lower fusing point as a result, is conducive to be formed in subsequent Low Temperature Heat Treatment
Alloy electrode of good performance.
According to an embodiment of the invention, the alloy transition layer 610 can also further contain in B, P, Ga and In extremely
A kind of few element.Play the role of locally adulterating by the position that the dvielement contacts battery main body with electrode as a result, reduce
The series resistance of emitter/back surface field and grid line.
According to an embodiment of the invention, the alloy transition layer 610 with a thickness of 5-300nm.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer 620 containing Cu and selected from Mo, W, Ti, Ni, Cr, Al,
At least one of Mg, Ta, Sn, Zn and Ag metal.As a result, by selecting suitable metal and Cu to form alloy, substantially not
Influence the weatherability that electrode is significantly improved while conductivity.
According to an embodiment of the invention, the cupric electrical conductivity alloy layer 620 can also be further containing in B, P, Ga and In
At least one element.According to an embodiment of the invention, the cupric electrical conductivity alloy layer 620 with a thickness of 1-100 μm.
According to an embodiment of the invention, the copper content of the cupric electrical conductivity alloy layer 620 is by nearly 610 end of alloy transition layer to far
610 end of alloy transition layer is incremented by gradient, and the copper content at nearly 610 end of alloy transition layer is 85%-99%wt, remote alloy transition
The copper content at 610 end of layer is 99%-100%wt.
According to an embodiment of the invention, the resistivity of the metal grid lines electrode layer 600 is not more than 1.5 × 10-5Ω·cm.By
This, the anticorrosive antioxygen that metal grid lines electrode layer and including transparent conducting oxide layer form good Ohmic contact, and had
Change characteristic.
According to another aspect of the present invention, the present invention provides a kind of sides for preparing silicon heterojunction solar battery above-mentioned
Method.With reference to Fig. 3, according to an embodiment of the invention, the method for preparing solar cell above-mentioned is explained, this method
Include:
S100 provides n-type crystalline silicon substrate layer
According to an embodiment of the invention, providing n-type crystalline silicon substrate layer 100.Specifically, which is cleaned,
And suede structure is made in the upper and lower surfaces of substrate layer 100.
According to an embodiment of the invention, the type of crystal silicon is not particularly restricted in n-type crystalline silicon substrate layer, art technology
Personnel can select according to actual needs, and according to a particular embodiment of the invention, n-type crystalline silicon substrate layer 100 is N-shaped monocrystalline
Silicon substrate or N-shaped multicrystalline silicon substrate.
S200 forms the hydrogenated amorphous silicon buffer layer of lightly doped n-type
According to an embodiment of the invention, forming lightly doped n-type hydrogen in the upper and lower both side surface of n-type crystalline silicon substrate layer 100
Change amorphous silicon buffer layer 200.Specifically, according to an embodiment of the invention, to form this using chemical vapour deposition technique hydrogenated amorphous
Silicon buffer layer 200.The hydrogenated amorphous silicon buffer layer 200 of lightly doped n-type can repair the silicon thin film of deposition by introducing hydrogen atom
In dangling bonds, reduce the defects of lattice.
S300 forms the hydrogenated amorphous silicon emitter layer of heavily-doped p-type
According to an embodiment of the invention, forming heavy doping p on the surface of side lightly doped n-type hydrogenated amorphous silicon layer 200
The hydrogenated amorphous silicon emitter layer 300 of type.
S400 forms highly doped n-type amorphous silicon hydride back surface field layer
According to an embodiment of the invention, forming weight on the surface of the hydrogenated amorphous silicon buffer layer 200 of other side lightly doped n-type
Adulterate N-shaped amorphous silicon hydride back surface field layer 400.
S500 forms including transparent conducting oxide layer
According to an embodiment of the invention, non-in the hydrogenated amorphous silicon emitter layer 300 of heavily-doped p-type and highly doped n-type hydrogenation
Including transparent conducting oxide layer 500 is formed on the surface of crystal silicon back surface field layer 400.According to an embodiment of the invention, heavily-doped p-type hydrogenates
Two layers of including transparent conducting oxide layer on the surface of amorphous silicon emitter layer 300 and highly doped n-type amorphous silicon hydride back surface field layer 400
500 type can be the same or different.
According to an embodiment of the invention, hydrogenated amorphous silicon buffer layer 200, hydrogenated amorphous silicon emitter layer 300, hydrogenated amorphous
Silicon back surface field layer 400 and including transparent conducting oxide layer 500 are heavy using plasma enhanced chemical vapor sedimentation, Hot Filament Chemical Vapor
What product, microwave plasma CVD or electron cyclotron resonance chemical vapor deposition were formed.
S600 forms metal grid lines electrode layer
In including transparent conducting oxide layer 500, amorphous silicon hydride back surface field layer 400 and the hydrogenated amorphous silicon emitter of heavily-doped p-type
Metal grid lines electrode layer 600 is formed on at least one layer of surface of layer 300, wherein metal grid lines electrode layer contains alloy transition
Layer 610 and cupric electrical conductivity alloy layer 620.
According to an embodiment of the invention, alloy transition layer 610 is formed using physical vaporous deposition.According to the present invention
Preferred embodiment, alloy transition layer 610 is that physical vaporous deposition is used to be formed for evaporation deposition method and/or sputtering method
's.
According to an embodiment of the invention, cupric electrical conductivity alloy layer 620 is formed using galvanoplastic.
The method of the formation metal grid lines electrode layer in order to facilitate understanding provides a kind of formation metal grid lines electrode herein
The exemplary method of layer:
(1-a) is hydrogenated amorphous in the including transparent conducting oxide layer 500, amorphous silicon hydride back surface field layer 400 and heavily-doped p-type
Deposit alloy metal on at least one layer of surface of silicon emitter layer 300 forms alloy transition layer 610.
According to an embodiment of the invention, the alloying metal is Ni-Cu-Sn alloy or Ni-Cu-In alloy.
According to an embodiment of the invention, sedimentation is utilized to form alloy transition layer 610, wherein deposition method includes but not
It is limited to physical vaporous deposition (PVD).
(1-b) forms the mask layer 630 of predetermined pattern using photoresistance film on the surface of alloy transition layer 610.
It according to an embodiment of the invention, the material of mask layer 630 is not particularly limited, but must be electrical isolation.
According to a particular embodiment of the invention, the exposure mask with photoetching process and with grid electrode pattern is by alloy part transition
Layer is etched away with chemical reagent, forms the position of opening that alloying metal is contacted with including transparent conducting oxide layer, then pass through heat treatment
Photoresistance film is solidified, mask layer is formed.
(1-c) forms cupric electrical conductivity alloy layer 620 on the surface of alloy transition layer 610, specifically, is formed in alloy gold
Belong to the position of opening contacted with including transparent conducting oxide layer.Since mask layer is electrical isolation, pass through galvanoplastic, cupric
It is formed at the position that electrical conductivity alloy layer can only be open on the mask layer.
(1-d) removes the alloy transition layer 610 that mask layer 630 and mask layer 630 cover, and is formed in metal grid lines electrode layer
Mesosome.It should be noted that during removing alloy transition layer 610, it is inevitably conductive to established cupric
Alloy-layer generates certain corrosiveness.Since the thickness of cupric electrical conductivity alloy layer 620 is much higher than alloy transition layer 610,
The corrosiveness is comparatively slight, will not adversely affect to the performance of subsequent electrode.
(1-e) makes annealing treatment metal grid lines electrode layer intermediate, obtains metal grid lines electrode layer 600.Specifically,
The annealing is carried out in protective atmosphere.
According to an embodiment of the invention, the temperature of the annealing is 125-350 degrees Celsius, the time is 15-60 minutes.By
This, annealing it is high-efficient, effect is good.
According to an embodiment of the invention, copper content changes in gradient in metal grid lines electrode layer 600, from close to described
Including transparent conducting oxide layer side 96%-99%wt rises to the 99-100%wt at the top of metal grid lines electrode layer.
For a further understanding of the method for the formation metal grid lines electrode layer, with reference to Fig. 4, providing a kind of formation again herein should
The exemplary method of metal grid lines electrode layer 600:
(2-a) removes partially transparent conductive oxide layer 500, forms the including transparent conducting oxide layer with predetermined pattern
500, wherein the including transparent conducting oxide layer 500 is the electrically conducting transparent oxygen of the hydrogenated amorphous silicon emitter layer 300 of nearly heavily-doped p-type
Compound layer 500.And the forming method such as above-mentioned steps of the including transparent conducting oxide layer 500 close to 400 side of amorphous silicon back surface field layer
It is shown, i.e. step (1-a)-(1-e).
According to an embodiment of the invention, removing including transparent conducting oxide layer using photoetching process or wet etching.
Wherein, it should be noted that the including transparent conducting oxide layer 500 or nearly amorphous silicon hydride back surface field layer 400
Including transparent conducting oxide layer 500, i.e. alloy transition layer 610 can also be formed in amorphous silicon hydride back surface field layer 400.
(2-b) is on the surface of including transparent conducting oxide layer 500 and hydrogenated amorphous silicon emitter layer 300 with predetermined pattern
Upper deposit alloy metal forms alloy transition layer 610.
According to an embodiment of the invention, the alloying metal is Ni-Al alloy.The annealed diffusion of group iii elements Al as a result,
Afterwards, can be formed with the hydrogenated amorphous silicon emitter layer 300 of p-type it is good contact, reduce resistivity.
Mask layer 630 is formed on the surface of the alloy transition layer 610 of (2-c) above including transparent conducting oxide layer 500.
It according to an embodiment of the invention, the material of mask layer 630 is not particularly limited, but must be electrical isolation.
Cupric conduction is formed on the surface of the alloy transition layer 610 of (2-d) above hydrogenated amorphous silicon emitter layer 300 to close
Layer gold 620 forms metal grid lines electrode layer intermediate.
(2-e) removes the alloy transition layer 610 that mask layer 630 and mask layer 630 cover, to form metal grid lines electrode
Layer intermediate.Likewise, inevitably generating certain corrosion in removal to established cupric electrical conductivity alloy layer and making
With.Since the thickness of cupric electrical conductivity alloy layer is much higher than alloy transition layer, the corrosiveness is comparatively slight, will not
The performance of subsequent electrode is adversely affected.
(2-f) makes annealing treatment metal grid lines electrode layer intermediate, to obtain the metal grid lines electrode layer
600.The technique of the annealing is with (1-e), and details are not described herein.
According to an embodiment of the invention, copper content changes in gradient in metal grid lines electrode layer 600, from close to described
Including transparent conducting oxide layer side 85-95%wt rises to the 95%-100%wt at the top of metal grid lines electrode layer.
It should be noted that above two preparation metal grid lines electrode layer is all used for silicon heterogenous battery double-face electrode
Production, similar techniques route can also be used in the production of silicon heterogenous battery single-side electrode.For those skilled in the art and
Speech, can also have all diverse implementation on the basis of this technology path is it will be apparent that the present invention is without description exhausted
With limitation.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
Centainly refer to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be any
One or more embodiment or examples in can be combined in any suitable manner.
Although an embodiment of the present invention has been shown and described, it will be understood by those skilled in the art that: not
A variety of change, modification, replacement and modification can be carried out to these embodiments in the case where being detached from the principle of the present invention and objective, this
The range of invention is defined by the claims and their equivalents.
Claims (12)
1. a kind of silicon heterojunction solar battery characterized by comprising
N-type crystalline silicon substrate layer；
The hydrogenated amorphous silicon buffer layer of lightly doped n-type, the hydrogenated amorphous silicon buffer layer of lightly doped n-type are formed in the n-type crystalline silicon
In the upper and lower both side surface of substrate layer；
The hydrogenated amorphous silicon emitter layer of heavily-doped p-type, the hydrogenated amorphous silicon emitter layer of heavily-doped p-type are formed in described in side
On the surface of the hydrogenated amorphous silicon buffer layer of lightly doped n-type；
Highly doped n-type amorphous silicon hydride back surface field layer, the highly doped n-type amorphous silicon hydride back surface field layer are formed in light described in the other side
On the surface for adulterating the hydrogenated amorphous silicon buffer layer of N-shaped；
Including transparent conducting oxide layer, the including transparent conducting oxide layer are formed in the hydrogenated amorphous silicon emitter of the heavily-doped p-type
On the surface of layer and the highly doped n-type amorphous silicon hydride back surface field layer；
Metal grid lines electrode layer, the metal grid lines electrode layer include:
Alloy transition layer, it is hydrogenated amorphous that the alloy transition layer is formed in the including transparent conducting oxide layer, the highly doped n-type
On at least one layer of surface of silicon back surface field layer and the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type；
Cupric electrical conductivity alloy layer, the cupric electrical conductivity alloy layer are formed on the surface of the alloy transition layer.
2. silicon heterojunction solar battery according to claim 1, which is characterized in that the lightly doped n-type amorphous silicon hydride
The doping concentration of layer is 108-1017/cm3。
3. silicon heterojunction solar battery according to claim 1, which is characterized in that
The alloy transition layer contains at least two gold medals in Cu, Mo, W, Ti, Ni, Cr, Al, Mg, Ta, Sn, Zn and Ag
Belong to,
Optionally, the cupric electrical conductivity alloy layer is containing Cu and in Mo, W, Ti, Ni, Cr, Al, Mg, Ta, Sn, Zn and Ag
At least one metal.
4. silicon heterojunction solar battery according to claim 3, which is characterized in that the alloy transition layer further contains
Selected from least one of B, P, Ga and In element,
Optionally, the cupric electrical conductivity alloy layer further contains selected from least one of B, P, Ga and In element.
5. silicon heterojunction solar battery according to claim 1, which is characterized in that the copper of the cupric electrical conductivity alloy layer contains
Amount is incremented by by nearly alloy transition layer end to remote alloy transition layer end in gradient, and the copper at nearly alloy transition layer end
Content is 85%-99%wt, and the copper content at remote alloy transition layer end is 99%-100%wt.
6. silicon heterojunction solar battery according to claim 1, which is characterized in that the resistance of the metal grid lines electrode layer
Rate is not more than 1.5 × 10-5Ω·cm。
7. silicon heterojunction solar battery according to claim 1, which is characterized in that the thickness of the n-type crystalline silicon substrate layer
It is 50-200 μm,
Optionally, the hydrogenated amorphous silicon buffer layer of the lightly doped n-type with a thickness of 1-15nm,
Optionally, the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type with a thickness of 5-25nm,
Optionally, the highly doped n-type amorphous silicon hydride back surface field layer with a thickness of 5-25nm,
Optionally, the including transparent conducting oxide layer with a thickness of 50-300nm,
Optionally, the alloy transition layer with a thickness of 5-300nm,
Optionally, the cupric electrical conductivity alloy layer with a thickness of 1-100 μm.
8. a kind of method for preparing the described in any item silicon heterojunction solar batteries of claim 1-7 characterized by comprising
N-type crystalline silicon substrate layer is provided；
The hydrogenated amorphous silicon buffer layer of lightly doped n-type is formed in the upper and lower both side surface of the n-type crystalline silicon substrate layer；
The hydrogenated amorphous silicon emitter of heavily-doped p-type is formed on the surface of the hydrogenated amorphous silicon buffer layer of the lightly doped n-type described in side
Layer；
Highly doped n-type amorphous silicon hydride back surface field is formed on the surface of the hydrogenated amorphous silicon buffer layer of the lightly doped n-type described in the other side
Layer；
On the surface of the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type and the highly doped n-type amorphous silicon hydride back surface field layer
It is respectively formed including transparent conducting oxide layer；And
It is hydrogenated in the including transparent conducting oxide layer, the highly doped n-type amorphous silicon hydride back surface field layer and the heavily-doped p-type non-
Metal grid lines electrode layer is formed on at least one layer of surface of crystal silicon emitter layer, wherein the metal grid lines electrode layer contains
Alloy transition layer and cupric electrical conductivity alloy layer.
9. according to the method described in claim 8, it is characterized in that, the hydrogenated amorphous silicon buffer layer of the N-shaped, the heavy doping p
The hydrogenated amorphous silicon emitter layer of type and the highly doped n-type amorphous silicon hydride back surface field layer are heavy using plasma enhanced chemical vapor
Area method, hot-wire chemical gas-phase deposition, microwave plasma CVD or electron cyclotron resonance chemical vapor deposition are formed
,
Optionally, the alloy transition layer is formed using physical vaporous deposition, it is preferable that the physical vaporous deposition
For evaporation deposition method and sputtering method,
Optionally, the cupric electrical conductivity alloy layer is formed using galvanoplastic.
10. according to the method described in claim 9, it is characterized in that, the method for forming the metal grid lines electrode layer includes:
It is hydrogenated in the including transparent conducting oxide layer, the highly doped n-type amorphous silicon hydride back surface field layer and the heavily-doped p-type non-
Deposit alloy metal on at least one layer of surface of crystal silicon emitter layer, to form alloy transition layer；
The mask layer of predetermined pattern is formed on the surface of the alloy transition layer using photoresistance film；
Form the cupric electrical conductivity alloy layer on the surface of the alloy transition layer, and the cupric electrical conductivity alloy layer with it is described
Mask layer is arranged in a crossed manner；
The alloy transition layer of the mask layer and mask layer covering is removed, to form metal grid lines electrode layer intermediate；
The metal grid lines electrode layer intermediate is made annealing treatment, to obtain the metal grid lines electrode layer,
Optionally, the alloying metal is Ni-Cu-Sn alloy or Ni-Cu-In alloy.
11. according to the method described in claim 10, it is characterized in that, the including transparent conducting oxide layer is the nearly heavy doping
The transparent conductive oxide at N-shaped amorphous silicon hydride back surface field layer end or the hydrogenated amorphous silicon emitter layer end of the heavily-doped p-type
Layer.
12. according to the method described in claim 9, it is characterized in that, the method for forming the metal grid lines electrode layer includes:
The part including transparent conducting oxide layer is removed, to form the including transparent conducting oxide layer with predetermined pattern, wherein
The including transparent conducting oxide layer is the transparent conductive oxide of the nearly hydrogenated amorphous silicon emitter layer of heavily-doped p-type
Layer；
In the table of the including transparent conducting oxide layer with predetermined pattern and the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type
Deposit alloy metal on face, to form alloy transition layer；
Mask layer is formed on the surface of the alloy transition layer above the including transparent conducting oxide layer；
The cupric is formed on the surface of the alloy transition layer above the hydrogenated amorphous silicon emitter layer of the heavily-doped p-type
Electrical conductivity alloy layer, to form metal grid lines electrode layer intermediate, wherein the cupric electrical conductivity alloy layer and the mask layer are handed over
Fork setting；
The alloy transition layer of the mask layer and mask layer covering is removed, to form metal grid lines electrode layer intermediate；
The metal grid lines electrode layer intermediate is made annealing treatment, to obtain the metal grid lines electrode layer,
Optionally, the alloying metal is Ni-Al alloy.
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| CN113410328A (en) * | 2021-05-12 | 2021-09-17 | 北京工业大学 | Crystalline silicon heterojunction solar cell |
| CN114122154A (en) * | 2021-10-11 | 2022-03-01 | 中国科学院电工研究所 | Carrier selective passivation contact solar cell and preparation method thereof |
| CN114497259A (en) * | 2020-10-27 | 2022-05-13 | 一道新能源科技(衢州)有限公司 | Solar cell and preparation method thereof |
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