CN109148445A - 一种动态电阻及芯片及电路 - Google Patents
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Abstract
本发明公开了一种动态电阻及芯片及电路，所述动态电阻包括：一个N沟道耗尽型器件和一个P沟道耗尽型器件，N沟道耗尽型器件和P沟道耗尽型器件前后串联，N沟道耗尽型器件的源极与P沟道耗尽型器件的源极相连，N沟道耗尽型器件的栅极与P沟道耗尽型器件的漏极相连，P沟道耗尽型器件的栅极与N沟道耗尽型器件的漏极相连，N沟道耗尽型器件的漏极为动态电阻电流输入端，P沟道耗尽型器件的漏极为动态电阻电流输出端；具有电路损耗小，对浪涌电流完全隔离；与采用PTC热敏电阻相比较，具有响应快，电隔离更彻底，电路发热小等优点。
Description
技术领域
本发明涉及电子信息领域，具体地，涉及一种动态电阻及芯片及电路。
背景技术
在传统的过流保护电路中常采用PTC热敏电阻器，将PTC热敏串联于被保护的电路中，PTC在电路电流增大时，由于其自身消耗的功率增大，使得其自身温度上升，由此使得其电阻值迅速增大，从而形成对浪涌电流的抑制。但使用PTC器件，其自身温度上升并使电阻值增大所需要的响应时间较长，为毫秒级，在如此长的时间中，浪涌电流有可能已经对电路形成损坏，并且由于器件发热严重，为电路带来可靠性方面的风险。
另一种方式为采用耗尽型MOS器件在电路中用作限流保护，通常会在耗尽型MOS器件的源极串联一个固定电阻，如图1所示。耗尽型MOS器件的阈值电压及固定电阻阻值大小共同决定了电路最大输出电流，由于在固定电阻上所产生的电压降约等于耗尽型MOS器件的阈值电压，根据U/R＝I可以得到输出的最大电流值。此电路中，固定电阻的阻值越大，限流保护的效果越明显，但更大的电阻值会持续造成较大的电路损耗。
发明内容
为解决现有技术的不足，本发明提供一种动态电阻及芯片及电路，所述动态电阻包含了一个N沟道耗尽型器件和一个P沟道耗尽型器件，N沟道耗尽型器件和P沟道耗尽型器件前后串联，N沟道耗尽型器件的源极与P沟道耗尽型器件的源极相连，N沟道耗尽型器件的栅极与P沟道耗尽型器件的漏极相连，P沟道耗尽型器件的栅极与N沟道耗尽型器件的漏极相连。
本发明所述的动态电阻，N沟道耗尽型器件的漏极为电流输入端，P沟道耗尽型器件的漏极为电流输出端。当电流小于动态电阻的阈值电流时，动态电阻的阻值为N沟道耗尽型器件和P沟道耗尽型器件的导通电阻值之和，其值的大小与器件芯片面积有关。由于N沟道器件漏源之间的电压即为P沟道器件栅源之间的电压，其值为电流值乘以N沟道器件的导通电阻值；同时P沟道器件漏源之间的电压即为N沟道器件栅源之间的电压，其值为电流值乘以P沟道器件的导通电阻值。因此，当流过器件的电流增大时，电流值乘以导通电阻值也随之增大，当达到耗尽型器件阈值电压(关断电压)时，器件电阻值急剧增大，从而对电流进行有效抑制。
本发明所述的耗尽型器件可为MOS场效应晶体管或者结型场效应晶体管(JFET)。
本发明所述动态电阻，所包含N沟道耗尽型器件和P沟道耗尽型器件，通过半导体工艺，可集成于同一芯片内部，这将有利于简化电路。
本申请还提供了一种集成所述动态电阻的芯片，芯片最下方为N型衬底，P型外延层位于N型衬底之上；位于芯片左侧的器件为N沟道耗尽型MOS器件，N沟道耗尽型MOS器件为横向结构，在多晶硅栅极的正下方布置有通过离子注入预先形成的导电沟道；位于芯片右侧的器件为P沟道结型场效应晶体管。
本申请还提供了一种基于所述动态电阻的单向浪涌电流抑制的电路，所述电路包括：
N沟道耗尽型MOS场效应晶体管、动态电阻；N沟道耗尽型MOS场效应晶体管的栅极和动态电阻的输出端均与所述电路的输出端连接，N沟道耗尽型MOS场效应晶体管的源极与动态电阻的输入端连接，N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输入端连接。
本申请还提供了一种集成所述动态电阻的芯片，芯片最下方为N型衬底，P型外延层位于N型衬底之上；芯片上集成有2个动态电阻，其中一个动态电阻的输出端与另一个动态电阻的输入端连接。
本申请还提供了一种基于所述动态电阻的具有双向过流过压保护功能的电路，所述电路包括：
第一N沟道耗尽型MOS场效应晶体管、第二N沟道耗尽型MOS场效应晶体管、第一动态电阻、第二动态电阻；第一N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输入/输出端连接，第一N沟道耗尽型MOS场效应晶体管的栅极和第一动态电阻的一端均与第二动态电阻的一端以及第二N沟道耗尽型MOS场效应晶体管的栅极连接，第一N沟道耗尽型MOS场效应晶体管的源极与第一动态电阻的另一端连接，第二动态电阻的另一端与第二N沟道耗尽型MOS场效应晶体管的源极连接，第二N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输出/输入端连接。
本申请提供的一个或多个技术方案，至少具有如下技术效果或优点：
本发明所述的动态电阻与N沟道耗尽型MOS器件串联使用，与传统采用固定电阻相比较，具有电路损耗小，对浪涌电流完全隔离。与采用PTC热敏电阻相比较，具有响应快，电隔离更彻底，电路发热小等优点。
附图说明
此处所说明的附图用来提供对本发明实施例的进一步理解，构成本申请的一部分，并不构成对本发明实施例的限定；
图1为采用N沟道耗尽型MOS与固定电阻串联进行电流抑制的电路；
图2为本发明动态电阻电路原理图；
图3为本发明动态电阻芯片结构原理图；
图4为采用N沟道耗尽型MOS与动态电阻串联进行电流抑制的电路；
图5为双向动态电阻芯片结构原理图；
图6为双向电流抑制电路原理图。
具体实施方式
为了能够更清楚地理解本发明的上述目的、特征和优点，下面结合附图和具体实施方式对本发明进行进一步的详细描述。需要说明的是，在相互不冲突的情况下，本申请的实施例及实施例中的特征可以相互组合。
在下面的描述中阐述了很多具体细节以便于充分理解本发明，但是，本发明还可以采用其他不同于在此描述范围内的其他方式来实施，因此，本发明的保护范围并不受下面公开的具体实施例的限制。
实施例1，图2展示了单向动态电阻的电路原理，其中包含了一个N沟道耗尽型MOS器件和P沟道结型场效应晶体管(JFET)，其中N沟道耗尽型MOS器件的漏极为电流输入端，P沟道结型场效应晶体管(JFET)的漏极为电流输出端。
图3为N沟道耗尽型MOS器件和P沟道结型场效应晶体管集成于同一芯片的结构示意图。芯片最下方为N型衬底，P型外延层位于N型衬底之上。位于芯片左侧的器件为N沟道耗尽型MOS器件，器件为横向结构，在多晶硅栅极的正下方布置有通过离子注入预先形成的导电沟道。位于芯片右侧的器件为P沟道结型场效应晶体管。
图4展示了采用N沟道耗尽型MOS器件和动态电阻串联进行单向浪涌电流抑制的电路原理。当单向突然增大的电流达到动态电阻的阈值电流时，动态电阻阻值瞬间增大，以形成对电流的有效抑制。大电流经常伴随着高的电压，由于动态电阻的阻值增大后，使串联于动态电阻前端的N沟道耗尽型MOS器件处于关断状态，N沟道耗尽型MOS器件高的阻断电压可以对电路进行可压保护。
实施例2，图5展示了双向动态电阻集成于同一芯片的结构原理，其采用了2两组单向动态电阻，2组单向动态电阻背靠背相连。无论电流方向如何，均有1组器件可实时监测电流大小，当电流超过所设计的阈值时，动态电阻阻值迅速增大，以形成对电流的抑制，而另一组器件则为正向导通状态。
图6展示了在双向保护动态电阻的前后端各串联一个N沟道耗尽型MOS器件的电路，此电路对具有双向过流过压保护功能。
尽管已描述了本发明的优选实施例，但本领域内的技术人员一旦得知了基本创造性概念，则可对这些实施例作出另外的变更和修改。所以，所附权利要求意欲解释为包括优选实施例以及落入本发明范围的所有变更和修改。
显然，本领域的技术人员可以对本发明进行各种改动和变型而不脱离本发明的精神和范围。这样，倘若本发明的这些修改和变型属于本发明权利要求及其等同技术的范围之内，则本发明也意图包含这些改动和变型在内。
Claims (7)
1.一种动态电阻，其特征在于，所述动态电阻包括：
一个N沟道耗尽型器件和一个P沟道耗尽型器件，N沟道耗尽型器件和P沟道耗尽型器件前后串联，N沟道耗尽型器件的源极与P沟道耗尽型器件的源极相连，N沟道耗尽型器件的栅极与P沟道耗尽型器件的漏极相连，P沟道耗尽型器件的栅极与N沟道耗尽型器件的漏极相连，N沟道耗尽型器件的漏极为动态电阻电流输入端，P沟道耗尽型器件的漏极为动态电阻电流输出端。
2.根据权利要求1所述的动态电阻，其特征在于，耗尽型器件为MOS场效应晶体管或者结型场效应晶体管。
3.根据权利要求1所述的动态电阻，其特征在于，所述动态电阻通过半导体工艺，集成于同一芯片内部。
4.一种集成权利要求1-2中任意一个所述动态电阻的芯片，其特征在于，芯片最下方为N型衬底，P型外延层位于N型衬底之上；位于芯片左侧的器件为N沟道耗尽型MOS器件，N沟道耗尽型MOS器件为横向结构，在多晶硅栅极的正下方布置有通过离子注入预先形成的导电沟道；位于芯片右侧的器件为P沟道结型场效应晶体管。
5.一种基于权利要求1-2中任意一个所述动态电阻的单向浪涌电流抑制的电路，其特征在于，所述电路包括：
N沟道耗尽型MOS场效应晶体管、动态电阻；N沟道耗尽型MOS场效应晶体管的栅极和动态电阻的输出端均与所述电路的输出端连接，N沟道耗尽型MOS场效应晶体管的源极与动态电阻的输入端连接，N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输入端连接。
6.一种集成权利要求1-2中任意一个所述动态电阻的芯片，其特征在于，芯片最下方为N型衬底，P型外延层位于N型衬底之上；芯片上集成有2个动态电阻，其中一个动态电阻的输出端与另一个动态电阻的输入端连接。
7.一种基于权利要求1-2中任意一个所述动态电阻的具有双向过流过压保护功能的电路，其特征在于，所述电路包括：
第一N沟道耗尽型MOS场效应晶体管、第二N沟道耗尽型MOS场效应晶体管、第一动态电阻、第二动态电阻；第一N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输入/输出端连接，第一N沟道耗尽型MOS场效应晶体管的栅极和第一动态电阻的一端均与第二动态电阻的一端以及第二N沟道耗尽型MOS场效应晶体管的栅极连接，第一N沟道耗尽型MOS场效应晶体管的源极与第一动态电阻的另一端连接，第二动态电阻的另一端与第二N沟道耗尽型MOS场效应晶体管的源极连接，第二N沟道耗尽型MOS场效应晶体管的漏极与所述电路的输出/输入端连接。
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| CN117930930A (zh) * | 2024-03-20 | 2024-04-26 | 成都方舟微电子有限公司 | Ldo应用电路 |
| CN117930930B (zh) * | 2024-03-20 | 2024-05-31 | 成都方舟微电子有限公司 | Ldo应用电路 |
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| US5742463A (en) * | 1993-07-01 | 1998-04-21 | The University Of Queensland | Protection device using field effect transistors |
| US20090231773A1 (en) * | 2008-02-11 | 2009-09-17 | Morrish Andrew J | Transient blocking unit using normally-off device to detect current trip threshold |
| CN101702509A (zh) * | 2009-11-19 | 2010-05-05 | 上海长园维安微电子有限公司 | 阻断型浪涌保护器件 |
| CN102270639A (zh) * | 2010-12-17 | 2011-12-07 | 盛况 | 新型功率半导体集成器件 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN117930930A (zh) * | 2024-03-20 | 2024-04-26 | 成都方舟微电子有限公司 | Ldo应用电路 |
| CN117930930B (zh) * | 2024-03-20 | 2024-05-31 | 成都方舟微电子有限公司 | Ldo应用电路 |
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