CN109147835A - Power-supply system and semiconductor packages aggregate - Google Patents
Power-supply system and semiconductor packages aggregate Download PDFInfo
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- CN109147835A CN109147835A CN201811132440.7A CN201811132440A CN109147835A CN 109147835 A CN109147835 A CN 109147835A CN 201811132440 A CN201811132440 A CN 201811132440A CN 109147835 A CN109147835 A CN 109147835A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 130
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- 230000005611 electricity Effects 0.000 claims description 14
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- 238000005516 engineering process Methods 0.000 description 14
- 239000010410 layer Substances 0.000 description 12
- 238000005538 encapsulation Methods 0.000 description 7
- 238000000034 method Methods 0.000 description 7
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
- G11C5/147—Voltage reference generators, voltage or current regulators; Internally lowered supply levels; Compensation for voltage drops
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4074—Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
Abstract
Embodiment of the disclosure proposes a kind of power-supply system and semiconductor packages aggregate.The power-supply system includes: internal voltage generating circuit, for generating at least one builtin voltage；Wherein, at least one described builtin voltage is used to be supplied at least one semiconductor chip by power supply chip interconnection structure.
Description
Technical field
The disclosure belongs to technical field of semiconductors, in particular to a kind of power-supply system and semiconductor packages aggregate.
Background technique
Mobile consumer-elcetronics devices (for example, cellular phone, notebook computer and personal digital assistant etc.) increases
The demand to compact high-performance storage device is added.In many ways, the modern development of semiconductor storage can be considered as
The process of the data bit of maximum quantity is improved with defined service speed using the smallest possible device.In this context, art
Language " the smallest " is generally represented in " transverse direction " X/Y plane and (such as is limited by the major surfaces of printed circuit board or formwork flat
Face) in the Minimum Area that is occupied by storage device.Generally, the limitation of the transverse area allowed occupied by storage device inspires
Storage device designer is vertically integrated the data storage capacity of its device.
It should be noted that the information in the invention of above-mentioned background technology part is only used for reinforcing the reason to the background of the disclosure
Solution, therefore may include the information not constituted to the prior art known to persons of ordinary skill in the art.
Summary of the invention
An invention according to the present invention, provides a kind of power-supply system, comprising: internal voltage generating circuit, for generating
At least one builtin voltage；Wherein, at least one described builtin voltage by power supply chip interconnection structure for being supplied at least
One semiconductor chip.
In a kind of exemplary embodiment of the disclosure, the internal voltage generating circuit includes: at least one voltage tune
Device is saved, for generating at least one described builtin voltage.
In a kind of exemplary embodiment of the disclosure, at least one described voltage regulator includes the first charge pump electricity
Road, the second charge pump circuit, third charge pump circuit, the first low pressure difference linear voltage regulator, the second low pressure difference linear voltage regulator with
And third low pressure difference linear voltage regulator；Wherein, it described first is respectively used to be exported according to external voltage to third charge pump circuit
First builtin voltage, the second builtin voltage and third builtin voltage；Described first uses respectively to third low pressure difference linear voltage regulator
According to the 4th builtin voltage of external voltage output, the 5th builtin voltage and the 6th builtin voltage；Wherein, in described first
Portion's voltage is greater than the external voltage, the pole of second builtin voltage and the third builtin voltage with the external voltage
Property is opposite；4th to the 6th builtin voltage, which is respectively less than, is equal to the external voltage.
In a kind of exemplary embodiment of the disclosure, at least one described voltage regulator includes the first low pressure difference linearity
Voltage-stablizer, the first charge pump circuit, the second charge pump circuit, the second low pressure difference linear voltage regulator, third low pressure difference linearity pressure stabilizing
Device and the 4th low pressure difference linear voltage regulator；Wherein, first to fourth low pressure difference linear voltage regulator is respectively used to according to outer
The first builtin voltage of portion's voltage output, the 4th builtin voltage, the 5th builtin voltage and the 6th builtin voltage；Described the first to the second
Charge pump circuit is respectively used to export the second builtin voltage and third builtin voltage according to the external voltage；Wherein, described
One builtin voltage, the 4th to the 6th builtin voltage, which are respectively less than, is equal to the external voltage；Second builtin voltage and described
Three builtin voltages are opposite with the polarity of the external voltage.
In a kind of exemplary embodiment of the disclosure, the power-supply system further includes generating circuit from reference voltage, is used for
Generate reference voltage；Wherein, each voltage regulator is respectively used to be made according to the external voltage, the reference voltage and power supply
It can signal output first builtin voltage, second builtin voltage, the third builtin voltage, the 4th inside electricity
Pressure, the 5th builtin voltage and the 6th builtin voltage.
According to one aspect of the disclosure, a kind of semiconductor packages aggregate is provided, comprising: package substrate；Such as above-mentioned
Power-supply system described in one embodiment, the power-supply system are set on the package substrate；At least one semiconductor chip.
In a kind of exemplary embodiment of the disclosure, at least one described semiconductor chip includes multiple semiconductor cores
Piece, each semiconductor chip Electricity Functional having the same in the multiple semiconductor chip.
In a kind of exemplary embodiment of the disclosure, the semiconductor chip is storage chip.
In a kind of exemplary embodiment of the disclosure, the semiconductor chip is dram chip.
In a kind of exemplary embodiment of the disclosure, the multiple semiconductor chip is successively stacked vertically in the power supply
In system.
In a kind of exemplary embodiment of the disclosure, the power supply chip interconnection structure includes through silicon via.
In a kind of exemplary embodiment of the disclosure, the multiple semiconductor chip is respectively and directly arranged to the encapsulation
On substrate, the power-supply system is directly arranged on the package substrate.
In a kind of exemplary embodiment of the disclosure, the power supply chip interconnection structure includes plain conductor.
In a kind of exemplary embodiment of the disclosure, the multiple semiconductor chip is successively stacked vertically in the encapsulation
On substrate, the power-supply system is directly arranged on the package substrate.
In a kind of exemplary embodiment of the disclosure, the diameter of the power supply chip interconnection structure and it is described at least one
The quantity of semiconductor chip is related.
In a kind of exemplary embodiment of the disclosure, further includes: signal chip interconnection structure, for passing through the encapsulation
External control signal is input to each semiconductor chip and/or inputs or export each semiconductor chip for data-signal by substrate.
In a kind of exemplary embodiment of the disclosure, each semiconductor chip and the power-supply system share the encapsulation base
The earthing power supply that plate provides.
In a kind of exemplary embodiment of the disclosure, the package dimension of the power-supply system is less than or equal to each semiconductor core
The package dimension of piece.
Detailed description of the invention
The detailed description of the following preferred embodiment to the disclosure, the various mesh of the disclosure are considered in conjunction with the accompanying drawings
Mark, feature and advantage will become apparent.Attached drawing is only the exemplary diagram of the disclosure, is not necessarily to draw in proportion
System.In the accompanying drawings, same appended drawing reference always shows same or similar component.Wherein:
Fig. 1 is a kind of structural schematic diagram of semiconductor packages aggregate in the related technology；
Fig. 2 is the structural schematic diagram of another semiconductor packages aggregate in the related technology；
Fig. 3 is a kind of structural schematic diagram of semiconductor chip in the related technology；
Fig. 4 is the structural schematic diagram for showing a kind of semiconductor packages aggregate according to the embodiment of the present disclosure；
Fig. 5 is the structural schematic diagram for showing another semiconductor packages aggregate according to the embodiment of the present disclosure；
Fig. 6 is the structural schematic diagram for showing a kind of power-supply system according to the embodiment of the present disclosure；
Fig. 7 is the timing diagram based on power-supply system shown in Fig. 6；
Fig. 8 is the circuit diagram of the Vp charge pump circuit based on power-supply system shown in Fig. 6；
Fig. 9 is the timing diagram based on Vp charge pump circuit shown in Fig. 8；
Figure 10 is the circuit diagram that the Vpclk based on Fig. 8 is generated；
Figure 11 is the circuit diagram that the Vpclken based on Figure 10 is generated；
Figure 12 is the circuit diagram of the Vbb charge pump circuit based on power-supply system shown in Fig. 6；
Figure 13 is the circuit diagram of the Vnwl charge pump circuit based on power-supply system shown in Fig. 6；
Figure 14 is the circuit diagram of the Vcore low pressure difference linear voltage regulator based on power-supply system shown in Fig. 6；
Figure 15 is the circuit diagram of the Veq low pressure difference linear voltage regulator based on power-supply system shown in Fig. 6.
Specific embodiment
The exemplary embodiments for embodying disclosure features and advantages will describe in detail in the following description.It should be understood that this
Open can have various variations in different embodiments, all not depart from the scope of the present disclosure, and it is therein illustrate and
Attached drawing is inherently illustrative, rather than to limit the disclosure.
It in being described below the different illustrative embodiments to the disclosure, is carried out referring to attached drawing, the attached drawing is formed
A part of this disclosure, and the exemplary knot of difference of many aspects of the achievable disclosure is wherein shown by way of example
Structure, system and step.It should be understood that other specified schemes of component, structure, exemplary means, system and step can be used, and
And structural and functional modification can be carried out without departing from disclosure range.
Fig. 1 is a kind of structural schematic diagram of semiconductor packages aggregate in the related technology.
It is by multiple semiconductor chips (such as semiconductor in diagram as shown in Figure 1, one of the relevant technologies mode
Storage chip A-D) vertical stacking in the vertical Z plane relative to lateral X/Y plane, for example, A chip is at the top of B chip,
B chip is at the top of C chip, and C chip is at the top of D chip.
The semiconductor packages aggregate of stacking is a type of three-dimensional (3D) integrated circuit.That is, from other systems
It unites from the viewpoint of (such as storage control), 3D storage equipment plays global storage.Data are write to be read to grasp with data
Work is handled by 3D storage device, to be deposited in a manner of being applied generally to non-stacking (that is, single semiconductor chip) storage device
Storage writes data or takes back read data.However, 3D stores equipment can be in per unit lateral surfaces compared with non-stacking storage device
Product stores and provides a greater amount of data.
As shown in Figure 1, the semiconductor packages aggregate 100 of the semiconductor chip with multiple superposed, including package substrate
101 and semiconductor chip A-D, they are laminated on package substrate 101 by such sequence.
Each semiconductor chip has peripheral edge margin, and electrode pads 102 are arranged thereon.Pass through bonding wire (wire-bond) 103
Electrode pads (not shown) in the electrode pads 102 and package substrate 101 that make semiconductor chip A-D is interconnected.
In semiconductor packages aggregate 100 shown in Fig. 1, the width of each electrode pads 102 should at 100 μm or so or
It is bigger, to realize being reliably connected between bonding wire 103 and electrode pads 102.In addition, the spacing of each electrode pads 102 cannot
It is too small, thus 102 number of electrode pads that semiconductor core on piece is arranged is restricted.Meanwhile bonding wire 103 is increased by stacking
The occupied total horizontal area of device, and usually require insert layer between adjacent semiconductor chips in a stack, example
Such as RDL (Re-distribution Layer, redistribution layer) 104.
Here, if semiconductor chip A-D is made into DRAM (Dynamic Random Access Memory, dynamic random
Access memory) chip, then in addition to supply terminals (mains terminals) and grounding terminal, it should be connect to the biggish signal of number
Line end, as electrode pads 102 are arranged in address signal, command signal and data signal line terminals.Therefore, make to distribute to power supply line
The number of the electrode pads 102 of end and ground connection terminals is restricted.
Fig. 2 is the structural schematic diagram of another semiconductor packages aggregate in the related technology.
Three dimensional integrated circuits based on through silicon via (Through Silicon Via, TSV) pass through through silicon via for multilayer chiop
Vertical stacking is integrated, to realize the interconnected communication of chip chamber, therefore the cross in addition to being limited by the periphery of the maximum chip in stacking
To area, additional horizontal area is not needed.In addition, TSV can shorten the overall length of certain signal paths of the stacking by device
Degree, therefore help speed up service speed.Therefore, by the use of TSV or similar stacking manufacturing process, using multiple vertical
Storage (and other) equipment that the chip of stacking is realized is able to use the single collection with the relatively small lateral surfaces product area of coverage
Mass data is stored and provided at circuit.
As shown in Fig. 2, semiconductor packages aggregate 200 has the multilayer identical semiconductor chip A-D of size therebetween.It is multiple
Semiconductor chip A-D with identical size by multiple TSV 202 and electrode pads 203 come mutual lamination, to realize
The electric connection of chip chamber.Due to being not necessarily to that welding gasket is arranged for each bonding wire, so, this technology can reduce semiconductor packages
The size of aggregate.
The semiconductor packages aggregate 200 of Fig. 2 can be RAM device structure.Specifically, semiconductor packages aggregate
200 include a package substrate 201 and 4 dram chip A-D being sequentially stacked on package substrate 201.In dram chip and
In the peripheral edge margin of package substrate 201, along the Z direction from top dram chip to bottom dram chip, multiple TSV 202 are passed through
Each semiconductor chip.
Fig. 3 is a kind of structural schematic diagram of semiconductor chip in the related technology.
Fig. 3 is the schematic diagram of the single layer dram chip in semiconductor packages aggregate 200 shown in Fig. 2.DRAM core in Fig. 2
Piece A-D has port same as below or pin, for example, BA0-2 (Bank Sel), A0-15 (Address address signal),
RAS/, CAS/, WE/ (Command control signal), CLK, CLK/ (clock signal), CS/, RESET/ (reset signal), DQ [0:
15] (data-signal) and VDD, VDDQ, VSS, VSSQ, VPP external power supply signal etc., and these ports or pin with
TSV, plain conductor (metal wire) or RDL connection, and it is connected to packaging pin (package Balls, PINs).
Wherein, Bank Sel, Address, Command, CLK, RESET/ these control signals or address signal respectively
Electrical connection passes through every layer of dram chip A-D.These external power supply signals of VDD, VDDQ, VSS, VSSQ, VPP are respectively electrically connected connection
Cross every layer of dram chip A-D.
DRAM memory cell array 301 includes that a large amount of individual storages with the matrix correlation of row and column signal wire arrangement are single
Member.Each storage unit, which is able to respond to store in write order, writes data, and in response to for example depositing from external device (ED) (not shown)
It stores up controller or the received read command of processor and reading data is provided.Read/write command cause certain control signals (such as row ground
Location, column address, enable signal etc.) generation, these control signals together with certain control voltages pass through relevant peripheral equipment
It sets (such as row decoder 302 and column decoder 303) and is applied to memory cell array 301.
During write operation, data (that is, being intended for storage in the data in memory cell array 301) are write from external circuit
(such as external memory, external input device, processor, storage control, storage switch etc.) is transmitted to data register.One
Denier is stored in data register, and memory cell array 301 can be written to by conventional structure and technology by writing data, conventional to tie
Structure and technology may include such as sensing amplifier and write driver circuit.
During read operation, the control signal of the control voltage and row decoder 302 and column decoder 303 that are applied is defeated
Usually cooperation is out to identify and select one or more storage units in memory cell array 301, and facilitates offer for referring to
Show the signal of the value for the data being stored in a storage unit." the reading data " generated is general to be transmitted by reading sensing amplifier to deposit
Storage is in data register.The reading data being stored in data register then can be provided under the control for reading control circuit
External circuit.
As shown in figure 3, every layer of dram chip includes all DRAM operation interrelated logic blocks in Fig. 2, such as Writing/Reading control is patrolled
It collects, refresh control and internal electric source (such as Vp, Vbb, Vnwl, Vcore, Veq, Vplt etc.), these internal electric sources are needed by phase
The charge pump circuit or voltage regulator answered are adjusted to obtain correct voltage level.
Each layer dram chip in semiconductor packages aggregate shown in Fig. 2 200 respectively includes respective charge pump (Charge
Pump) circuit and voltage regulator (voltage regulator), i.e. dram chip A-D internal electric source supply having the same
Circuit, since dram chip is needed using nanoscale high-order processing procedure, and power supply chip (Power IC) generally only needs to use
Micron-sized low order processing procedure, upper 1000 times of processing procedure difference between the two, if power supply chip is integrated in dram chip, by
It is not suitable for power supply chip in dram chip manufacturing process, the efficiency that will lead to power supply chip reduces, such as from common 90%
Efficiency drops to 60% or so.In addition, power supply chip is integrated in dram chip, chip area can be occupied, improves DRAM core
The cost of piece.Meanwhile dram chip making technology is expensive, and power supply making technology is cheap.
Fig. 4 is the structural schematic diagram for showing a kind of semiconductor packages aggregate according to the embodiment of the present disclosure.
As shown in figure 4, embodiment of the present invention provides a kind of semiconductor packages aggregate 400, semiconductor packages set
Body 400 may include: package substrate 401；Power-supply system 402, power-supply system 402 can be set on the package substrate 401；
At least one semiconductor chip, here by taking four semiconductor chip A-D as an example, but it's not limited to that for the disclosure, can basis
Specific demand is adjusted correspondingly.
In the exemplary embodiment, at least one described semiconductor chip may include multiple semiconductor chips, described more
Each semiconductor chip Electricity Functional having the same in a semiconductor chip.
In the exemplary embodiment, the semiconductor chip can be storage chip.
In the exemplary embodiment, the semiconductor chip can be dram chip.But the disclosure is not construed as limiting this, institute
Stating semiconductor chip can be any type of chip.
In the embodiment shown in fig. 4, the multiple semiconductor chip can successively be stacked vertically in the power-supply system 402
On.For example, dram chip A is stacked vertically on dram chip B, dram chip B is stacked vertically on dram chip C,
Dram chip C is stacked vertically on dram chip D.
In the embodiment shown in fig. 4, power-supply system 402 can by TSV 403 as power supply chip interconnection structure by its
Each builtin voltage of output is separately input into each semiconductor chip.
It should be noted that, although illustrating only multiple semiconductor chips in Fig. 4 is successively stacked vertically in the power supply system
Embodiment on system, but in other embodiments, the multiple semiconductor chip can also be respectively and directly arranged to the encapsulation
On substrate 401, i.e., each semiconductor chip is adjacent to being arranged in (side-by- in 401 transverse plane of package substrate each other
Side arrangement mode), the power-supply system is also directly arranged on the package substrate 401.In further embodiments, described
Multiple semiconductor chips can also successively vertical stacking be set on the package substrate 401, and the power-supply system can also be straight
It connects and is set on the package substrate 401.
In each semiconductor chip adjacent to being arranged in the arrangement mode in 401 transverse plane of package substrate each other,
Power-supply system 402 can be separately input by each builtin voltage that plain conductor is output it as power supply chip interconnection structure
In each semiconductor chip.
Fig. 5 is the structural schematic diagram for showing another semiconductor packages aggregate according to the embodiment of the present disclosure.
It is inputted as shown in figure 5, at least one builtin voltage that power-supply system 402 exports passes through corresponding TSV 403 respectively
To each layer dram chip A-D.Shown in Fig. 5 three arrows for for example, be not used to limit power-supply system 402 it is defeated
The quantity of builtin voltage out.
In the exemplary embodiment, the diameter of the power supply chip interconnection structure and at least one semiconductor chip
Quantity is related.For example, the semiconductor chip number of plies stacked in power-supply system 402 is more, then the diameter of corresponding TSV 403 is got over
Greatly, this is because when transmitting a signal to the more semiconductor chip on upper layer by TSV 403, the pressure drop generated is bigger, at this point,
Pressure drop can be reduced by increasing the quantity of the diameter of TSV 403 or the TSV 403 of parallel connection, so that each layer semiconductor
The value that chip receives the same builtin voltage is roughly equal.
In the embodiment shown in fig. 5, the diameter of each TSV 403 is for example about 20 μm, and is arranged by about 50 μm of spacing, this
It is enough to prevent the short trouble between adjacent TSV.But, as the possibility of production TSV technology develops, these diameters be can reduce
And spacing.
With continued reference to Fig. 5, which can also include: signal chip interconnection structure 404, wherein described
Signal chip interconnection structure 404 can be used for by the package substrate 401 by external control signal (such as Address,
The signals such as Command) it is input to each semiconductor chip and/or data-signal (such as DQ [0-15]) is inputted or exported fifty-fifty
Conductor chip.In the embodiment of the present invention, signal chip interconnection structure 404 can also use TSV.
In the embodiment shown in fig. 5, each semiconductor chip A-D and the power-supply system 402 can share the encapsulation base
The earthing power supply (not shown) that plate 401 provides.
In the exemplary embodiment, the package dimension of the power-supply system can be less than or equal to the encapsulation of each semiconductor chip
Size.
For example, in the embodiment shown in figs. 4 and 5, the package dimension of the power-supply system 402 is less than each semiconductor chip
The package dimension of A-D.
Fig. 6 is the structural schematic diagram for showing a kind of power-supply system according to the embodiment of the present disclosure.
As shown in fig. 6, embodiment of the present invention provides a kind of power-supply system 600, the power-supply system 600 be can wrap
Include: internal voltage generating circuit 610, the internal voltage generating circuit 610 can be used for generating at least one builtin voltage；Its
In, at least one described builtin voltage be used for by power supply chip interconnection structure (such as TSV or wire-bond) be supplied to
A few semiconductor chip (such as the dram chip in above-described embodiment, but the present invention is not limited to this).
In the exemplary embodiment, the internal voltage generating circuit 610 may include: at least one voltage regulator,
For generating at least one described builtin voltage.
In the exemplary embodiment, at least one described voltage regulator may include the first charge pump circuit, the second electricity
Lotus pump circuit, third charge pump circuit, the first low pressure difference linear voltage regulator, the second low pressure difference linear voltage regulator and third low pressure
Difference linear constant voltage regulator；Wherein, it described first is respectively used to export the first inside electricity according to external voltage to third charge pump circuit
Pressure, the second builtin voltage and third builtin voltage；Described first is respectively used to according to third low pressure difference linear voltage regulator
External voltage exports the 4th builtin voltage, the 5th builtin voltage and the 6th builtin voltage；Wherein, first builtin voltage is greater than
The external voltage, second builtin voltage and the third builtin voltage are opposite with the polarity of the external voltage；Institute
It states the 4th to the 6th builtin voltage and is respectively less than and be equal to the external voltage.
In the embodiment of the present disclosure, low pressure difference linear voltage regulator (Low Dropout Regulator, LDO), using in its line
Property region in run transistor or field-effect tube (Field Effect Transistor, FET), from the input voltage of application
In subtract the voltage of excess, generate the output voltage through overregulating.The cost of LDO linear voltage regulator is low, low noise, quiescent current
Small, these are its outstanding advantages.The outward element that it is needed is also seldom, usually only needs one or two of shunt capacitance.If defeated
Enter voltage and output voltage very close to selection LDO can reach very high efficiency, and the input current of LDO is substantially equal to export
Electric current, if pressure drop is too big, consumption energy on LDO is too big, inefficient.It in other embodiments, can also be according to reality
Situation is using the LDO in the DC-DC converter replacement embodiment of the present disclosure.
In the embodiment shown in fig. 6, by taking the semiconductor chip is dram chip as an example, and assume that each layer dram chip is equal
This six builtin voltages of Vp, Vbb, Vnwl, Vcore, Vplt, Veq are needed, then at least one described voltage regulator can be at this time
Including the first charge pump circuit 611, the second charge pump circuit 612, third charge pump circuit 613, the first low pressure difference linearity pressure stabilizing
Device 614, the second low pressure difference linear voltage regulator 615 and third low pressure difference linear voltage regulator 616.Wherein, the first charge pump circuit
611 can be used for exporting the first builtin voltage Vp according to external voltage Vext.Second charge pump circuit 612 can be used for according to outer
Portion voltage Vext exports the second builtin voltage Vbb.Third charge pump circuit 613 can be used for exporting the according to external voltage Vext
Three builtin voltage Vnwl.First low pressure difference linear voltage regulator 614 can be used for exporting the 4th inside electricity according to external voltage Vext
Press Vcore.Second low pressure difference linear voltage regulator 615 can be used for exporting the 5th builtin voltage Vplt according to external voltage Vext.
Third low pressure difference linear voltage regulator 616 can be used for exporting the 6th builtin voltage Veq according to external voltage Vext.
In the embodiment of the present invention, the first builtin voltage Vp is greater than the external voltage Vext, second inside electricity
Press the Vbb and third builtin voltage Vnwl with the polarity of the external voltage Vext on the contrary, such as Vext=1.2V, Vp=
3.0V, Vbb=-0.5V, Vnwl=-0.3V, the above voltage value be only used for for example, the disclosure it's not limited to that.
It should be noted that the inversion device in corresponding charge pump can when input voltage is opposite with the polarity of output voltage
To convert the positive voltage of input to the negative voltage of output.
In the embodiment of the present invention, the 4th builtin voltage Vcore, the 5th builtin voltage Vplt, the 6th builtin voltage Veq
Respectively less than it is equal to the external voltage Vext, such as Vext=1.2V, Vcore=1.0V, Vplt=Veq=0.5V, but this public affairs
Open that it's not limited to that.
In the exemplary embodiment, at least one described voltage regulator includes the first low pressure difference linear voltage regulator, first
Charge pump circuit, the second charge pump circuit, the second low pressure difference linear voltage regulator, third low pressure difference linear voltage regulator and the 4th are low
Pressure difference linear voltage regulator；Wherein, first to fourth low pressure difference linear voltage regulator is respectively used to export the according to external voltage
One builtin voltage, the 4th builtin voltage, the 5th builtin voltage and the 6th builtin voltage；The first to the second charge pump circuit point
The second builtin voltage and third builtin voltage Yong Yu not be exported according to the external voltage；Wherein, first builtin voltage,
Four to the 6th builtin voltages, which are respectively less than, is equal to the external voltage；Second builtin voltage and the third builtin voltage with
The polarity of the external voltage is opposite.
Or by taking Fig. 6 as an example, it is assumed that each layer semiconductor chip be required to Vp, Vbb, Vnwl, Vcore, Vplt, Veq this six
A builtin voltage, then at least one described voltage regulator may include first the 611, first electricity of low pressure difference linear voltage regulator at this time
Lotus pump circuit 612, the second charge pump circuit 613, the second low pressure difference linear voltage regulator 614, third low pressure difference linear voltage regulator 615
And the 4th low pressure difference linear voltage regulator 616.Wherein, the first low pressure difference linear voltage regulator 611 can be used for according to external voltage
Vext exports the first builtin voltage Vp.First charge pump circuit 612 can be used for being exported inside second according to external voltage Vext
Voltage Vbb.Second charge pump circuit 613 can be used for exporting third builtin voltage Vnwl according to external voltage Vext.Second is low
Pressure difference linear voltage regulator 614 can be used for exporting the 4th builtin voltage Vcore according to external voltage Vext.Third low pressure difference linearity
Voltage-stablizer 615 can be used for exporting the 5th builtin voltage Vplt according to external voltage Vext.4th low pressure difference linear voltage regulator 616
It can be used for exporting the 6th builtin voltage Veq according to external voltage Vext.
In the embodiment of the present disclosure, the first builtin voltage Vp, the 4th builtin voltage Vcore, the 5th builtin voltage Vplt
And the 6th builtin voltage Veq can be less than or equal to the external voltage Vext, such as Vext > 3.3V, Vp=3.0V,
Vcore=1.0V, Vplt=Veq=0.5V；The second builtin voltage Vbb and third builtin voltage Vnwl with it is described
The polarity of external voltage Vext is on the contrary, such as Vext > 3.3V, Vbb=-0.5V, Vnwl=-0.3V.
With continued reference to Fig. 6, the power-supply system 600 can also include generating circuit from reference voltage 620, and reference voltage generates
Circuit 620 can be used for generating reference voltage Vref.
In the embodiment shown in fig. 6, each voltage regulator may be respectively used for according to the external voltage Vext, the ginseng
It examines voltage Vref and power supply enable signal EN and exports the first builtin voltage Vp, the second builtin voltage Vbb, described the
Three builtin voltage Vnwl, the 4th builtin voltage Vcore, the 5th builtin voltage Vplt and the 6th builtin voltage
Veq。
In the embodiment shown in fig. 6, the semiconductor packages aggregate including the power-supply system 600 can also include signal
Chip interconnection structure 700, wherein the signal chip interconnection structure 700 can be used for through the semiconductor packages aggregate
Package substrate (not shown) is by external control signal (such as external power supply VDD/VDDQ, VSS/VSSQ, address signal
Address, Bank Sel, control signal Command, clock signal clk or/CLK etc.) be input to each semiconductor chip and/
Or data-signal (such as DQ [0-15]) is inputted or is exported each semiconductor chip.In the embodiment of the present invention, signal chip is mutual
Connection structure 700 can also use TSV.
It should be noted that embodiment illustrated in fig. 6 is with the semiconductor chip in semiconductor packages aggregate for DRAM core
It is illustrated for piece, in other embodiments, if the semiconductor chip in semiconductor packages aggregate is other kinds of
Chip, the then quantity and type for the builtin voltage that corresponding internal voltage generating circuit generates can also occur to change accordingly,
Similar, the external control signal and/or data-signal that signal chip interconnection structure provides can also occur to change accordingly.
Fig. 7 is the timing diagram based on power-supply system shown in Fig. 6.
As shown in fig. 7, when external voltage Vext is high level (it is assumed that Vext be VDD for be illustrated), after
The continuous high level for waiting power supply enable signal EN arrives, and when VDD and EN is high level, internal voltage generating circuit starts work
Make, after certain delay, internal voltage generating circuit export respectively the described first to the 6th builtin voltage Vp, Vbb,
Vnwl、Vcore、Vplt、Veq。
The power-supply system and semiconductor packages aggregate that embodiment of the present invention provides, by by a unified power supply system
System is builtin voltage needed for multiple semiconductor chips in the semiconductor packages aggregate provide each semiconductor chip simultaneously, should
Power-supply system does not need to be integrated within any semiconductor chip, so as to realize semiconductor chip using high-order processing procedure system
Make, and power-supply system is made of low order processing procedure, so on the one hand due to improving power supply system using the production respectively to match
The efficiency of system；On the other hand, power-supply system will not occupy the chip area of DRAN chip interior, reduce dram chip at
This.
Fig. 8 is the circuit diagram of the Vp charge pump circuit based on power-supply system shown in Fig. 6.Fig. 9 is based on Vp electricity shown in Fig. 8
The timing diagram of lotus pump circuit.Figure 10 is the circuit diagram that the Vpclk based on Fig. 8 is generated.Figure 11 is that the Vpclken based on Figure 10 is generated
Circuit diagram.
As shown in Figure 10, reference voltage Vref is supplied shortly after in VDD, reaches high level, peripheral control unit is by EN signal
It is enabled, make the charge pump circuit functions of Fig. 8, pumping gradually rises Vp voltage.In Fig. 9, after Vp reaches target voltage,
Vpclk signal stops, and the charge pump circuit of Fig. 8 is caused to stop working.If Vp is lower than target voltage, Vpclk starts to generate, cause
The charge pump circuit of Fig. 8 starts to work (pump).
Figure 10 is Vpclk generation circuit, when wherein Vpclken is high level, starts to generate Vpclk；Vpclken is low electricity
Usually, Vpclk stops generating.Figure 11 is the generation circuit of Vpclken, and divider resistance R1 and R2 therein can be according to specifically answering
It is designed with scene.
Figure 12 is the circuit diagram of the Vbb charge pump circuit based on power-supply system shown in Fig. 6.Figure 13 is based on electricity shown in Fig. 6
The circuit diagram of the Vnwl charge pump circuit of source system.
The principle of Figure 12 and Figure 13 is substantially similar with Figure 11, and details are not described herein.
Figure 14 is the circuit diagram of the Vcore low pressure difference linear voltage regulator based on power-supply system shown in Fig. 6.Figure 15 is based on figure
The circuit diagram of the Veq low pressure difference linear voltage regulator of power-supply system shown in 6.
It is illustrated by taking Figure 14 as an example, which can use OP amplifier (operational
Amplifier, operational amplifier), normal phase input end connects the voltage value after Vext partial pressure, can be according to concrete application scene tune
The Vext of the value of whole R3 and R4, the Vcore after inverting input terminal input feedback, the third input terminal connection of OP amplifier is used for
Amplify rectified action.
It should be noted that the resistance value of R3 and R4 may be the same or different.Similar, the divider resistance in Figure 15
The resistance value of R5 and R6 may be the same or different.
Be described in detail above and/or illustrate the disclosure proposition power-supply system and semiconductor packages set it is exemplary
Embodiment.But embodiment of the present disclosure is not limited to particular implementation as described herein, on the contrary, each embodiment
Component part and/or step can be independent with other component parts as described herein and/or step and be used separately.One implementation
Each component part of mode and/or each step can also be in conjunction with the other component parts and/or step of other embodiment
It uses.When introducing described here and/or diagram element/component part/wait, term "one", " one " and " above-mentioned " etc.
To indicate there are one or more elements/component part/etc..Term "comprising", " comprising " and " having " are to indicate open
Formula be included the meaning and refer to that other element/group also may be present in the element/component part/in addition to listing other than waiting
At part/etc..In addition, the term " first " and " second " etc. in claims and specification are only used as label, it is not
To the numerical limit of its object.
Although the spacer material production method that the disclosure proposes is described according to different specific embodiments, this
Field technical staff, which will recognize that, to be in the spirit and scope of the claims modified the implementation of the disclosure.
Claims (18)
1. a kind of power-supply system characterized by comprising
Internal voltage generating circuit, for generating at least one builtin voltage；
Wherein, at least one described builtin voltage is used to be supplied at least one semiconductor core by power supply chip interconnection structure
Piece.
2. power-supply system according to claim 1, which is characterized in that the internal voltage generating circuit includes:
At least one voltage regulator, for generating at least one described builtin voltage.
3. power-supply system according to claim 2, which is characterized in that at least one described voltage regulator includes the first electricity
Lotus pump circuit, the second charge pump circuit, third charge pump circuit, the first low pressure difference linear voltage regulator, the second low pressure difference linearity are steady
Depressor and third low pressure difference linear voltage regulator；Wherein,
Described first is respectively used to export the first builtin voltage, the second builtin voltage according to external voltage to third charge pump circuit
With third builtin voltage；
Described first is respectively used to export the 4th builtin voltage, the according to the external voltage to third low pressure difference linear voltage regulator
Five builtin voltages and the 6th builtin voltage；
Wherein, first builtin voltage is greater than the external voltage, second builtin voltage and the third builtin voltage
It is opposite with the polarity of the external voltage；4th to the 6th builtin voltage, which is respectively less than, is equal to the external voltage.
4. power-supply system according to claim 2, which is characterized in that at least one described voltage regulator includes first low
Pressure difference linear voltage regulator, the first charge pump circuit, the second charge pump circuit, the second low pressure difference linear voltage regulator, third low voltage difference
Linear voltage regulator and the 4th low pressure difference linear voltage regulator；Wherein,
First to fourth low pressure difference linear voltage regulator is respectively used to according in the first builtin voltage of external voltage output, the 4th
Portion's voltage, the 5th builtin voltage and the 6th builtin voltage；
The first to the second charge pump circuit is respectively used to be exported in the second builtin voltage and third according to the external voltage
Portion's voltage；
Wherein, first builtin voltage, the 4th to the 6th builtin voltage, which are respectively less than, is equal to the external voltage；In described second
Portion's voltage and the third builtin voltage are opposite with the polarity of the external voltage.
5. power-supply system according to claim 3 or 4, which is characterized in that further include:
Generating circuit from reference voltage, for generating reference voltage；
Wherein, each voltage regulator is respectively used to defeated according to the external voltage, the reference voltage and power supply enable signal
First builtin voltage, second builtin voltage, the third builtin voltage, the 4th builtin voltage, described out
Five builtin voltages and the 6th builtin voltage.
6. a kind of semiconductor packages aggregate characterized by comprising
Package substrate；
Such as power-supply system described in any one of claim 1 to 5, the power-supply system is set on the package substrate；
At least one semiconductor chip.
7. semiconductor packages aggregate according to claim 6, which is characterized in that at least one described semiconductor chip packet
Multiple semiconductor chips are included, each semiconductor chip Electricity Functional having the same in the multiple semiconductor chip.
8. semiconductor packages aggregate according to claim 7, which is characterized in that the semiconductor chip is storage core
Piece.
9. semiconductor packages aggregate according to claim 8, which is characterized in that the semiconductor chip is DRAM core
Piece.
10. semiconductor packages aggregate according to claim 7, which is characterized in that the multiple semiconductor chip is successively
It is stacked vertically in the power-supply system.
11. semiconductor packages aggregate according to claim 10, which is characterized in that the power supply chip interconnection structure packet
Include through silicon via.
12. semiconductor packages aggregate according to claim 7, which is characterized in that the multiple semiconductor chip difference
It is directly arranged on the package substrate, the power-supply system is directly arranged on the package substrate.
13. semiconductor packages aggregate according to claim 12, which is characterized in that the power supply chip interconnection structure packet
Include plain conductor.
14. semiconductor packages aggregate according to claim 7, which is characterized in that the multiple semiconductor chip is successively
It is stacked vertically on the package substrate, the power-supply system is directly arranged on the package substrate.
15. semiconductor packages aggregate according to claim 6, which is characterized in that the power supply chip interconnection structure
Diameter is related to the quantity of at least one semiconductor chip.
16. semiconductor packages aggregate according to claim 6, which is characterized in that further include:
Signal chip interconnection structure, for by the package substrate by external control signal be input to each semiconductor chip and/
Or data-signal is inputted or is exported each semiconductor chip.
17. semiconductor packages aggregate according to claim 6, which is characterized in that each semiconductor chip and the power supply
System shares the earthing power supply that the package substrate provides.
18. semiconductor packages aggregate according to claim 6, which is characterized in that the package dimension of the power-supply system
Less than or equal to the package dimension of each semiconductor chip.
Priority Applications (3)
| Application Number | Priority Date | Filing Date | Title |
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| CN201811132440.7A CN109147835B (en) | 2018-09-27 | 2018-09-27 | Power supply system and semiconductor package assembly |
| PCT/CN2019/108429 WO2020063827A1 (en) | 2018-09-27 | 2019-09-27 | Power supply system and semiconductor package assembly |
| US17/211,550 US11482272B2 (en) | 2018-09-27 | 2021-03-24 | Power supply system and semiconductor package assembly |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201811132440.7A CN109147835B (en) | 2018-09-27 | 2018-09-27 | Power supply system and semiconductor package assembly |
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| CN109147835A true CN109147835A (en) | 2019-01-04 |
| CN109147835B CN109147835B (en) | 2024-02-09 |
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| WO2020063720A1 (en) * | 2018-09-27 | 2020-04-02 | Changxin Memory Technologies, Inc. | Power supply system and semiconductor package assembly |
| WO2020063827A1 (en) * | 2018-09-27 | 2020-04-02 | Changxin Memory Technologies, Inc. | Power supply system and semiconductor package assembly |
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| WO2020063827A1 (en) * | 2018-09-27 | 2020-04-02 | Changxin Memory Technologies, Inc. | Power supply system and semiconductor package assembly |
| US11482272B2 (en) | 2018-09-27 | 2022-10-25 | Changxin Memory Technologies, Inc. | Power supply system and semiconductor package assembly |
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| CN109147835B (en) | 2024-02-09 |
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