CN109145324A - A kind of parameterized module unit of transistors - Google Patents

Abstract

The present invention provides small size matching transistor parameterized module units to improve the stability of domain to improve the efficiency for drawing domain, wherein the small size matching transistor modular unit with parameter, is made of the transistor of two fixed matching connection relationships.

Description

A kind of parameterized module unit of transistors

Technical field

The present invention relates to after integrated circuit and power device field more particularly to Analogous Integrated Electronic Circuits and power device design End.

Background technique

IC design includes Front-end Design and two stages are designed in rear end, and Front-end Design is responsible for logic realization, usually It is the speech like sound using verilog/VHDL, carries out the description of behavioral scaling.Rear end design refers to the gate leve for generating Front-end Design Netlist is laid out wiring by EDA design tool and carries out physical verification and finally generate the mistake of the GDS file for manufacture Journey, main responsibility have: chip makes physical structural analysis, logic analysis, establish rear end design cycle, laying out pattern wiring, Layout editing, gets in touch with fab and submits creation data domain physical verification.So-called GDS file is a kind of patterned text Part is a kind of format of integrated circuit diagram.

With the increase increasingly of mixed-signal designs complexity, development technology design tool packet (PDK, Process Design Kit) and to establish verifying reference flowchart be extremely important for reducing the market risk brought by expensive design repeatedly 's.In general, fab can customize the design component of PDK according to the requirement of technology, and each technique can have a set of right The PDK answered.

PDK is the complete process file set that provides for analog/mixed signal IC circuit design, be connection IC design and The data platform of IC technique manufacture.The content of PDK includes:

Device model (Device Model): the simulation model file provided by Foundry；

Symbol and view (Symbols & View): for the symbol of principle diagram design, the design cell of parametrization all passes through The verifying of SPICE emulation；

Component descriptor format (CDF, Component Description Format) and Callback function: the attribute of device is retouched State file, define type of device, device name, device parameters and parameter call relation collection of functions Callback, device model, Various view formats of device etc.；

Parameterized units (Pcell, Parameterized Cell): it is write by the SKILL language of Cadence, corresponding Domain has passed through design rule check (DRC, design rule check) and domain and circuit diagram (LVS) is verified, and facilitates design Domain (Schematic Driven Layout) design cycle of personnel's progress schematic diagram driving；

Technological document (Technology File): for the technical papers of layout design and verifying, the design number comprising GDSII It is defined according to the mapping relations of layer and process layer, the attribute definition of design data layer, Photographing On-line rule, electric rule, display color Coloured silk definition and graphical format definition etc.；

Physical verification rule (PV Rule) file: it is extracted comprising layout verification file DRC/LVS/RC, supports Cadence's Diva, Dracula, Assura etc..

What wherein the parameter in parameterized units (Pcell) referred to is exactly CDF parameter, and it is fixed that their combination can be realized user The institute of system is functional, is the core of PDK.In fact, the library of PDK just refers to the intersection of all parameterized units.It is specific next It says, parameterized units have following effect:

(1) data for being inserted into domain can be accelerated, avoid the repetition creation of unit；

(2) space of physical disk is saved, similar portion may be connected to identical resource；

(3) mistake occurred because to safeguard multiple versions of same unit is avoided；

(4) editting function for realizing level does not need to go to change hierarchical structure to change the design of domain.

In short, if having the PDK, IC of the optimization sets such as parameterized units structure, symbol and the rule by verifying The work of designer can free from the task of cumbersome fallibility and become high quality and rich in efficiency.

In traditional territory unit library, mos transistor basic unit is only existed, layout drawing personnel are drawing matching MOS When transistor, two mos transistors with parameter are first called, then confirm the mos transistor come further according to circuit simulation Dimensional parameters carry out parameter setting to the territory unit of each mos transistor, are attached then according to matched principle and cloth Office, the later period modification during, if mos transistor size is varied, change operation it is very cumbersome, and be easy without Mistake occurs in meaning.

Summary of the invention

The present invention provides small size matching transistor parameterized module units to be improved with improving the efficiency for drawing domain The stability of domain.

Small size matching transistor parameterized module unit provided by the invention, by the crystalline substance of two fixed matching connection relationships Body pipe composition.The modular unit provides control two parameters of transistor grid length and grid width, modifies two parameters, can be with The size of transistor is adjusted, inside will make automatically corresponding adjustment, still maintain matching connection relationship.

Optionally, six metal lines are drawn in the modular unit, is connected for modular unit external circuit.

Optionally, the grid area that can adjust the transistor at any time allows area, Optimized Matching essence according to practical domain Exactness.

Optionally, the modular unit uses complete common centroid domain structure.

Optionally, described transistor the right and left adds equidistant setoff grid, avoids because of polysilicon etch rate Mismatch caused by inconsistent.

Optionally, the gate electrode for serving as a contrast or foil pipe is connected in the modular unit with backgate, helps to ensure that the electricity of transistor Learn characteristic is not influenced by the pseudo- channel formed below setoff pipe.

Optionally, do not have to polysilicon in the modular unit and multiple gate electrodes are connected with each other with metal, prevent Adjacent domain causes etch rate to change there are polysilicon graphics.

Optionally, the modular unit correctly handles the position of contact hole on polygate electrodes.

Optionally, the modular unit has close to symmetrical metal connecting line and is laid out.

Detailed description of the invention

Fig. 1 is preferred embodiment of the present invention small-medium size matching transistor parameterized module cellular construction schematic diagram.

Specific embodiment

The increase of gate area helps to reduce local irregularities' influence, improves matching accuracy.And because channel becomes The long influence for reducing channel-length modulation, so long channel MOSFET matches more accurate than short-channel transistor.This It is a have parameter, can with the changed domain modular unit of parameter, can guarantee breadth length ratio it is certain in the case where, at any time The grid area for adjusting it, according to chip area at any time by grid rea adjusting to most suitable size, so that obtaining in a practical situation Obtain best matching effect.

It can reduce the mismatch as caused by gradient by reducing the distance between matching transistor mass center.Common centroid domain cloth Office is closer, is just less susceptible to the influence by nonlinear gradient.Fig. 1 is the preferred embodiment of the invention, wherein MOS domain mass center Alignment and compact layout completely.The active grid region of MOS transistor uses long narrow rectangular in form, is divided into several sections, so as to Construct a compact array.Properly staggeredly these are interdigital for the module, match in the mass center and array symmetry axis of device The alignment of heart point.

The etch rate of polysilicon is not always consistent.The aperture of polysilicon is bigger, and etch rate is faster, because of etching Ion can more freely enter side wall and the bottom of large opening, therefore when small aperture has just been carved, the edge of large opening is deposited In a degree of over etching.This effect makes the grid length of Silicon-gate MOS transistor change.It must reach medium or smart Otherwise the transistor of true currents match should may cause 1% or bigger electric current using setoff grid to ensure uniformly to etch Mismatch.In the module be added setoff grid, and ensure that setoff grid between actual gate at a distance from be equal to actual gate it Between distance, avoid because polysilicon etch rate it is inconsistent caused by mismatch.

The gate electrode for serving as a contrast or foil pipe is connected by the modular unit with backgate, help to ensure that the electrology characteristic of transistor not by Serving as a contrast or foil the pseudo- channel formed below pipe influences.Some designers connect setoff pipe with neighbouring gate electrode, but do so and can make Capacitor and leakage current is held to increase, so not using this method.

Many designers are connected with each other multiple gate electrodes with a polysilicon, form pectination grid structure.This is undoubtedly It is that very easily, but since adjacent domain is there are polysilicon graphics, this way may make etch rate change.For Reach best match effect, the modular unit connects simple rectangle polysilicon strip using metal.It is used without polysilicon Metal is connected with each other multiple gate electrodes, prevents adjacent domain from causing etch rate to become there are polysilicon graphics Change.

Contact hole site on MOS transistor active gate can cause significant threshold voltage mismatch.For this effect, The possible explanation of one kind is due to there is metal above active gate.The alternatively possible mechanism that contact induces is contact part Silication.If the polysilicon gate formed in technique is sufficiently thin, some silicides may complete penetration polysilicon gate.Aoxidize stratum boundary The silicide occurred at face can greatly change the work function of gate electrode near contact hole, and make total threshold voltage mismatch.If Stress form changes in crystallite dimension, impurity, then there may be the mismatches induced by contact.It is correctly handled in the module The position of contact hole on polygate electrodes guarantees the top for making to contact thick field oxide layer, it can not substantially change crystal at this time The property of pipe.

Reducing annealing is used for a long time to stablize the threshold voltage of MOS transistor in Designer Craftman.In annealing process, Hydrogen can penetrate into interlayer oxide.Some hydrogen atoms can eventually arrive at oxide layer-silicon interface, and in conjunction with dangling bonds.It should Reaction has neutralized the positive fixed charge of dangling bonds introducing.Due to incomplete hydrogenation, MOS transistor metal connecting line domain is matched Different can introduce big mismatch between identical device originally.The module is used to be laid out close to symmetrical metal connecting line, is subtracted The mismatch that light endless perhydrogenating introduces.

The modular unit provides control two parameters of transistor grid length and grid width, modifies two parameters, can be with The size of transistor is adjusted, inside will make automatically corresponding adjustment, still maintain matching connection relationship.In the modular unit, Six metal lines are drawn, are connected for modular unit external circuit.

Claims (9)

1. a kind of small size matching transistor parameterized module unit is made of the transistor of two fixed matching connection relationships, It is characterized in that, the modular unit provides control two parameters of transistor grid length and grid width, two parameters are modified, it can To adjust the size of transistor, inside will make automatically corresponding adjustment, still maintain matching connection relationship.

2. modular unit as described in claim 1, which is characterized in that six metal lines are drawn in the modular unit, for mould The connection of module unit external circuit.

3. modular unit as described in claim 1, which is characterized in that the grid area of the transistor, root can be adjusted at any time Factually border domain allows area, Optimized Matching accuracy.

4. modular unit as described in claim 1, which is characterized in that the modular unit uses complete common centroid domain knot Structure.

5. modular unit as described in claim 1, which is characterized in that described transistor the right and left adds equidistant setoff Grid, avoid because polysilicon etch rate it is inconsistent caused by mismatch.

6. modular unit as described in claim 1, which is characterized in that the gate electrode and back of pipe will be served as a contrast or foil in the modular unit Grid are connected, and help to ensure that the electrology characteristic of transistor is not influenced by the pseudo- channel formed below setoff pipe.

7. modular unit as described in claim 1, which is characterized in that do not have to polysilicon in the modular unit and with metal handle Multiple gate electrodes are connected with each other, and prevent adjacent domain from causing etch rate to change there are polysilicon graphics.

8. modular unit as described in claim 1, which is characterized in that the modular unit is correctly handled on polygate electrodes The position of contact hole.

9. modular unit as described in claim 1, which is characterized in that the modular unit has close to symmetrical metal connecting line Layout.