CN109144818B - Method and system for obtaining stability allowance of data bus interface - Google Patents
Method and system for obtaining stability allowance of data bus interface Download PDFInfo
- Publication number
- CN109144818B CN109144818B CN201810904287.9A CN201810904287A CN109144818B CN 109144818 B CN109144818 B CN 109144818B CN 201810904287 A CN201810904287 A CN 201810904287A CN 109144818 B CN109144818 B CN 109144818B
- Authority
- CN
- China
- Prior art keywords
- sampling signal
- group
- data signals
- data bus
- receiving time
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
- G06F11/3041—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is an input/output interface
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/30—Monitoring
- G06F11/3055—Monitoring arrangements for monitoring the status of the computing system or of the computing system component, e.g. monitoring if the computing system is on, off, available, not available
Abstract
The invention discloses a method and a system for obtaining stability allowance of a data bus interface, and belongs to the technical field of communication. According to the invention, whether the data bus interfaces corresponding to the group of data signals are in normal communication is judged according to the sampling results of the group of data signals by adjusting the receiving time of the sampling signals, so that the critical receiving time of the corresponding sampling signals when the data bus interfaces cannot be in normal communication is obtained, the stability allowance of the data bus interfaces is obtained according to the critical receiving time, and the purpose of obtaining the complete adoption position of the data signals during signal sampling is realized.
Description
Technical Field
The present invention relates to the field of communications technologies, and in particular, to a method and a system for obtaining a stability margin of a data bus interface.
Background
At present, in the read-write operation of a memory chip in a high-speed mode, due to the limitation of layout routing, different lengths of packaging routing inside the chip, and different numbers of single direct via holes of 4-Bit (Bit) or 8-Bit Data in the same group, time delay of each Bit Data Bit and DQS (Data strobe) signals in the same group of signals reaching DDR (Double Data Rate SDRAM, Double Data Rate storage) particles (write operation) and reaching a main chip (read operation) is different at the same time, and the stability margin of the same group of Data bus interfaces cannot be determined.
Disclosure of Invention
Aiming at the problem that the stability margin of the same group of data bus interfaces cannot be determined, a method and a system for acquiring the stability margin of the data bus interfaces are provided.
The invention provides a method for acquiring stability allowance of a data bus interface, which comprises the following steps:
receiving a sampling signal and a group of data signals sampled according to the sampling signal;
adjusting the receiving time of the sampling signal, and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling result of the group of data signals;
and acquiring critical receiving time of the corresponding sampling signal when the data bus interface cannot normally communicate, and acquiring stability allowance of the data bus interface according to the critical receiving time.
Preferably, the adjusting the receiving time of the sampling signal and determining whether the data bus interfaces corresponding to the group of data signals normally communicate according to the sampling result of the group of data signals includes:
adjusting the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal;
and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling results of the group of data signals.
Preferably, the adjusting the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal includes:
delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
Preferably, the obtaining a critical receiving time of the sampling signal corresponding to the data bus interface when the data bus interface cannot normally communicate, and obtaining the stability margin of the data bus interface according to the critical receiving time includes:
the method comprises the steps of obtaining delay critical receiving time of the sampling signal and advance critical receiving time of the sampling signal, calculating an adjusting time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtaining data bus interface stability allowance of a group of data signals sampled according to the sampling signal according to the adjusting time range.
Preferably, the delay critical receiving time is a critical time at which the group of data signals cannot be sampled according to the sampling signal during the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
The invention also provides a system for obtaining the stability allowance of the data bus interface, which comprises the following steps:
the receiving unit is used for receiving a sampling signal and a group of data signals sampled according to the sampling signal;
the processing unit is used for adjusting the receiving time of the sampling signals and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling results of the group of data signals;
and the obtaining unit is used for obtaining the critical receiving time of the corresponding sampling signal when the data bus interface cannot normally communicate, and obtaining the stability allowance of the data bus interface according to the critical receiving time.
Preferably, the processing unit is configured to adjust the receiving time of the sampling signal by a preset step length, sample the group of data signals according to the sampling signal, and determine whether the data bus interfaces corresponding to the group of data signals are in normal communication according to a sampling result of the group of data signals.
Preferably, the processing unit includes:
the delay module is used for delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and the advancing module is used for advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
Preferably, the obtaining unit is configured to obtain a delay critical receiving time of the sampling signal and an advance critical receiving time of the sampling signal, calculate an adjustment time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtain a data bus interface stability margin of a group of data signals sampled according to the sampling signal according to the adjustment time range.
Preferably, the delay critical receiving time is a critical time at which the group of data signals cannot be sampled according to the sampling signal during the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
The beneficial effects of the above technical scheme are that:
in the technical scheme, whether the data bus interfaces corresponding to the group of data signals are in normal communication is judged according to the sampling results of the group of data signals by adjusting the receiving time of the sampling signals, so that the critical receiving time of the sampling signals corresponding to the data bus interfaces which cannot be in normal communication is obtained, the stability allowance of the data bus interfaces is obtained according to the critical receiving time, and the purpose of obtaining the complete adoption position of the data signals during signal sampling is achieved.
Drawings
FIG. 1 is a flowchart illustrating a method for obtaining a stability margin of a data bus interface according to an embodiment of the present invention;
FIGS. 2 a-2 e are schematic diagrams illustrating an embodiment of determining the stability margin of the data bus interface by using the method for obtaining the stability margin of the data bus interface according to the present invention;
fig. 3 is a block diagram of a system for obtaining stability margin of a data bus interface according to the present invention.
Detailed Description
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It should be noted that the embodiments and features of the embodiments may be combined with each other without conflict.
The invention is further described with reference to the following drawings and specific examples, which are not intended to be limiting.
The invention provides a method for acquiring stability allowance of a data bus interface, which comprises the following steps:
s1, receiving a sampling signal and a group of data signals sampled according to the sampling signal, and acquiring a default position of the sampling signal;
it should be noted that the method for obtaining the stability margin of the data bus interface is applied to a data receiving end, and the data receiving end may be a main chip, a DDR memory, or an eMMC (fully called an Embedded Multi Media Card).
In practical application, the method for obtaining the stability margin of the data bus interface can be applied to a read operation process, a DDR memory sends a signal to a main chip, and the stability margin of the data bus interface is determined by adopting the method for obtaining the stability margin of the data bus interface at the main chip end.
The method for obtaining the stability allowance of the data bus interface can also be applied to a write operation process, the main chip sends a signal to the DDR memory, and the stability allowance of the data bus interface is determined by adopting the method for obtaining the stability allowance of the data bus interface at the DDR memory.
S2, adjusting the receiving time of the sampling signal, and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling result of the group of data signals;
in this embodiment, when the receiving time of the sampling signal is adjusted, the reference position of the group of data signals corresponding thereto is kept unchanged. And judging whether the data bus interface can normally communicate or not by adjusting the receiving time of the sampling signal. In a preferred embodiment, the step S2 of adjusting the receiving time of the sampling signal and determining whether the data bus interface corresponding to the group of data signals is in normal communication according to the sampling result of the group of data signals includes:
s21, adjusting the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal;
further the step S21 includes:
delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
And S22, judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling results of the group of data signals.
And S3, acquiring critical receiving time of the corresponding sampling signal when the data bus interface cannot normally communicate, and acquiring stability allowance of the data bus interface according to the critical receiving time.
Further, the step S3 specifically includes:
the method comprises the steps of obtaining delay critical receiving time of the sampling signal and advance critical receiving time of the sampling signal, calculating an adjusting time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtaining data bus interface stability allowance of a group of data signals sampled according to the sampling signal according to the adjusting time range.
Wherein the delay critical receiving time is a critical time at which the group of data signals cannot be sampled according to the sampling signal in the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
As an example, taking an example that a DDR memory receives a set of 8-Bit data signals, where a sampling signal is a DQS signal, to correspondingly explain the method for obtaining the stability margin of the data bus interface of the present invention, the sampling signal and a set of data signals corresponding to the sampling signal need to be received first, where the data bus interfaces corresponding to the set of data signals are D0-D7, as shown in fig. 2a, black rectangular bars at the bottom of the figure represent default positions of the DQS signal, and gray areas represent default positions of the data signals received by the data interfaces D0-D7; referring to FIG. 2b, the time when the receiving end receives the DQS signal is delayed (i.e., the DQS signal is shifted from the default position to the right by one frame, which is equivalent to a delay of 7 picoseconds (ps)) by using the default position of the DQS signal as a reference position while keeping the default position of the data signals received by the data interfaces D0-D7 unchanged; each time, the DQS signal is delayed by 7ps until the DQS signal is skewed to the right by 23 cells (delay 161ps), the data signals received by the data bus interfaces D0-D7 cannot be collected, which indicates that the data bus interfaces fail to communicate with reference to fig. 2D, and it can be determined that the delay critical receiving time of the DQS signal is 161ps with reference to fig. 2 c; similarly, the default position of the DQS signal is taken as a reference position, the time for receiving the DQS signal by the receiving end is advanced (namely, the DQS signal deviates one grid from the default position to the left, which is equivalent to 7ps ahead), and the data signals received by the data bus interface D0-D7 cannot be acquired until the DQS signal deviates to the boundary to the left, which indicates that the data bus interface fails to communicate, and the advanced critical receiving time of the DQS signal is determined; and calculating an adjustment time range of the DQS signal according to the delay critical receiving time and the advance critical receiving time of the DQS signal, so as to obtain stability margins of data bus interfaces D0-D7 sampled according to the DQS signal according to the adjustment time range, wherein black rectangular bars A and B in the lower part of FIG. 2e represent the adjustment time range of the DQS signal, and corresponding areas in the range represent that the data bus interfaces D0-D7 can normally communicate.
As shown in fig. 3, the present invention further provides a system for obtaining a stability margin of a data bus interface, including: receiving unit 1, processing unit 2 and acquisition unit 3, wherein:
a receiving unit 1, configured to receive a sampling signal and a group of data signals sampled according to the sampling signal;
the processing unit 2 is used for adjusting the receiving time of the sampling signal and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling result of the group of data signals;
and the obtaining unit 3 is configured to obtain a critical receiving time of the sampling signal when the data bus interface cannot normally communicate, and obtain the stability margin of the data bus interface according to the critical receiving time.
According to the invention, whether the data bus interfaces corresponding to the group of data signals are in normal communication is judged according to the sampling results of the group of data signals by adjusting the receiving time of the sampling signals, so that the critical receiving time of the corresponding sampling signals when the data bus interfaces cannot be in normal communication is obtained, the stability allowance of the data bus interfaces is obtained according to the critical receiving time, and the purpose of obtaining the complete adoption position of the data signals during signal sampling is realized.
In a preferred embodiment, the processing unit 2 is configured to adjust the receiving time of the sampling signal by a preset step length, sample the group of data signals according to the sampling signal, and determine whether the data bus interfaces corresponding to the group of data signals are in normal communication according to the sampling result of the group of data signals.
In a preferred embodiment, the processing unit 2 comprises:
the delay module is used for delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and the advancing module is used for advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
In a preferred embodiment, the obtaining unit 3 is configured to obtain a delay critical receiving time of the sampling signal and an advance critical receiving time of the sampling signal, calculate an adjustment time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtain a data bus interface stability margin of a group of data signals sampled according to the sampling signal according to the adjustment time range.
Further, the delay critical receiving time is a critical time at which the group of data signals cannot be sampled according to the sampling signal during the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
While the invention has been described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention.
Claims (10)
1. A method for obtaining stability allowance of a data bus interface is characterized in that the method is applied to a data receiving end, and the data receiving end comprises a DDR memory and a main chip;
the method comprises the following steps:
receiving a sampling signal and a group of data signals sampled according to the sampling signal;
adjusting the receiving time of the sampling signal, and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling result of the group of data signals;
acquiring critical receiving time of the corresponding sampling signal when the data bus interface cannot normally communicate, and acquiring stability allowance of the data bus interface according to the critical receiving time;
when the method is applied to a read operation process, a DDR memory sends a signal to a main chip, and the stability allowance of a data bus interface is determined at the main chip end by adopting the method; and
when the method is applied to the write operation process, the main chip sends a signal to the DDR memory, and the stability allowance of the data bus interface is determined by adopting the method at the DDR memory;
and keeping the reference position of the group of data signals corresponding to the sampling signal unchanged when the receiving time of the sampling signal is adjusted.
2. The method of claim 1, wherein the adjusting the receiving time of the sampling signal and determining whether the data bus interface corresponding to the group of data signals is in normal communication according to the sampling result of the group of data signals comprises:
adjusting the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal;
and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling results of the group of data signals.
3. The method of claim 2, wherein the adjusting the receiving time of the sampling signal by a preset step size, and sampling the group of data signals according to the sampling signal comprises:
delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
4. The method according to claim 3, wherein the obtaining of the stability margin of the data bus interface according to the critical receiving time of the sampling signal when the data bus interface cannot normally communicate comprises:
the method comprises the steps of obtaining delay critical receiving time of the sampling signal and advance critical receiving time of the sampling signal, calculating an adjusting time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtaining data bus interface stability allowance of a group of data signals sampled according to the sampling signal according to the adjusting time range.
5. The method of claim 4, wherein the delay-critical receiving time is a critical time at which the group of data signals cannot be sampled according to the sampling signal during the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
6. A system for obtaining stability margin of a data bus interface, wherein the method for obtaining stability margin of a data bus interface according to any one of claims 1 to 5 is applied, and comprises:
the receiving unit is used for receiving a sampling signal and a group of data signals sampled according to the sampling signal;
the processing unit is used for adjusting the receiving time of the sampling signals and judging whether the data bus interfaces corresponding to the group of data signals are in normal communication or not according to the sampling results of the group of data signals;
and the obtaining unit is used for obtaining the critical receiving time of the corresponding sampling signal when the data bus interface cannot normally communicate, and obtaining the stability allowance of the data bus interface according to the critical receiving time.
7. The system according to claim 6, wherein the processing unit is configured to adjust a receiving time of the sampling signal by a preset step size, sample the group of data signals according to the sampling signal, and determine whether the data bus interfaces corresponding to the group of data signals are in normal communication according to a sampling result of the group of data signals.
8. The system for deriving data bus interface stability margin of claim 7, wherein the processing unit comprises:
the delay module is used for delaying the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate;
and the advancing module is used for advancing the receiving time of the sampling signal by a preset step length, and sampling the group of data signals according to the sampling signal until the data bus interfaces corresponding to the group of data signals can not normally communicate.
9. The system according to claim 8, wherein the obtaining unit is configured to obtain a delay critical receiving time of the sampling signal and an advance critical receiving time of the sampling signal, calculate an adjustment time range of the sampling signal according to the delay critical receiving time and the advance critical receiving time, and obtain the data bus interface stability margin of a group of data signals sampled according to the sampling signal according to the adjustment time range.
10. The system for obtaining data bus interface stability margin of claim 9, wherein the delay-critical receiving time is a critical time at which the set of data signals cannot be sampled according to the sampling signal during the delay process;
the advance critical reception time is a critical time at which the set of data signals cannot be sampled from the sampling signal during the advance process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810904287.9A CN109144818B (en) | 2018-08-09 | 2018-08-09 | Method and system for obtaining stability allowance of data bus interface |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201810904287.9A CN109144818B (en) | 2018-08-09 | 2018-08-09 | Method and system for obtaining stability allowance of data bus interface |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109144818A CN109144818A (en) | 2019-01-04 |
| CN109144818B true CN109144818B (en) | 2022-04-01 |
Family
ID=64792422
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810904287.9A Active CN109144818B (en) | 2018-08-09 | 2018-08-09 | Method and system for obtaining stability allowance of data bus interface |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109144818B (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110931062A (en) * | 2019-10-29 | 2020-03-27 | 晶晨半导体(上海)股份有限公司 | Method for improving sampling precision of EMMC data signal |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2330078A1 (en) * | 1999-02-24 | 2000-08-31 | Masafumi Narikawa | Communication device and interference rejection method therein |
| CN101110590B (en) * | 2007-08-21 | 2011-05-25 | 中兴通讯股份有限公司 | Method and device for phase adjustment in the course of detecting time sequence allowance |
| CN102347081A (en) * | 2010-07-30 | 2012-02-08 | 联芯科技有限公司 | Method for calibrating phase of DQS (bidirectional data strobe) delay for DDR (double data rate) controller and apparatus thereof |
| CN103164376A (en) * | 2011-12-12 | 2013-06-19 | 扬智科技股份有限公司 | Deviation solution device and method for parallel bus |
| CN106959934A (en) * | 2017-02-21 | 2017-07-18 | 深圳市紫光同创电子有限公司 | Low-voltage differential signal receiving interface and low-voltage differential signal method of reseptance |
-
2018
- 2018-08-09 CN CN201810904287.9A patent/CN109144818B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2330078A1 (en) * | 1999-02-24 | 2000-08-31 | Masafumi Narikawa | Communication device and interference rejection method therein |
| CN101110590B (en) * | 2007-08-21 | 2011-05-25 | 中兴通讯股份有限公司 | Method and device for phase adjustment in the course of detecting time sequence allowance |
| CN102347081A (en) * | 2010-07-30 | 2012-02-08 | 联芯科技有限公司 | Method for calibrating phase of DQS (bidirectional data strobe) delay for DDR (double data rate) controller and apparatus thereof |
| CN103164376A (en) * | 2011-12-12 | 2013-06-19 | 扬智科技股份有限公司 | Deviation solution device and method for parallel bus |
| CN106959934A (en) * | 2017-02-21 | 2017-07-18 | 深圳市紫光同创电子有限公司 | Low-voltage differential signal receiving interface and low-voltage differential signal method of reseptance |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109144818A (en) | 2019-01-04 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US20120262998A1 (en) | Clock synchronization in a memory system | |
| CN105701042A (en) | Optimizing method and system for signal quality of memory control interface | |
| US9437263B2 (en) | Apparatuses and methods for providing strobe signals to memories | |
| US9117509B2 (en) | Electronic apparatus, DRAM controller, and DRAM | |
| CN104505116B (en) | A kind of phase-modulation circuit and phase modulating method for high speed dynamic memory | |
| CN109144818B (en) | Method and system for obtaining stability allowance of data bus interface | |
| CN111243635A (en) | Write data sampling signal time sequence monitoring method, monitoring circuit and memory | |
| WO2020112315A3 (en) | Secure digital (sd) direct command for improving throughput with a reduced memory footprint | |
| US20190189226A1 (en) | Link training mechanism by controlling delay in data path | |
| CN105677594A (en) | Resetting and reading and writing calibration method and equipment for FPGA equipment in DDR3 interface | |
| US8589670B2 (en) | Adjusting system configuration for increased reliability based on margin | |
| CN109213707B (en) | Method, system, device and medium for acquiring sampling position of data interface | |
| CN110764440B (en) | Signal sampling method of memory | |
| CN111190540B (en) | Control method and device for write balance of memory interface | |
| US20140372787A1 (en) | Methods for dynamically adaptive bit-leveling by sweep sampling with automatic jitter avoidance | |
| US8619479B2 (en) | Method for synchronizing signals and processing data | |
| CN109450755B (en) | Method and system for enhancing stability margin of memory module bus interface | |
| US9036434B1 (en) | Random access memory and method of adjusting read timing thereof | |
| CN106796566A (en) | The dynamic voltage regulation of I/O interface signals | |
| CN109117394B (en) | Method and system for enhancing stability of bus interface | |
| CN109359067B (en) | Method and system for acquiring delay step time in storage module | |
| US10902896B2 (en) | Memory circuit and method thereof | |
| US20080232186A1 (en) | Memory interface and adaptive data access method | |
| CN110931062A (en) | Method for improving sampling precision of EMMC data signal | |
| CN109144912B (en) | Method and system for acquiring communication interface boundary of storage module |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |