CN109120274A - A kind of decoding circuit - Google Patents
A kind of decoding circuit Download PDFInfo
- Publication number
- CN109120274A CN109120274A CN201710487500.6A CN201710487500A CN109120274A CN 109120274 A CN109120274 A CN 109120274A CN 201710487500 A CN201710487500 A CN 201710487500A CN 109120274 A CN109120274 A CN 109120274A
- Authority
- CN
- China
- Prior art keywords
- nand gate
- gate
- decoding circuit
- nand
- model
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
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Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M13/00—Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes
- H03M13/65—Purpose and implementation aspects
- H03M13/6575—Implementations based on combinatorial logic, e.g. Boolean circuits
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- Physics & Mathematics (AREA)
- Probability & Statistics with Applications (AREA)
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The invention discloses a kind of decoding circuits, comprising: the first NOT gate, the first NAND gate, the second NAND gate, third NAND gate and the 4th NAND gate；First NOT gate is connected with the second NAND gate and the 4th NAND gate respectively, and the first NAND gate is connected with third NAND gate and the second NAND gate respectively, and third NAND gate is connected with the first NAND gate and the 4th NAND gate respectively.The invention has the benefit that circuit structure is simple, cost is relatively low, and electronic component used is less.
Description
Technical field
The present invention relates to field of circuit technology, especially a kind of decoding circuit.
Background technique
In the prior art, structure is complicated mostly for decoding circuit, and electronic component used is more, has a single function, with high costs.
Summary of the invention
Technical problem to be solved by the present invention lies in, a kind of decoding circuit is provided, circuit structure is simple, and cost is relatively low,
Electronic component used is less.
In order to solve the above technical problems, the present invention provides a kind of decoding circuit, comprising: the first NOT gate, the first NAND gate,
Two NAND gates, third NAND gate and the 4th NAND gate；First NOT gate is connected with the second NAND gate and the 4th NAND gate respectively, and first
NAND gate is connected with third NAND gate and the second NAND gate respectively, third NAND gate respectively with the first NAND gate and the 4th NAND gate
It is connected.
Preferably, NAND gate selects 74LVC32 model, and NOT gate selects 74LVC04 model.
The invention has the benefit that circuit structure is simple, cost is relatively low, and electronic component used is less.
Detailed description of the invention
Fig. 1 is electrical block diagram of the invention.
Specific embodiment
As shown in Figure 1, a kind of decoding circuit, comprising: the first NOT gate, the first NAND gate, the second NAND gate, third NAND gate
With the 4th NAND gate；First NOT gate is connected with the second NAND gate and the 4th NAND gate respectively, the first NAND gate respectively with third with
NOT gate and the second NAND gate are connected, and third NAND gate is connected with the first NAND gate and the 4th NAND gate respectively.
NAND gate selects 74LVC32 model, and NOT gate selects 74LVC04 model.
Although the present invention is illustrated and has been described with regard to preferred embodiment, it is understood by those skilled in the art that
Without departing from scope defined by the claims of the present invention, variations and modifications can be carried out to the present invention.
Claims (2)
1. a kind of decoding circuit characterized by comprising the first NOT gate, the first NAND gate, the second NAND gate, third NAND gate
With the 4th NAND gate；First NOT gate is connected with the second NAND gate and the 4th NAND gate respectively, the first NAND gate respectively with third with
NOT gate and the second NAND gate are connected, and third NAND gate is connected with the first NAND gate and the 4th NAND gate respectively.
2. decoding circuit as described in claim 1, which is characterized in that NAND gate selects 74LVC32 model, and NOT gate is selected
74LVC04 model.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710487500.6A CN109120274A (en) | 2017-06-23 | 2017-06-23 | A kind of decoding circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710487500.6A CN109120274A (en) | 2017-06-23 | 2017-06-23 | A kind of decoding circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN109120274A true CN109120274A (en) | 2019-01-01 |
Family
ID=64733411
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710487500.6A Pending CN109120274A (en) | 2017-06-23 | 2017-06-23 | A kind of decoding circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109120274A (en) |
-
2017
- 2017-06-23 CN CN201710487500.6A patent/CN109120274A/en active Pending
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| WD01 | Invention patent application deemed withdrawn after publication | ||
| WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20190101 |