CN103970950A - Designing method for DDR signal quality improvement - Google Patents
Designing method for DDR signal quality improvement Download PDFInfo
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- CN103970950A CN103970950A CN201410196228.2A CN201410196228A CN103970950A CN 103970950 A CN103970950 A CN 103970950A CN 201410196228 A CN201410196228 A CN 201410196228A CN 103970950 A CN103970950 A CN 103970950A
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- ddr
- signal quality
- ddr signal
- designing method
- quality improvement
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Abstract
The invention provides a designing method for DDR signal quality improvement and belongs to the electronic field. According to the designing method, DDR signal improvement is realized by adding a register between a CPU and a DIMM; DDR signal quality is improved, and normal operation of a system is ensured.
Description
technical field
the present invention relates to electronic applications, specifically a kind of method for designing of improving DDR signal quality.
Background technology
At present, in the time that DDR designs, the length of arrangement wire for DDR on PCB has strict demand.If our design has exceeded length requirement, the eye pattern of DDR signal cannot be opened.When PCB space is enough, we design DDR time can strictly observe the length requirement of DDR.But more and more miniaturization of electronic product at present, structural design also becomes increasingly complex.Some limitation that may occur PCB design, causes DDR design length cannot meet the length requirement scope of Intel.In the situation that length cannot ensure, in order to ensure DDR signal quality, we should improve by some means the signal quality of DDR, guarantee that DDR signal eye diagram meets code requirement, to reach the object of guaranteeing the normal operation of system.
Summary of the invention
Based on the complicacy of current design, and DDR designs length of arrangement wire requirement strict on PCB.For guaranteeing that PCB device layout cannot meet DDR on PCB when length of arrangement wire requirement, the quality of DDR signal.We adopt the method for designing of adding register between CPU and DIMM, improve DDR signal.Improve DDR signal quality, guarantee the normal operation of system.
The invention has the beneficial effects as follows:
Guarantee signal quality.Limitation, the reduction PCB that can break the requirement of DDR length of arrangement wire ensure signal quality when design difficulty, have guaranteed that DDR signal eye diagram meets code requirement, reach the object of guaranteeing the normal operation of system.
Brief description of the drawings
Accompanying drawing 1 is DDR design diagram of the present invention.
Embodiment
For guaranteeing that PCB device layout cannot meet DDR on PCB when length of arrangement wire requirement, the quality of DDR signal.We adopt the method for designing of adding register between CPU and DIMM, improve DDR signal.Improve DDR signal quality, guarantee the normal operation of system.
Claims (1)
1. improve a method for designing for DDR signal quality, it is characterized in that, in order to ensure DDR signal quality, guaranteeing the normal operation of system, between CPU and DIMM, add register, DDR signal will send by register.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410196228.2A CN103970950A (en) | 2014-05-12 | 2014-05-12 | Designing method for DDR signal quality improvement |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201410196228.2A CN103970950A (en) | 2014-05-12 | 2014-05-12 | Designing method for DDR signal quality improvement |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN103970950A true CN103970950A (en) | 2014-08-06 |
Family
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Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201410196228.2A Pending CN103970950A (en) | 2014-05-12 | 2014-05-12 | Designing method for DDR signal quality improvement |
Country Status (1)
| Country | Link |
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| CN (1) | CN103970950A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776420A (en) * | 2016-11-11 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of mainboard structure for lifting DDR signal transmission quality |
| CN112597729A (en) * | 2021-03-04 | 2021-04-02 | 新华三半导体技术有限公司 | DDR SDRAM channel optimization method and device and memory chip |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050188281A1 (en) * | 2004-02-04 | 2005-08-25 | Vincent Nguyen | Memory module with testing logic |
| US20120106228A1 (en) * | 2010-11-03 | 2012-05-03 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
-
2014
- 2014-05-12 CN CN201410196228.2A patent/CN103970950A/en active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20050188281A1 (en) * | 2004-02-04 | 2005-08-25 | Vincent Nguyen | Memory module with testing logic |
| US20120106228A1 (en) * | 2010-11-03 | 2012-05-03 | Netlist, Inc. | Method and apparatus for optimizing driver load in a memory package |
Non-Patent Citations (1)
| Title |
|---|
| TOMEK JASIONOWSKI: "RDIMM最大限度提高服务器性能和可扩展性", 《中国电子商情(基础电子)》 * |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN106776420A (en) * | 2016-11-11 | 2017-05-31 | 郑州云海信息技术有限公司 | A kind of mainboard structure for lifting DDR signal transmission quality |
| CN112597729A (en) * | 2021-03-04 | 2021-04-02 | 新华三半导体技术有限公司 | DDR SDRAM channel optimization method and device and memory chip |
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| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
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Application publication date: 20140806 |