CN109117302A - A kind of internal memory data acquiring method, system, Memory Management Middleware and medium - Google Patents
A kind of internal memory data acquiring method, system, Memory Management Middleware and medium Download PDFInfo
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- CN109117302A CN109117302A CN201810835485.4A CN201810835485A CN109117302A CN 109117302 A CN109117302 A CN 109117302A CN 201810835485 A CN201810835485 A CN 201810835485A CN 109117302 A CN109117302 A CN 109117302A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1044—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices with specific ECC/EDC distribution
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
- G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
- G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
- G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
- G06F11/1072—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in multilevel memories
Abstract
This application discloses a kind of internal memory data acquiring methods, it is connected applied to one end with the Memory Controller Hub on CPU, the other end is separately connected the Memory Management Middleware of preset quantity memory, by using the hardware of this additional, by it is original need to be completed by processor operate and handle step for realizing memory mirror purpose and all marry again to the Memory Management Middleware, allow processor end as there is only processing steps when single internal memory to carry out, it completes to parse by the Memory Management Middleware, more parts of forwardings, it collects feedback data and carries out error checking and correction, and correct feedback data is finally back to processor, so that processor pressure is smaller, occupying system resources are less, also application scenarios are widened to single channel system simultaneously, practical effect is more preferably.The application further simultaneously discloses a kind of internal storage data and obtains system, Memory Management Middleware and computer readable storage medium, has above-mentioned beneficial effect.
Description
Technical field
This application involves memory high reliability field, in particular to a kind of internal memory data acquiring method, system, memory management
Middleware and computer readable storage medium.
Background technique
Memory failure will lead to computer data and permanently lose or system failure, to bring and can not estimate to personal or enterprise
The disaster of meter, all computers need to guarantee the reliability of memory.
Memory mirror is the currently used method for improving reliability of memory, the warm back-up class of working principle and hard disk
Seemingly, memory mirror is that internal storage data is done to two copies, is individually placed in main memory and mirror memory.Once event occurs for main memory
Hinder (or data transmission fault), data will be transferred on mirror memory, effectively prevent due to memory by Memory Controller Hub
Loss of data caused by channel failure guarantees that computer system operates normally to improve the reliability and stability of system.
Specifically, the program (such as Fig. 1) is directly to hang two or more memory bars on the processor of computer, by handling
Device controls the read-write operation of two or more memory bars and is write simultaneously from processor into two or more memories when system works
Enter data, processor selects several data in EMS memory correctly that memory using certain mechanism for correcting errors in read operation.It can
By, it is evident that the work done under in a manner of such all transfers to processor to complete, meeting extreme influence processor handles other
The performance of business, while being also that cannot achieve memory mirror function to the system of two-way or multichannel is not supported on hardware, to hardware
It is required that higher.
Therefore, how to overcome items technological deficiency present in existing promotion internal storage data reliability scheme, one kind is provided
The scheme of smaller, lower to the hardware requirement promotion reliability of memory of processor pressure is that those skilled in the art are urgently to be resolved
Problem.
Summary of the invention
The purpose of the application is to provide a kind of internal memory data acquiring method, applied to the Memory Controller Hub on one end and CPU
The connected, other end is separately connected the Memory Management Middleware of preset quantity memory, will by using the hardware of this additional
It is original need to be completed by processor operate and handle step for realizing memory mirror purpose and all marry again to the memory management
Middleware allows processor end as there is only processing steps when single internal memory to carry out, among the memory management
Part completes parsing, more parts of forwardings, collects feedback data and carry out error checking and correction, and correct feedback data is finally back to place
Device is managed, so that processor pressure is smaller, occupying system resources are less, while also widening application scenarios to single channel system, it is real
Border using effect is more preferably.
The another object of the application is the provision of a kind of internal storage data and obtains system, Memory Management Middleware and calculating
Machine readable storage medium storing program for executing.
To achieve the above object, the application provides a kind of internal memory data acquiring method, is applied to Memory Management Middleware, should
Method includes:
Receive the read request command that Memory Controller Hub is initiated；Wherein, the Memory Controller Hub is located on CPU；
The read request command is parsed, and format is can be read into memory in obtained parsing post command while being sent to and oneself
The connected each memory of body, so that each memory returns to corresponding reading feedback data；
ECC error checking and correction is carried out to each reading feedback data received, obtains error checking and correction as a result, and according to the mistake
Check results determine target memory；Wherein, the target memory is to determine that there is no in mistake after the ECC error checking and correction
It deposits；
Format is can be read into the memory in the reading feedback data that the target memory returns and is back to the Memory control
Device.
Optionally, the internal memory data acquiring method further include:
For the different priority of all each memory settings for being connected to the Memory Management Middleware；
When the quantity for determining the target memory according to the error checking and correction result is greater than 1, selection wherein possesses maximum
The memory of priority is as preferred memory；
It is corresponding, format is can be read into the memory in the reading feedback data that the target memory returns and is back in described
Memory controller, specifically:
Format is can be read into the memory in the reading feedback data that the preferred memory returns and is back to the Memory control
Device.
Optionally, the internal memory data acquiring method further include:
The number that mistake does not occur in the reading feedback data that each memory returns is counted according to the error checking and correction result,
And it is quotient with total degree, obtain accuracy；
Each respective accuracy of memory in the same period is counted, and replaces the accuracy lower than pre- using new memory
If the memory of accuracy threshold value.
To achieve the above object, present invention also provides a kind of internal storage datas to obtain system, is applied among memory management
Part, the system include:
Read request command receiving unit, for receiving the read request command of Memory Controller Hub initiation；Wherein, the memory control
Device processed is located on CPU；
Parsing and Dispatching Unit, for parsing the read request command, and obtained parsing post command is readable with memory
It takes format while being sent to each memory being connected with itself, so that each memory returns to corresponding reading feedback data；
Error checking and correction and target memory determination unit, for carrying out ECC error checking and correction to each reading feedback data received,
Error checking and correction is obtained as a result, and determining target memory according to the error checking and correction result；Wherein, the target memory is described in warp
Determine that there is no the memories of mistake after ECC error checking and correction；
Target memory data return unit, the reading feedback data for returning to the target memory are readable with the memory
Format is taken to be back to the Memory Controller Hub.
Optionally, which obtains system further include:
Priority setting unit, for for different excellent of all each memory settings for being connected to the Memory Management Middleware
First grade；
According to priority selecting unit determines that the quantity of the target memory is greater than according to the error checking and correction result for working as
When 1, the memory for wherein possessing greatest priority is chosen as preferred memory；
It is corresponding, the target memory data return unit specifically:
Format is can be read into the memory in the reading feedback data that the preferred memory returns and is back to the Memory control
Device.
Optionally, which obtains system further include:
Accuracy computing unit, for counting the reading feedback data that each memory returns according to the error checking and correction result
In the number of mistake does not occur, and be quotient with total degree, obtain accuracy；
Memory replacement unit for counting each respective accuracy of memory in the same period, and is replaced using new memory
Change the memory that the accuracy is lower than default accuracy threshold value.
To achieve the above object, present invention also provides a kind of Memory Management Middlewares, comprising:
Memory, for storing computer program；
Processor realizes the internal memory data acquiring method as described in above content when for executing the computer program
The step of.
To achieve the above object, described computer-readable to deposit present invention also provides a kind of computer readable storage medium
It is stored with computer program on storage media, is realized when the computer program is executed by processor in as described in above content
The step of deposit data acquisition methods.
Obviously, a kind of internal memory data acquiring method provided herein, applied to the Memory Controller Hub on one end and CPU
The connected, other end is separately connected the Memory Management Middleware of preset quantity memory, will by using the hardware of this additional
It is original need to be completed by processor operate and handle step for realizing memory mirror purpose and all marry again to the memory management
Middleware allows processor end as there is only processing steps when single internal memory to carry out, among the memory management
Part completes parsing, more parts of forwardings, collects feedback data and carry out error checking and correction, and correct feedback data is finally back to place
Device is managed, so that processor pressure is smaller, occupying system resources are less, while also widening application scenarios to single pass system,
Practical effect is more preferably.The application additionally provides a kind of internal storage data simultaneously and obtains system, Memory Management Middleware and calculating
Machine readable storage medium storing program for executing has above-mentioned beneficial effect, and details are not described herein.
Detailed description of the invention
In order to illustrate the technical solutions in the embodiments of the present application or in the prior art more clearly, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
The embodiment of application for those of ordinary skill in the art without creative efforts, can also basis
The attached drawing of offer obtains other attached drawings.
Fig. 1 is a kind of structural schematic diagram of the existing promotion of mirror-image fashion based on memory reliability of memory；
Fig. 2 is the structural schematic diagram that a kind of mirror-image fashion based on memory provided by the present application promotes reliability of memory；
Fig. 3 is a kind of flow chart of internal memory data acquiring method provided by the embodiments of the present application；
Fig. 4 is the flow chart of another internal memory data acquiring method provided by the embodiments of the present application；
Fig. 5 is a kind of logical construction schematic diagram of Memory Management Middleware provided by the embodiments of the present application；
Fig. 6 is the structural block diagram that a kind of internal storage data provided by the embodiments of the present application obtains system.
Specific embodiment
The core of the application is to provide a kind of internal memory data acquiring method, system, Memory Management Middleware and computer can
Storage medium is read, is connected by newly-increased one end with the Memory Controller Hub on CPU, the other end is separately connected in preset quantity memory
Management middleware is deposited, original needs are operated and handled into step whole turn by what processor was completed for realizing memory mirror purpose
It transfers and allows processor end as there is only processing steps when single internal memory to carry out to the Memory Management Middleware, by
The Memory Management Middleware completes parsing, more parts of forwardings, collects feedback data and carry out error checking and correction, and finally will be correctly anti-
Feedback data are back to processor so that processor pressure is smaller, occupying system resources are less, while also by application scenarios widen to
Single channel system, practical effect is more preferably.
To keep the purposes, technical schemes and advantages of the embodiment of the present application clearer, below in conjunction with the embodiment of the present application
In attached drawing, the technical scheme in the embodiment of the application is clearly and completely described, it is clear that described embodiment is
Some embodiments of the present application, instead of all the embodiments.Based on the embodiment in the application, those of ordinary skill in the art
All other embodiment obtained without making creative work, shall fall in the protection scope of this application.
Embodiment one
Below in conjunction with Fig. 3, Fig. 3 is a kind of flow chart of internal memory data acquiring method provided by the embodiments of the present application, Fig. 3 institute
The method shown is applied to that one end is connected with the Memory Controller Hub on CPU, the other end is separately connected the memory pipe of preset quantity memory
Middleware is managed, connection relationship is as shown in Figure 2, the specific steps are as follows:
S101: the read request command that Memory Controller Hub is initiated is received；
This step is intended to receive the memory request initiated by upper layer operating system, the present embodiment by taking read request command as an example,
Purpose is that some data are read from memory returns to upper layer operating system, and write request order is similar, and only purpose is
By in the data write-in memory of upper layer operating system, those skilled in the art are according to read request command provided by the present application
Can easily recursion is to the realization process of write request order, details are not described herein again.
It should be noted that the read request command of this step description be Memory Controller Hub " with for " on CPU there is only
The read request command issued when one external memory, because as shown in Fig. 2, in CPU, among memory management connected to it
Part is exactly unique existing memory, therefore CPU only needs to process operations to execution according to most common.
S102: parsing read request command, and format is can be read into memory in obtained parsing post command while being sent to each
Memory, so that each memory returns to corresponding reading feedback data；
On the basis of S101, this step is intended to parse the read request command sent by the Memory Controller Hub on CPU, to mention
Object content is taken out, which is the directional information for wanting to read which kind of data from memory, so as to according to the direction
Information finds this partial data from memory.Meanwhile after being parsed, it is also necessary to more parts are copied as, to be transmitted to simultaneously
It is connected to the multiple memories of itself.At least there is a main memory and at least one mirror memory in the mode of mirror image based on memory,
But due to being two different memory bars, in duplication and repeating process also need that path is adjusted flexibly according to the actual situation
And parameter so that main memory and mirror memory can receive the order that Memory Controller Hub issues.
After each memory receives the order issued by memory intermediate management part, the storage sky at itself is ordered according to these
Between the middle reading for carrying out information, and be fed back to Memory Management Middleware.
S103: ECC error checking and correction is carried out to each reading feedback data received, obtains error checking and correction as a result, and according to difference
Wrong check results determine target memory；
On the basis of S102, this step is intended to carry out error checking and correction to the reading feedback data that multiple memories return, will
The reading feedback data for not occurring error in data is back to Memory Controller Hub, completes the processing of a read request command.Wherein, target
Memory is to determine that there is no the memories of mistake after ECC error checking and correction.
ECC is the english abbreviation of Error Correcting Code, and Chinese is " error checking and correction ", and ECC is
A technique for can be realized " error checking and correction ", ECC memory is exactly the memory for applying this technology, generally applies more
On server and graphics workstation, this will make entire computer system more tend to safety and stability at work.It is to be understood that ECC skill
Art cannot not mention Parity (even-odd check).
Applying before ECC technology appearance, in memory at most is another technology, is exactly (the odd even school Parity
It tests).In digital circuit, the smallest data unit is exactly to be " bit (bit) ", is also cried data " position ", and " bit " is also memory
In minimum unit, it is that the high and low level signal of data is indicated by " 1 " and " 0 ".In digital circuit 8 it is continuous
Bit is a byte (byte), there was only 8 without each byte in the memory of " even-odd check " in memory, if it certain
One has stored out mistake, and the corresponding data wherein stored will be made to change and cause application program that mistake occurs.And band
There is the interior of " even-odd check " to add additional one again outside there are each byte (8) for carrying out error detection.Such as one
A certain numerical value (1,0,1,0,1,0,1,1) is stored in byte, each mutually adds up (1+0+1+0+1+0+1+1=5) this.
It is on the contrary then be 0 if for even parity check, check bit is just defined as 1 as a result, odd number；For odd, then on the contrary.When CPU is returned
When readback takes the data of storage, it can be added the data stored in first 8 again, and whether calculated result is consistent with check bit.
It will attempt to correct these mistakes when CPU has found that the two is different.But the deficiency of Parity is: when memory finds some data bit
When wrong, might not but it can determine that in which position, it is also just different surely to correct mistake, so interior with even-odd check
The major function deposited is only " it was found that mistake ", can not correct the simple mistake in part.
Parity memory is to check current 8 data by increasing a data bit on the basis of original data bit
Correctness, but as the data bit that the increase Parity of data bit is used to examine also is multiplied, that is when data bit is 16
It needs to increase by 2 for checking when position, then needs to increase by 4 when data bit is 32, and so on.Especially work as data volume
When very big, the probability of corrupt data is also bigger, just seems power for that can only correct the method for odd-even check of easy bugs
Not from the heart, it being based on such a case, a kind of new memory techniques are come into being, here it is ECC, this technology
It is that check bit is added to realize outside in original data bit, the difference is that the increased method of the two is different, this is also resulted in
The major function of the two is not quite alike.It unlike Parity if data bit is 8, need to increase by 5 come into
The inspection of row ECC error and correction, data bit often double, and ECC only increases by a bit trial position, that is to say, that when data bit is 16
When position ECC when being 6,32 ECC be 7, ECC are 8 when data bit is 64, and so on, the every increasing of data bit
It doubles, ECC only increase by one.In short, ECC can allow mistake in memory, and system can be made to obtain error correction
To continue normally to operate, not reason mistake and interrupt, and ECC have the automatic identification more powerful than Parity, corrigendum energy
Parity can not be checked that the error bit come is found and by error correction by power.
It should be noted that the probability is relatively small for memory error, when being abnormal with failure, working condition is more steady
It is fixed, therefore have very that maximum probability occurs that there are multiple target memories after ECC error checking and correction, but do not need to return to multiple mesh simultaneously
The reading feedback data of memory is marked to Memory Controller Hub, because being the same, is also needed when such situation occurs therefrom
Choose a more particularly suitable memory reading feedback data, mode is varied, can priority-based mode, based on number
Sequence, based on resources occupation rate etc. mode, can according to the actual situation under all influence factor flexible choices that may be present, this
Place is simultaneously not specifically limited.
S104: format is can be read into memory in the reading feedback data that target memory returns and is back to Memory Controller Hub.
On the basis of S103, the reading feedback data that this step returns to target memory is with the identifiable shape of Memory Controller Hub
Formula is back to Memory Controller Hub, to complete the processing of a read request command.
Further, the mode of memory mirror is typically based on to promote reliability of memory, by a main memory and a mirror
As memory composition, so that when main memory breaks down, mirror memory can also be replaced in time, so that data are not lost in
It is disconnected.In principle, the quantity of mirror memory is more, and reliability of memory is higher, but in actual application, more memory associations
The difficulty of tune process can be obviously improved with increasing for mirror memory quantity, not only proposed higher performance to middleware and wanted
It asks, it is also necessary to higher cost of implementation, therefore the mode for generalling use a main mirror image is sufficient for most application scenarios,
But it is also not excluded for that the mode of more mirror memories is arranged based on other purposes, it can flexible choice according to the actual situation.
Further, it when some memory failure for being connected to Memory Management Middleware is not available, can mention in time
Warning information prompting changing out can tentatively enable two when the memory of connection is more than or equal to 3, when one of damage
When, directly close damage memory bank connection, while enable before not enabled spare memory, at least use two memories
To realize the purpose for promoting reliability of memory.
Further, it can also be counted according to error checking and correction result in the reading feedback data that each memory returns and mistake does not occur
Number accidentally, and it is quotient with total degree, obtain accuracy；Each respective accuracy of memory in the same period is counted, and using new
Memory replaces the memory that accuracy is lower than default accuracy threshold value.I.e. there are exceptions or failure to become for discovery in time in this manner
The memory of gesture.
Based on the above-mentioned technical proposal, a kind of internal memory data acquiring method provided by the embodiments of the present application, be applied to one end with
Memory Controller Hub on CPU is connected, the other end is separately connected the Memory Management Middleware of preset quantity memory, by using this
Original needs are operated and handled step whole by what processor was completed for realizing memory mirror purpose by the hardware of additional
It marries again and allows processor end as there is only processing steps when single internal memory to carry out to the Memory Management Middleware,
Parsing, more parts of forwardings are completed, feedback data is collected and are carried out error checking and correction by the Memory Management Middleware, and finally will be correct
Feedback data is back to processor, so that processor pressure is smaller, occupying system resources are less, while also widening application scenarios
To single channel system, practical effect is more preferably.
Embodiment two
Below in conjunction with Fig. 4, Fig. 4 is the flow chart of another internal memory data acquiring method provided by the embodiments of the present application, this
Embodiment on the basis of example 1, provide it is a kind of based on priority come the quantity of target memory be greater than 1 when choose one
The mode of a preferred memory, specific implementation step are as follows:
S201: the read request command that Memory Controller Hub is initiated is received；
S202: parsing read request command, and format is can be read into memory in obtained parsing post command while being sent to each
Memory, so that each memory returns to corresponding reading feedback data；
S203: ECC error checking and correction is carried out to each reading feedback data received, obtains error checking and correction as a result, and according to difference
Wrong check results determine target memory；
S204: for the different priority of all each memory settings for being connected to Memory Management Middleware；
S205: when the quantity of target memory is greater than 1, the memory for wherein possessing greatest priority is chosen as preferably interior
It deposits；
The present embodiment is the different priority of all each memory settings for being connected to Memory Management Middleware first, and is being worked as
When the quantity of target memory is greater than 1, the memory for wherein possessing greatest priority is chosen as preferred memory, highest priority meaning
This memory be more suitable for.Further, it can also be carried out according to the working condition of each memory for the priority of each memory setting
Dynamic adjusts, so that preferred memory all is done in the best memory choosing of working condition in such situation every time.
S206: format is can be read into memory in the reading feedback data that preferred memory returns and is back to Memory Controller Hub.
Embodiment three
On the basis of the above embodiments, the present embodiment provides a kind of use FPGA (Field Programmable Gate
Array, field programmable gate array) constitute Memory Management Middleware, and by have more the module being made of IO primitive come reality
The now operation of each step, comprising:
PHY_HOST module: the interface module with Memory Controller Hub realizes DDR (Double Data Rate synchronous dynamic random storage
Device, a kind of memory standards) IO input and output；
Command analysis module: the CMD order that parsing cpu controller is sent is completed, and is sent to two PHY_DEV moulds simultaneously
Block；
PHY_DEVx module: the Memory Controller Hub function that IO primitive is realized；
Redundant control module: the back read data for receiving two memory bars is tested, and completes access selection.
Fig. 5 is referred to below, is successively illustrated so that CPU initiates read request command as an example:
CPU Memory Controller Hub initiates read request command, and the DDR that PHY_HOST module correctly samples input using primitive reads life
Order is sent to command analysis module, is sent to two PHY_DEV simultaneously after the parsing of command analysis module completion read request command
Read request command is sent to memory bar respectively with the format of DDR by module, PHY_DEV module, memory bar return back read data to
PHY_DEV module, the DDR that PHY_DEV module correctly samples input using primitive read data and are sent to redundant control module, redundancy
Control module carries out ECC check, and selection check does not have vicious access, and the priority of main memory access is higher than the logical of mirror memory
Road, read data after redundant control module exports give PHY_HOST module, PHY_HOST module reading data DDR format send out
Give CPU Memory Controller Hub.
PHY_HOST module and PHY_DEV module have used FPGA I/O primitive respectively, are delayed small and can dynamically adjust
Whole IO delay delay.Using to I/O primitive further include ISERDES/OSERDES and IODELAY, ISERDES/OSERDES
The conversion that can be used to realize rate is completed the rate inside the double-speed data and FPGA of DDR between single times of rate and is converted；
IODELAY is a programmable delay unit, can compensate for Sampling caused by DDR signal is delayed because of PCB trace.
The present embodiment connects processor and memory bar using the Memory Management Middleware based on FPGA primitive as bridge, whole
A Memory Management Middleware+memory bar only need to access memory by operating method all the way in processor only memory all the way
?；And Memory Management Middleware can connect two-way or multichannel memory, the mistake error correction of multichannel memory is all by the memory
Middleware is managed to complete；Simultaneously the Memory Management Middleware can it is any using standard DIMM (dual inline memory module, i.e.,
Memory bar interface) interface system in use, system is without making any change.
It should be noted that primitive concept involved by the present embodiment, in operating system or computer network term model
Refer to be instructed by several in farmland and form, for completing a process of certain function, is made of several machine instructions
Completion certain specific function one section of program, there is inseparability, i.e. the execution of primitive must be continuous, execute
Do not allow to be interrupted in journey.
Be different under similar scene be possibly used for realize the IP Core (IP kernel, in embedded FPGA design of identical purpose
In, refer to certain designed modules, be divided into software module and hardware module), the primitive that the present embodiment uses hardly accounts for
With fpga logic resource, and function is built by user, and flexibility and modularization are stronger, can not only meet DDR RL (Read
Latency reads incubation period) requirement can also carry out demand customization in a manner of similar ASIC, Project Realization level by
Just operability is stronger, and the most important is that the low delay that the characteristic that can not be interrupted due to it makes it be satisfied memory read-write is wanted
It asks.
And the mode of IP kernel passes through its reading for being unable to satisfy DDR RL of process verification although theoretically may be implemented
Delay requirement, because it is larger generally to possess biggish delay, and its source code is invisible, Wu Fagen to meet general requirment
It modifies according to user demand；Still make its nothing since to make it that can occupy fpga logic resource more for its too fat to move structure simultaneously
Method is applied in engineering.
Because situation is complicated, it can not enumerate and be illustrated, those skilled in the art should be able to recognize according to the application
The basic skills principle combination actual conditions of offer may exist many examples, in the case where not paying enough creative works,
It should within the scope of protection of this application.
Fig. 6 is referred to below, Fig. 6 is the structural block diagram that a kind of internal storage data provided by the embodiments of the present application obtains system,
The system may include:
Read request command receiving unit 100, for receiving the read request command of Memory Controller Hub initiation；Wherein, in described
Memory controller is located on CPU；
Parsing and Dispatching Unit 200, for parsing the read request command, and can with memory by obtained parsing post command
Reading format is sent to each memory being connected with itself simultaneously, so that each memory returns to corresponding reading feedback data；
Error checking and correction and target memory determination unit 300, for carrying out ECC mistake school to each reading feedback data received
It tests, obtains error checking and correction as a result, and determining target memory according to error checking and correction result；Wherein, target memory is through ECC mistake school
Determine that there is no the memories of mistake after testing；
Lattice can be read with memory in target memory data return unit 400, the reading feedback data for returning to target memory
Formula is back to Memory Controller Hub.
Further, which, which obtains system, to include:
Priority setting unit, for for different preferential of all each memory settings for being connected to Memory Management Middleware
Grade；
According to priority selecting unit, for choosing when the quantity for determining target memory according to error checking and correction result is greater than 1
Wherein possess the memory of greatest priority as preferred memory；
It is corresponding, target memory data return unit 400 specifically:
Format is can be read into memory in the reading feedback data that preferred memory returns and is back to Memory Controller Hub.
Further, which, which obtains system, to include:
Accuracy computing unit does not occur for being counted in the reading feedback data that each memory returns according to error checking and correction result
The number of mistake, and it is quotient with total degree, obtain accuracy；
Memory replacement unit, for counting each respective accuracy of memory in the same period, and just using the replacement of new memory
True rate is lower than the memory of default accuracy threshold value.
Based on the above embodiment, present invention also provides a kind of Memory Management Middleware, which may include storage
Device and processor, wherein have computer program in the memory, which calls the computer program in the memory
When, step provided by above-described embodiment may be implemented.Certainly, the middleware can also include various necessary network interfaces,
Power supply and other components etc..
Present invention also provides a kind of computer readable storage mediums, have computer program thereon, the computer program
Step provided by above-described embodiment may be implemented when being performed terminal or processor execution.The storage medium may include: U
Disk, mobile hard disk, read-only memory (Read-Only Memory, ROM), random access memory (Random Access
Memory, RAM), the various media that can store program code such as magnetic or disk.
Specific examples are used herein to illustrate the principle and implementation manner of the present application, and between each embodiment
For progressive relationship, each embodiment focuses on the differences from other embodiments, identical between each embodiment
Similar portion may refer to each other.For the device disclosed in the embodiment, reference can be made to corresponding method part illustration.The above reality
The explanation for applying example is merely used to help understand the present processes and its core concept.For the ordinary skill people of the art
Member for, under the premise of not departing from the application principle, can also to the application, some improvement and modification can also be carried out, these improve and
Modification is also fallen into the protection scope of the claim of this application.
It should also be noted that, in the present specification, relational terms such as first and second and the like be used merely to by
One entity or operation are distinguished with another entity or operation, without necessarily requiring or implying these entities or operation
Between there are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant meaning
Covering non-exclusive inclusion, so that the process, method, article or equipment for including a series of elements not only includes that
A little elements, but also other elements including being not explicitly listed, or further include for this process, method, article or
The intrinsic element of equipment.In the absence of more restrictions, the element limited by sentence "including a ...", is not arranged
Except there is also other identical elements in the process, method, article or equipment for including element.
Claims (8)
1. a kind of internal memory data acquiring method, which is characterized in that be applied to Memory Management Middleware, comprising:
Receive the read request command that Memory Controller Hub is initiated；Wherein, the Memory Controller Hub is located on CPU；
The read request command is parsed, and format is can be read into memory in obtained parsing post command while being sent to and itself phase
Each memory even, so that each memory returns to corresponding reading feedback data；
ECC error checking and correction is carried out to each reading feedback data received, obtains error checking and correction as a result, and according to the error checking and correction
As a result target memory is determined；Wherein, the target memory is to determine that there is no the memories of mistake after the ECC error checking and correction；
Format is can be read into the memory in the reading feedback data that the target memory returns and is back to the Memory Controller Hub.
2. internal memory data acquiring method according to claim 1, which is characterized in that further include:
For the different priority of all each memory settings for being connected to the Memory Management Middleware；
When the quantity for determining the target memory according to the error checking and correction result is greater than 1, selection wherein possesses maximum preferential
The memory of grade is as preferred memory；
It is corresponding, format is can be read into the memory in the reading feedback data that the target memory returns and is back to the memory control
Device processed, specifically:
Format is can be read into the memory in the reading feedback data that the preferred memory returns and is back to the Memory Controller Hub.
3. internal memory data acquiring method according to claim 1 or 2, which is characterized in that further include:
It is counted according to the error checking and correction result and wrong number does not occur in the reading feedback data that each memory returns, and with
Total degree is quotient, obtains accuracy；
Each respective accuracy of memory in the same period is counted, and is lower than using the new memory replacement accuracy and is preset just
The memory of true rate threshold value.
4. a kind of internal storage data obtains system, which is characterized in that be applied to Memory Management Middleware, comprising:
Read request command receiving unit, for receiving the read request command of Memory Controller Hub initiation；Wherein, the Memory Controller Hub
On CPU；
Parsing and Dispatching Unit, can be read lattice for parsing the read request command, and by obtained parsing post command with memory
Formula is sent to each memory being connected with itself simultaneously, so that each memory returns to corresponding reading feedback data；
Error checking and correction and target memory determination unit are obtained for carrying out ECC error checking and correction to each reading feedback data received
Error checking and correction is as a result, and determine target memory according to the error checking and correction result；Wherein, the target memory is through the ECC
Determine that there is no the memories of mistake after error checking and correction；
Lattice can be read with the memory in target memory data return unit, the reading feedback data for returning to the target memory
Formula is back to the Memory Controller Hub.
5. internal storage data according to claim 4 obtains system, which is characterized in that further include:
Priority setting unit, for for different preferential of all each memory settings for being connected to the Memory Management Middleware
Grade；
According to priority selecting unit, for when determined according to the error checking and correction result target memory quantity be greater than 1 when,
The memory for wherein possessing greatest priority is chosen as preferred memory；
It is corresponding, the target memory data return unit specifically:
Format is can be read into the memory in the reading feedback data that the preferred memory returns and is back to the Memory Controller Hub.
6. internal storage data according to claim 4 or 5 obtains system, which is characterized in that further include:
Accuracy computing unit, for being counted in the reading feedback data that each memory returns not according to the error checking and correction result
The number of mistake occurs, and is quotient with total degree, obtains accuracy；
Memory replacement unit replaces institute for counting each respective accuracy of memory in the same period, and using new memory
State the memory that accuracy is lower than default accuracy threshold value.
7. a kind of Memory Management Middleware characterized by comprising
Memory, for storing computer program；
Processor realizes that internal storage data as described in any one of claims 1 to 3 obtains when for executing the computer program
The step of method.
8. a kind of computer readable storage medium, which is characterized in that be stored with computer on the computer readable storage medium
Program, the computer program realize internal storage data acquisition side as described in any one of claims 1 to 3 when being executed by processor
The step of method.
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111209129A (en) * | 2019-12-27 | 2020-05-29 | 曙光信息产业股份有限公司 | Memory optimization method and device based on AMD platform |
| CN117234996A (en) * | 2023-11-10 | 2023-12-15 | 广州翼辉信息技术有限公司 | Automatic calibration method for communication between GMAC and FPGA |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060288177A1 (en) * | 2005-06-21 | 2006-12-21 | Mark Shaw | Memory mirroring apparatus and method |
| CN107748704A (en) * | 2017-10-13 | 2018-03-02 | 郑州云海信息技术有限公司 | The method and device that memory mirror based on FPGA is realized |
| US9959074B1 (en) * | 2016-11-29 | 2018-05-01 | EMC IP Holding Company LLC | Asynchronous in-memory data backup system |
-
2018
- 2018-07-26 CN CN201810835485.4A patent/CN109117302A/en active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060288177A1 (en) * | 2005-06-21 | 2006-12-21 | Mark Shaw | Memory mirroring apparatus and method |
| US9959074B1 (en) * | 2016-11-29 | 2018-05-01 | EMC IP Holding Company LLC | Asynchronous in-memory data backup system |
| CN107748704A (en) * | 2017-10-13 | 2018-03-02 | 郑州云海信息技术有限公司 | The method and device that memory mirror based on FPGA is realized |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111209129A (en) * | 2019-12-27 | 2020-05-29 | 曙光信息产业股份有限公司 | Memory optimization method and device based on AMD platform |
| CN117234996A (en) * | 2023-11-10 | 2023-12-15 | 广州翼辉信息技术有限公司 | Automatic calibration method for communication between GMAC and FPGA |
| CN117234996B (en) * | 2023-11-10 | 2024-01-30 | 广州翼辉信息技术有限公司 | Automatic calibration method for communication between GMAC and FPGA |
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Application publication date: 20190101 |