CN109104188A - It is a kind of for minimizing the local oscillation circuit of ODU receiving channel - Google Patents
It is a kind of for minimizing the local oscillation circuit of ODU receiving channel Download PDFInfo
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- CN109104188A CN109104188A CN201811190633.8A CN201811190633A CN109104188A CN 109104188 A CN109104188 A CN 109104188A CN 201811190633 A CN201811190633 A CN 201811190633A CN 109104188 A CN109104188 A CN 109104188A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
- H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
- H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
- H03B5/08—Generation of oscillations using amplifier with regenerative feedback from output to input with frequency-determining element comprising lumped inductance and capacitance
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/099—Details of the phase-locked loop concerning mainly the controlled oscillator of the loop
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Abstract
The invention discloses a kind of for minimizing the local oscillation circuit of ODU receiving channel, including frequency synthesizer, this vibration magnifier, local oscillator frequency multiplier and the local oscillator filter being sequentially connected in series, frequency synthesizer and monolithic mechatronics, single-chip microcontroller controls the signal frequency of the generation of the frequency synthesizer, this vibration magnifier carries out power amplification to the signal of generation, frequency multiplication is carried out by frequency of the local oscillator frequency multiplier to signal again, local oscillator filter is then filtered output to the signal after frequency multiplication.Further disclose the composition of chip and interface network used in foregoing circuit.The local oscillation circuit be applied to miniaturization ODU receiving channel, required composite signal frequency can be changed by way of parameter configuration, at the same also have the characteristics that it is reliable and stable, save power consumption, reduce volume, drop low cost aspect also there is advantage.
Description
Technical field
The invention belongs to fields of communication technology, are suitable for satellite communication more particularly to one kind and minimize ODU receiving channel
Local oscillation circuit.
Background technique
In satellite communication equipment, ODU (Out-door Unit) refers to outdoor unit, mainly includes frequency transformation and function
Rate amplification, specific to be divided into transmission channel and receiving channel again, transmission channel typically refers to BUC (Block Up-
Converter), i.e., up-conversion power amplifier, receiving channel are primarily referred to as LNB (Low Noise Block down-
Converter), i.e. low noise amplification, frequency converter.
In satellite communication equipment, it usually needs local oscillation circuit is as source oscillation signal, and the local oscillator electricity in receiving channel
The frequency of oscillation that road generates usually requires to adjust, to meet to the different application demands for receiving frequency.In addition, due to receiving
Satellite-signal can have Doppler effect and frequency deviation occurs, it is also desirable to the source oscillation signal for enabling to local oscillation circuit to generate
Frequency can adapt to the reception signal frequency of this variation.
Also, with satellite communication equipment miniaturization trend, it is also desirable to which each section built-up circuit therein, which has, to be accounted for
With the advantages such as space is few, low in energy consumption, stability is high.
Summary of the invention
The invention mainly solves the technical problem of providing a kind of for minimizing the local oscillation circuit of ODU receiving channel, solves
Certainly frequency is not easy to and circuit complicated composition, the component mostly big problem with power consumption in the prior art.
In order to solve the above technical problems, the technical solution adopted by the present invention is that providing a kind of logical for minimizing ODU reception
The local oscillation circuit in road, it is described including frequency synthesizer, this vibration magnifier, local oscillator frequency multiplier and the local oscillator filter being sequentially connected in series
Frequency synthesizer and monolithic mechatronics, the single-chip microcontroller control the signal frequency of the generation of the frequency synthesizer, and described
Vibration magnifier carries out power amplification to the signal, then carries out frequency multiplication, institute by frequency of the local oscillator frequency multiplier to the signal
It states local oscillator filter and output then is filtered to the signal after frequency multiplication.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the frequency synthesizer packet
Include the phase discriminator, loop filter and voltage controlled oscillator being sequentially connected in series, the first reference source input terminal of the phase discriminator be used for
External reference source electrical connection, the external reference source are inputted to the phase discriminator with reference to frequency by the first reference source input terminal
Rate signal, the numerical control interface of the phase discriminator is corresponding to be electrically connected the single-chip microcontroller, the single-chip microcontroller by the numerical control interface to
The phase discriminator inputs frequency control parameters, and the phase demodulation output end of the phase discriminator is electrically connected the input of the loop filter
End, the output end of the loop filter are electrically connected the voltage controling end of the voltage controlled oscillator, the vibration of the voltage controlled oscillator
Signal output end output composite signal is swung, and the oscillator signal output end is also inputted with the second reference source of the phase discriminator
End electrical connection, so that the composite signal enters the phase discriminator by the second reference source input terminal.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, described vibration magnifier packet
Include chip ECG001F-G.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the local oscillator frequency multiplier packet
Include chip HMC369LP3E.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the local oscillator filter is
Microstrip filter.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the microstrip filter packet
The U-shaped microwave metal tape of 5 be arranged on ceramic substrate is included, the microwave metal tape is sequentially arranged at intervals and is centrosymmetric
Distribution, wherein the first microwave metal tape opening upwards and it is located at symmetrical centre, the second microwave metal tape and third microwave gold
Belonging to band, Open Side Down, is located at the left and right side of the first microwave metal tape, the 4th microwave metal tape opening upwards
And it is located at the left side of the second microwave metal tape, it is laterally extended on the left branch of the 4th microwave metal tape as first end
Mouthful, the 5th microwave metal tape opening upwards and the right side for being located at the third microwave metal tape, the 5th microwave metal tape
It is laterally extended on right branch as second port.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the phase discriminator includes core
Piece ADF4106, the loop filter include operational amplifier chip AD797, and the end CP of the chip ADF4106 passes through concatenation
First RC network is electrically connected with the negative input of the chip AD797, and the positive input of the chip AD797 then passes through
Two RC networks connect direct current 5V voltage, and the negative input of the chip AD797 also passes through third RC network and the chip AD797
Output end electrical connection.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the voltage controlled oscillator packet
Chip SMV5000E is included, the chip SMV5000E voltage input end is electrically connected with the output end of the chip AD797, the core
The oscillator signal output end of piece SMV5000E is connected to the end RFin_A of the chip ADF4106 by resistor network.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the single-chip microcontroller is chip
Three ends I/O of ATTINY9, the chip ATTINY9 are connected respectively the enable end of the chip ADF4106, data terminal
And clock end, and three ends I/O resistance in parallel and be grounded.
In local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel, the local oscillation circuit is also wrapped
Include voltage conversion circuit, 5V DC voltage is converted to 3.3V DC voltage by the voltage conversion circuit, and independently to
The chip ATTINY9 and chip ADF4106 provides 3.3V DC-voltage supply.
The beneficial effects of the present invention are: the invention discloses a kind of for minimizing the local oscillation circuit of ODU receiving channel, wrap
The frequency synthesizer being sequentially connected in series, this vibration magnifier, local oscillator frequency multiplier and local oscillator filter are included, frequency synthesizer and monolithic are electromechanical
Connection, single-chip microcontroller control the signal frequency of the generation of the frequency synthesizer, this vibration magnifier carries out power to the signal of generation
Amplification, then frequency multiplication is carried out by frequency of the local oscillator frequency multiplier to signal, local oscillator filter is then filtered the signal after frequency multiplication defeated
Out.Further disclose the composition of chip and interface network used in foregoing circuit.The local oscillation circuit is applied to miniaturization
ODU receiving channel can change required composite signal frequency by way of parameter configuration, while also have reliable and stable
Feature also has advantage saving power consumption, reduction volume, drop low cost aspect.
Detailed description of the invention
Fig. 1 is the present invention for minimizing the one embodiment composition block diagram of local oscillation circuit of ODU receiving channel；
Fig. 2 is the present invention for minimizing one embodiment frequency synthesizer of the local oscillation circuit composition frame of ODU receiving channel
Figure；
Fig. 3 is phase detector circuit figure in another embodiment of local oscillation circuit of the present invention for minimizing ODU receiving channel；
Fig. 4 is active loop filter in another embodiment of local oscillation circuit of the present invention for minimizing ODU receiving channel
Circuit diagram；
Fig. 5 is passive loop filter in another embodiment of local oscillation circuit of the present invention for minimizing ODU receiving channel
Circuit diagram；
Fig. 6 is the loop filter circuit of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel
Figure；
Fig. 7 is the single chip circuit figure of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel；
Fig. 8 is the voltage-controlled oscillator circuit of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel
Figure；
Fig. 9 is the amplifier circuit figure of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel；
Figure 10 is the frequency multiplier circuit figure of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel；
Figure 11 is the local oscillator microstrip filter of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel
Structure chart；
Figure 12 is the voltage conversion circuit of local oscillation circuit another embodiment of the present invention for minimizing ODU receiving channel
Figure.
Specific embodiment
To facilitate the understanding of the present invention, in the following with reference to the drawings and specific embodiments, the present invention will be described in more detail.
A better embodiment of the invention is given in the attached drawing.But the invention can be realized in many different forms, and unlimited
In this specification described embodiment.On the contrary, purpose of providing these embodiments is makes to the disclosure
Understand more thorough and comprehensive.
It should be noted that unless otherwise defined, all technical and scientific terms used in this specification with belong to
The normally understood meaning of those skilled in the art of the invention is identical.Used term in the description of the invention
It is the purpose in order to describe specific embodiment, is not intended to the limitation present invention.
With reference to the accompanying drawing, various embodiments of the present invention are described in detail.Fig. 1 is the present invention for minimizing ODU
The one embodiment composition schematic diagram of local oscillation circuit of receiving channel.As shown in Figure 1, the local oscillation circuit includes that the frequency being sequentially connected in series is closed
Grow up to be a useful person P1, this vibration magnifier P2, local oscillator frequency multiplier P3 and local oscillator filter P4, the frequency synthesizer is also electrically connected with single-chip microcontroller P0
It connects, the single-chip microcontroller P0 controls the signal frequency of the generation of the frequency synthesizer, and described vibration magnifier P2 is to the signal
Power amplification is carried out, then frequency multiplication is carried out by frequency of the local oscillator frequency multiplier P3 to the signal, the local oscillator filter P4 is then
Output is filtered to the local oscillation signal after frequency multiplication.
The frequency for the signal that the local oscillation circuit can synthesize frequency synthesizer by single-chip microcontroller is configured or changes, and makes
Obtaining the frequency values that the local oscillation circuit generates can change, and adapt to a variety of application demands.In addition, using integrated circuit in the local oscillation circuit
Component reduces the separating component in peripheral circuit, can there is smaller volume.
Further, as shown in Fig. 2, the frequency synthesizer 10 includes phase discriminator 101, the loop filter being sequentially connected in series
102 and voltage controlled oscillator 103, the first reference source input terminal 1011 of the phase discriminator 101 is used for external reference source 11 (such as
10MHz temperature compensating crystal oscillator) it is electrically connected, the external reference source 11 passes through the first reference source input terminal 1011 to the phase discriminator
101 input reference frequency signals (such as 10MHz signal), the corresponding electrical connection single-chip microcontroller of the numerical control interface 1013 of the phase discriminator 101
12, the single-chip microcontroller 12 inputs frequency control parameters, the phase discriminator to the phase discriminator 101 by the numerical control interface 1013
101 phase demodulation output end is electrically connected the input terminal of the loop filter 102, and the output end of the loop filter 102 is electrically connected
The voltage controling end 1031 of the voltage controlled oscillator 103 is connect, the oscillator signal output end 1032 of the voltage controlled oscillator 103 exports
Composite signal, and the oscillator signal output end 1032 is also electric with the second reference source input terminal of the phase discriminator 101 1012
Connection, so that the composite signal enters the phase discriminator 101 by the second reference source input terminal 1012.
For embodiment illustrated in fig. 2, wherein single-chip microcontroller 12 can be to 101 write frequency of phase discriminator by numerical control interface 1013
Control parameter, the frequency control parameters mainly include first divided to the reference frequency signal from external reference source 11
Thus frequency division parameter value divides reference frequency signal to obtain the first fractional frequency signal with the first frequency division parameter value；And
To the second frequency division parameter value that the composite signal for carrying out the generation of voltage controlled oscillator 103 is divided, thus with the second frequency dividing ginseng
Numerical value divides composite signal to obtain the second fractional frequency signal；By the way that the first frequency division parameter value and the second frequency dividing ginseng is rationally arranged
Numerical value, the first fractional frequency signal obtained after enabling to phase discriminator 101 to divide reference frequency signal and composite signal respectively and
Second fractional frequency signal carries out phase bit comparison, to obtain the phase difference of the two fractional frequency signals, the phase difference is from phase discriminator 101
The output of phase demodulation output end, obtains a voltage value, which is applied to voltage-controlled vibration again after loop filter 102 filters
The voltage controling end 1031 of device 103 is swung, thus change the frequency of the composite signal of the output of voltage controlled oscillator 103, and the synthesis is believed
Number phase discriminator 101 is fed back to further through the second reference source input terminal 1012, looped back and forth like this, so that it may so that composite signal
Frequency is the frequency needed for us, and keeps stablizing output.
The local oscillation circuit of this structure has the function of numerical control, can by single-chip microcontroller come rationally be arranged frequency control parameters come
The frequency for the composite signal that voltage controlled oscillator 103 generates is adjusted, therefore has the advantages that frequency is adjustable.In practical applications,
It can according to need the synthesis that the parameter difference for only needing single-chip microcontroller to be arranged in different products may make the product to generate
Signal frequency is different, and no longer needs to appoint the parameter that single-chip microcontroller exports once after the frequency characteristic of the product is decided
What is modified or adjustment, ensure that the stability of the output of products frequency.Therefore, scheme used by the present embodiment is generating synthesis
When signal, there is good controllability, while also with good stability.
Phase discriminator 101 in Fig. 2 can realize by monomer chip, as shown in Figure 3, it is preferred that the phase discriminator packet
Chip ADF4106 is included, the first reference source input terminal of the phase discriminator corresponds to the end REFin of the chip ADF4106, described
Second reference source input terminal of phase discriminator corresponds to the end RFin_A of the chip ADF4106, the numerical control interface of the phase discriminator
The SPI interface of the chip ADF4106 is corresponded to, the corresponding SPI interface includes enable end LE, data terminal DATA and clock end
CLK, the phase demodulation output end of the phase discriminator correspond to the end CP of the chip ADF4106.
Preferably, the end REFin of chip ADF4106 is also connected with RC filter network, can to the reference signal of input into
Row filtering.The RC filter network includes capacitor C6, C7 of concatenation, and resistance R2 is also electrically connected between the two capacitors,
The other end of resistance R2 is grounded.Preferably, the capacitance of capacitor C6, C7 is 10nF, and the resistance value of resistance R2 is 51 Ω.
Additionally, it is preferred that, it is 5V DC voltage and 3.3V direct current respectively that chip ADF4106 is powered using twin voltage
Pressure power supply.Wherein, the end A_Vdd, the end DVdd and CE terminate 3.3V, and Vp terminates 5V, and the end Vp is also connected with power filter network,
It is made of inductance L1 and capacitor C1, C2.
Here, chip ADF4106 is selected, is on the one hand that the chip is defeated with very wide operating frequency range, including maximum
Frequency bandwidth is 6GHz out, is 20MHz-250MHz by the reference signal that the end RFin_A can input, maximum phase demodulation frequency is
56MHz, operating voltage be 5V and 3.3V, running current be 20mA (under 3.3V voltage conditions), ground noise be-
223dBc/Hz, and the manipulation to the chip can be realized by three Wiring ports, control word is simple and easy to write, and debugging is convenient.
Further, the active loop filter that the loop filter in Fig. 2 is made of operational amplifier, or
The passive loop filter being made of RC circuit.As shown in Figure 4 and Figure 5, chip ADF4106 and active loop are respectively illustrated
The circuit interface relationship and chip ADF4106 of filter and the circuit interface relationship of passive loop filter.
As shown in figure 4, the positive input access of the operational amplifier in the active loop filter is with reference to electricity
It presses, the end CP after the first loop filtering resistance R1 of negative input concatenation of the operational amplifier with the chip ADF4106
Electrical connection, and the end CP also the first loop filtering capacitor C1 of parallel connection is grounded, and the negative input of the operational amplifier is also
The output end for being connected to the operational amplifier by concatenating the second loop filtering resistance R2 and the second loop filtering capacitor C2,
The output end of the operational amplifier is the output end of the active loop filter, is electrically connected the electricity of the voltage controlled oscillator
Press control terminal.
Preferably, the resistance value of the resistance R1 in Fig. 4 is 100 Ω, and the resistance value of R2 is 160 Ω, and the capacitance of capacitor C1 is
33.0nF, the capacitance of capacitor C2 are 120nF.
The advantages of this active loop filter be biggish voltage can be driven to the voltage controlled oscillator of rear stage, the disadvantage is that
A part of noise can be introduced, certain influence is brought on the ground noise of the local oscillation circuit.
As shown in figure 5, the RC circuit in the passive loop filter includes being electrically connected with the end CP of the chip ADF4106
The other end parallel connection third loop filtering capacitor C3 of the third loop filtering resistance R2, the third loop filtering resistance R2 that connect and
Ground connection, and the output end as the passive loop filter is electrically connected the voltage controling end of the voltage controlled oscillator, it is described
The end CP of chip ADF4106 also parallel connection Fourth Ring road filter capacitor C1 and be grounded, one end of Fourth Ring road filter resistance R1 also with
The end the CP electrical connection, the other end concatenate fifth ring road filter capacitor C2 and are grounded.
Preferably, the resistance value of the resistance R1 in Fig. 5 is 180 Ω, and the resistance value of R2 is 360 Ω, and the capacitance of capacitor C1 is
10.0nF, the capacitance of capacitor C2 are 120nF, and the capacitance of capacitor C3 is 3.90nF.
The advantages of this passive loop filter is will not to bring noise, but shortcoming cannot be improved to rear stage
The voltage-controlled adjustment voltage of voltage controlled oscillator.
Therefore, the loop filter that can be used as of two embodiments of Fig. 4 and Fig. 5 uses, can be according to application conditions difference
And it reasonably selects and uses.
It is further preferred that as shown in fig. 6, the operational amplifier in the active loop filter is chip
The end CP of AD797, the chip ADF4106 are electrically connected by concatenating the negative input of the first RC network and the chip AD797
It connects, the positive input of the chip AD797 then passes through the second RC network and connects direct current 5V voltage, the negative sense of the chip AD797
Input terminal also passes through third RC network and is electrically connected with the output end of the chip AD797.
Fig. 6 shows interface relationship and the two between phase demodulation chip ADF4106 and operation amplifier chip AD797
Practical situations of the chip in frequency synthesizer.
Preferably, wherein first RC network includes the end CP and the chip AD797 in the chip ADF4106
The first resistor R4 and second resistance R5 being sequentially connected in series between negative input, between the first resistor R4 and second resistance R5
Electrical connection first capacitor C13 and be grounded, and also and meet the second capacitor C61 at the end CP and be grounded, and at the end CP
It is also electrically connected 3rd resistor R35, the 3rd resistor R35 is electrically connected third capacitor C60 again and is grounded.
By first RC network construct chip ADF4106 the end CP and the chip AD797 negative input it
Between interface relationship, enable to the phase discrimination signal exported by the end CP to carry out smoothed filter after first RC network, eliminate
Erratic fluctuations therein ensure that the stability of phase demodulation output signal.
It is further preferred that second RC network is included in the direct current 5V voltage and the chip in Fig. 6
Magnetic bead inductance L4, the 4th resistance R8, the 5th resistance R9 and the 6th resistance R10 being sequentially connected in series between the positive input of AD797；
Also it is parallel with capacitor the 4th capacitor C15 and the 5th capacitor C16 respectively between the magnetic bead inductance L4 and the 4th resistance R8, it is described
The other end of 4th capacitor C15 and the 5th capacitor C16 is grounded；Also distinguish between the 4th resistance R8 and the 5th resistance R9
The other end for being parallel with the 7th resistance R11 and the 6th capacitor C17, the 7th resistance R11 and the 6th capacitor C17 is grounded；Described
The 8th capacitor C18, the other end ground connection of the 8th capacitor C18 are also parallel between 5th resistance R9 and the 6th resistance R10；?
The 8th resistance R12, the 8th electricity are also parallel between the 6th resistance R10 and the positive input of the chip AD797
The other end of resistance R12 concatenates the 9th capacitor C19 and is grounded.
Voltage regulation filtering can be carried out to the direct current 5V voltage of access by second RC network, so that into chip AD797
Positive input direct current 5V voltage it is relatively stable, in addition be exactly by be arranged these resistance resistance value so that in chip
The voltage of the positive input of AD797 is arranged on appropriate voltage value, thus be conducive to chip AD797 to positive input and
When progress voltage compares between negative input, with stable and suitable Voltage Reference foundation.Therefore, the second RC network
Double action with pressure stabilizing and partial pressure.
Preferably, in the second RC network in Fig. 6, the resistance value of resistance R8 is 1k Ω, and the resistance value of R9 is 10 Ω, R10's
Resistance value is 100 Ω, and the resistance value of R11 is 1k Ω, and the resistance value of R12 is 10 Ω, and the capacitance of capacitor C15 is 100nF, capacitor C16's
Capacitance is 100pF, and the capacitance of capacitor C17 is 1uF, and the capacitance of capacitor C18 is 10nF, and the capacitance of capacitor C19 is
10nF。
It is further preferred that the third RC network includes the tenth capacitor C11 and the 9th resistance R3 being sequentially connected in series.
Output end by the third RC network in the chip AD797 is built between the negative input of chip AD797
Found feedback link, can to chip AD797 amplifying to pressure difference signal between positive input and negative input and
After filtering, a voltage signal is exported to the voltage controlled oscillator of rear stage by the output end of chip AD797.
It is further preferred that the single-chip microcontroller correspondence is chip ATTINY9 in Fig. 7, the three of the chip ATTINY9
A end I/O (Fig. 7 is shown as the end PB2_LE, the end PB1_CLK and the end PB0_DAT) is connected respectively the chip ADF4106's
Enable end, data terminal and clock end, and three ends I/O resistance in parallel and be grounded.
Chip ATTINY9 is small-sized single-chip microcontroller a small in size and few pin, including three I/O pins should all
It uses and is electrically connected with the enable end of chip ADF4106, data terminal and clock end.Also had using chip ATTINY9 low in energy consumption
Advantage.
It is further preferred that the chip SMV5000E is electric as shown in figure 8, voltage controlled oscillator includes chip SMV5000E4
Pressure input terminal (Fig. 8 is shown as the end Vt) is electrically connected with the output end of the chip AD797, the oscillation letter of the chip SMV5000E
Number output end (Fig. 8 is shown as the end RFOUT) is connected to the end RFin_A of the chip ADF4106 by resistor network.Preferably,
The resistor network includes resistance R6, R7 and R13, and resistance value is 18 Ω, the T-shaped design of these three resistance, wherein the one end resistance R6
The oscillator signal output end of chip SMV5000E is connect, the other end is electrically connected R7 and R13, and the other end of R7 can be used as synthesis
Oscillator signal output, and the other end of R13 then feeds back to the end RFin_A of the chip ADF4106.The resistor network is realized
By-passing to composite signal, while also playing the effect of front and back impedance matching.
Further, as shown in figure 9, described vibration magnifier includes chip ECG001F-G.The work of chip ECG001F-G
Making frequency range is 0-6GHz, and gain is 20dB, noise coefficient 3.4dB, exports 1dB compression horsepower 12.5dBm ,+5V power supply, work electricity
Flow 30mA.The chip is encapsulated using 6 feet, and shape is small and circuit is easy to use.
Be electrically connected from one end R7 in resistor network shown in Fig. 8 with the capacitor C14 in Fig. 9, C14 again with chip
The end RFI of ECG001F-G is electrically connected, and chip ECG001F-G is to the composite signal exported by voltage controlled oscillator chip SMV5000E
Carry out power amplification.It can be seen that peripheral circuit needed for chip ECG001F-G is few, in addition to filtering in the end RFO electric connection of power supply
Outside lattice network, other pins of the chip are grounded.The power filter network mainly includes inductance L5, L18, capacitor C21,
C22, resistance R14, R15, wherein inductance L18 mono- terminates 5V DC voltage, the other end be electrically connected capacitor C21, C22 and resistance R14,
R15, wherein capacitor C21, C22 earth, and resistance R14, R15 it is in parallel after be commonly connected to inductance L5, inductance L5's is another
The end RFO of end connection chip ECG001F-G.
Preferably, it is also connected with build-out resistor network at the end RFO of chip ECG001F-G, which includes
Resistance R48, R49, R50, wherein R49 connects the end RFO, and resistance R48, R50 are grounded after being electrically connected the both ends of resistance R49.This
Distribution network enables to the output end of chip ECG001F-G, i.e. the end RFO can carry out good impedance with the frequency multiplier of rear stage
Matching.
Further, as shown in Figure 10, the local oscillator frequency multiplier includes chip HMC369LP3E.The chip inputs frequency
4.5GHz-8GHz, output frequency 9-16GHz, output power is up to 16dBm.Fundamental wave, triple-frequency harmonics isolation 18dB, 5V voltage
Work, static working current 75mA.The chip is also that frequency multiplication can be realized in single-chip, from fig. 10 it can be seen that the chip in addition to
Power end VCC connects outside power filter network, and other ports are mainly exactly to be grounded.The power filter network include inductance L14 and
Capacitor C29 and C41,5V voltage are connected to inductance L14, another termination capacitor C29 and C41 of L14, the other end of the two capacitors
It is grounded, and the end VCC of another chip termination HMC369LP3E of L14.
Further, as shown in figure 11, the local oscillator filter is microstrip filter.The structure of the microstrip filter includes
The U-shaped microwave metal tape of 5 be arranged on ceramic substrate, the microwave metal tape are sequentially arranged at intervals and are centrosymmetric point
Cloth, wherein the first microwave metal tape P41 opening upwards and be located at symmetrical centre, the second microwave metal tape P42 and third are micro-
Open Side Down by wave metal tape P43, is located at the left and right side of the first microwave metal tape P41, the 4th microwave metal
With P44 opening upwards and positioned at the left side of the second microwave metal tape P42, the left branch of the 4th microwave metal tape P44
On be laterally extended as first port P46, the 5th microwave metal tape P45 opening upwards and be located at the third microwave metal tape P43
Right side, be laterally extended as second port P47 on the right branch of the 5th microwave metal tape P45.
Preferably, the width of the first microwave metal tape P41 is 0.13mm, the length of left-hand branch and right-hand branch and
It is identical, it is 2.5mm, it is 1.21mm that lower part, which connects branch length, and the lower part connects two of the left and right end portions of branch
Turning is cut off by isosceles, obtained left cut while and length when right cut be 0.18mm, the first microwave metal tape P41 with it is described
Second microwave metal tape P42, third microwave metal tape P43 interval be 0.14mm.
It is further preferred that the second microwave metal tape P42 and third microwave metal tape P43 structure having the same,
Wherein the left-hand branch of the second microwave metal tape P42 is identical with the left-hand branch length of the third microwave metal tape P43,
It is 2.5mm, the right-hand branch of the right-hand branch of the second microwave metal tape P42 and the third microwave metal tape P43 are long
It spends identical, is 2.5mm, the second microwave top metal tape P42 connection branch connect with the top third microwave metal tape P43
Identical branch length is 1.21mm, and top connection branch connect two turnings of the left and right end portions of branch with top
It is cut off by isosceles, the length of obtained trimming is identical, is 0.18mm.
The right-hand branch of the second microwave metal tape P42 and the left-hand branch of the first microwave metal tape P41 are contour
Concordantly, i.e., under the left-hand branch of the lower edge of the right-hand branch of the second microwave metal tape P42 and the first microwave metal tape P41
The top edge of the corresponding connection branch in end is concordant, at the same the top edge of the left-hand branch of the first microwave metal tape P41 with
The lower edge that branch is connected corresponding to the right-hand branch upper end of the second microwave metal tape P42 is concordant.Equally, the third
The left-hand branch of microwave metal tape P43 and the right-hand branch of the first microwave metal tape P41 are contour concordant.
0.1mm, and described are divided between the second microwave metal tape P42 and the 4th microwave metal tape P44
Three microwave metal tape P43 and the interval of the 5th microwave metal tape P45 with it is identical and be 0.1mm.
Preferably, the length of the right-hand branch of the 4th microwave metal tape P44 is 2.5mm, and width is 0.13mm, left side
The length of branch is 1.65mm, and width is 0.24mm, and bottom connection branch is divided into two sections, wherein the first connection positioned at left side
The length of section is 1.05mm, and width is 0.24mm, and the left hand corner of first linkage section is cut off by isosceles, and what is obtained cuts
The length on side is 0.34mm, and the length positioned at second linkage section on right side is 0.56mm, and width is 0.13mm, and described second
The right hand corner of linkage section is cut off by isosceles, and the length of obtained trimming is 0.18mm.
It is further preferred that the length of the first port P46 is 0.76mm, width is 0.25mm, the first port
The distance of the top of first linkage section for arriving bottom connection branch below of P46 is 0.1mm.
Preferably, the 4th microwave metal tape P44 and the 5th microwave metal tape P45 structure having the same, the two are closed
In the left-hand branch length of the symmetrical distribution in microstrip antenna center, the 5th microwave metal tape P45 be 2.5mm, it is wide
Degree is 0.13mm, and the length of right-hand branch is 1.65mm, and width is 0.24mm, and bottom connection branch is divided into two sections, wherein is located at
The length of first linkage section on right side is 1.05mm, and width is 0.24mm, and the right hand corner of first linkage section by etc.
Waist excision, the length of obtained trimming is 0.34mm, and the length positioned at second linkage section in left side is 0.56mm, and width is
0.13mm, and the left hand corner of second linkage section is cut off by isosceles, and the length of obtained trimming is 0.18mm.
It is further preferred that the first port P46 and second port P47 structure having the same, the two is about micro-strip
The symmetrical distribution in center, the length of the second port P47 are 0.76mm, and width is 0.25mm, the second port P47
The distance of top of first linkage section for arriving bottom connection branch below be 0.1mm, distance is 0.1mm here,
In different embodiments, which can be a variety of numerical value, and such as 0.2mm, 0.3mm are not limited in the present embodiment.The first end
Mouth the distance between P46 and second port P47, that is to say that the length of the local oscillator microstrip filter is 8.85mm.
It is further preferred that the thickness of the first microwave metal tape P41 to the 5th microwave metal tape P45 are
0.13mm, the thickness of the ceramic substrate are 0.254mm.
It is further preferred that the bandpass filtering range of the local oscillator microstrip filter is 9.75GHz-10.6GHz, passband is inserted
Enter loss≤3dB, VSWR≤1.3, Out-of-band rejection is: within the scope of 5GHz-6.56GHz, inhibiting ratio >=55dBc, in 15GHz-
Within the scope of 16.95GHz, inhibit ratio >=55dBc.
It is further preferred that the local oscillation circuit further includes voltage conversion circuit, the voltage conversion circuit is by 5V direct current
Voltage is converted to 3.3V DC voltage, and independently provides 3.3V to the chip ATTINY9 and chip ADF4106
DC-voltage supply.As shown in figure 12, which includes chip LP5907-3.3, and the chip volume is small, pin is few,
It can be seen from the figure that 5V voltage is connected to the input terminal of the chip, the i.e. end IN, bypass one capacitor C44 ground connection, the chip it is defeated
Outlet, i.e. OUT terminal also bypass capacitor C20 ground connection, while being also electrically connected conversion output 3.3V DC voltage after inductance L7.It is excellent
Choosing, in order to guarantee the independence of 3.3V power supply, two panels chip LP5907-3.3 is used in the local oscillation circuit, respectively to chip
ATTINY9 and the chip ADF4106 separately provide 3.3V DC voltage.
Based on above embodiments, the invention discloses a kind of for minimizing the local oscillation circuit of ODU receiving channel, including according to
The frequency synthesizer of secondary concatenation, this vibration magnifier, local oscillator frequency multiplier and local oscillator filter, frequency synthesizer are electrically connected with single-chip microcontroller
It connects, single-chip microcontroller controls the signal frequency of the generation of the frequency synthesizer, this vibration magnifier carries out power to the signal of generation and puts
Greatly, then by frequency of the local oscillator frequency multiplier to signal frequency multiplication is carried out, local oscillator filter is then filtered output to the signal after frequency multiplication.
Further disclose the composition of chip and interface network used in foregoing circuit.The local oscillation circuit is applied to miniaturization ODU
Receiving channel can be changed required composite signal frequency by way of parameter configuration, while also have reliable and stable spy
Point also has advantage saving power consumption, reduction volume, drop low cost aspect.
The above description is only an embodiment of the present invention, is not intended to limit the scope of the invention, all to utilize this hair
Equivalent structure transformation made by bright specification and accompanying drawing content is applied directly or indirectly in other relevant technical fields,
It is included within the scope of the present invention.
Claims (10)
1. a kind of for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that including the frequency synthesis being sequentially connected in series
Device, this vibration magnifier, local oscillator frequency multiplier and local oscillator filter, the frequency synthesizer and monolithic mechatronics, the single-chip microcontroller
Controlling the signal frequency of the generation of the frequency synthesizer, described vibration magnifier carries out power amplification to the signal, then by
The local oscillator frequency multiplier carries out frequency multiplication to the frequency of the signal, and the local oscillator filter then carries out the local oscillation signal after frequency multiplication
Filtering output.
2. according to claim 1 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the frequency
Synthesizer includes the phase discriminator, loop filter and voltage controlled oscillator being sequentially connected in series, the first reference source input of the phase discriminator
For being electrically connected with external reference source, the external reference source is defeated to the phase discriminator by the first reference source input terminal at end
Enter reference frequency signal, the numerical control interface of the phase discriminator is corresponding to be electrically connected the single-chip microcontroller, and the single-chip microcontroller passes through the number
It controls interface and inputs frequency control parameters to the phase discriminator, the phase demodulation output end of the phase discriminator is electrically connected the loop filter
Input terminal, the output end of the loop filter is electrically connected the voltage controling end of the voltage controlled oscillator, the voltage controlled oscillation
The oscillator signal output end of device exports composite signal, and the oscillator signal output end is also referred to the second of the phase discriminator
Source input terminal electrical connection, so that the composite signal enters the phase discriminator by the second reference source input terminal.
3. according to claim 2 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the local oscillator
Amplifier includes chip ECG001F-G.
4. according to claim 3 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the local oscillator
Frequency multiplier includes chip HMC369LP3E.
5. according to claim 4 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the local oscillator
Filter is microstrip filter.
6. according to claim 5 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the micro-strip
Filter includes 5 U-shaped microwave metal tapes being arranged on ceramic substrate, and the microwave metal tape is sequentially arranged at intervals and is in
Central symmetry distribution, wherein the first microwave metal tape opening upwards and it is located at symmetrical centre, the second microwave metal tape and the
Open Side Down for three microwave metal tapes, is located at the left and right side of the first microwave metal tape, the 4th microwave metal tape
Opening upwards and the left side for being located at the second microwave metal tape, be laterally extended on the left branch of the 4th microwave metal tape for
First port, the 5th microwave metal tape opening upwards and the right side for being located at the third microwave metal tape, the 5th microwave gold
Belong to and being laterally extended on the right branch of band as second port.
7. described in any item for minimizing the frequency synthesizer of ODU receiving channel according to claim 2 to 6, feature exists
In the phase discriminator includes chip ADF4106, and the loop filter includes operational amplifier chip AD797, the chip
The end CP of ADF4106 is electrically connected by concatenating the first RC network with the negative input of the chip AD797, the chip
The positive input of AD797 then passes through the second RC network and connects direct current 5V voltage, and the negative input of the chip AD797 also passes through
Third RC network is electrically connected with the output end of the chip AD797.
8. according to claim 7 for minimizing the frequency synthesizer of ODU receiving channel, which is characterized in that the pressure
Controlling oscillator includes chip SMV5000E, the output end electricity of the chip SMV5000E voltage input end and the chip AD797
Connection, the oscillator signal output end of the chip SMV5000E are connected to the RFin_ of the chip ADF4106 by resistor network
The end A.
9. according to claim 8 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the monolithic
Machine is chip ATTINY9, and three ends I/O of the chip ATTINY9 are connected respectively the enabled of the chip ADF4106
End, data terminal and clock end, and three ends I/O resistance in parallel and be grounded.
10. according to claim 9 for minimizing the local oscillation circuit of ODU receiving channel, which is characterized in that the local oscillator
Circuit further includes voltage conversion circuit, and 5V DC voltage is converted to 3.3V DC voltage by the voltage conversion circuit, and is divided
It is not independent to provide 3.3V DC-voltage supply to the chip ATTINY9 and chip ADF4106.
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