CN109104172B - Voltage-to-pulse width modulation signal circuit - Google Patents
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Abstract
A voltage to pulse width modulation signal circuit, comprising: an integrating filter, the positive input end of which inputs an external input voltage signal Vin, the negative input end of which inputs a high-frequency pulse width modulation signal PWM1, and the output end of which outputs a voltage signal VINTEG; a two-way clock signal generating circuit, the input end of which inputs a voltage signal VINTEG, and the output end of which outputs a first clock signal CLK0 and a second clock signal CLK 1; the arithmetic circuit has the input ends inputting the first clock signal CLK0 and the second clock signal CLK1, and the output ends outputting the high-frequency pulse width modulation signal PWM1 and the frequency modulation pulse width modulation signal PWM2, the average duty ratio of the high-frequency pulse width modulation signal PWM1 has a fixed arithmetic relation with the periods of the first clock signal CLK0 and the second clock signal CLK1, and the average duty ratio of the high-frequency pulse width modulation signal PWM1 is equal to the average duty ratio of the frequency modulation pulse width modulation signal PWM 2. The invention is a negative feedback system integrating an integrating circuit, and has the advantages of higher precision, stable system and easy calibration.
Description
Technical Field
The invention relates to the field of integrated circuits, in particular to a voltage-to-Pulse Width Modulation (PWM) signal circuit of an integrated algorithm in the field of analog signal processing.
Background
In many industrial control systems, a large class of applications require control of terminal equipment through analog signals, and terminals often use PWM signals as a control mode; another common application is that when an analog signal controls a terminal, the analog signal is often isolated in order to ensure safety and interference resistance between the analog signal and the terminal, and the isolation of the analog signal is also realized in a voltage-PWM-isolation-PWM-voltage manner, so that a voltage-to-PWM technology with high reliability and high precision is widely required.
At present, two mainstream voltage-to-PWM technologies are provided, wherein one technology is realized by an analog circuit formed by discrete components, and the other technology is realized by a singlechip chip integrated with an ADC (analog-to-digital converter). The former has numerous components, and errors are introduced into an operational amplifier, a capacitor, a resistor and the like, so that the system precision is not high, and the calibration is difficult. The latter single chip microcomputer is based on program operation, the system is easy to be interfered to cause instability, and the performance of the on-chip integrated ADC is not optimistic, so that the accuracy of the system is not controllable when the application environment is complex and the interference is more.
Disclosure of Invention
The invention provides a voltage-to-pulse width modulation signal circuit, which is a negative feedback system integrating an integrating circuit, and has the advantages of higher precision, stable system and easy calibration.
In order to achieve the above object, the present invention provides a voltage-to-pulse width modulation signal circuit, comprising:
an integrating filter having a positive input terminal receiving an external input voltage signal Vin, a negative input terminal receiving a high frequency pulse width modulation signal PWM1, and an output terminal outputting a voltage signal VINTEG；
A two-way clock signal generating circuit with input terminal for inputting voltage signal VINTEGOutput terminals thereof output a first clock signal CLK0 and a second clock signal CLK 1;
the arithmetic circuit has the input ends inputting the first clock signal CLK0 and the second clock signal CLK1, and the output ends outputting the high-frequency pulse width modulation signal PWM1 and the frequency modulation pulse width modulation signal PWM2, the average duty ratio of the high-frequency pulse width modulation signal PWM1 has a fixed arithmetic relation with the periods of the first clock signal CLK0 and the second clock signal CLK1, and the average duty ratio of the high-frequency pulse width modulation signal PWM1 is equal to the average duty ratio of the frequency modulation pulse width modulation signal PWM 2.
The integrating filter comprises: the operational amplifier is connected with a first resistor and a second resistor at the negative input end of the operational amplifier in series, a first integrating capacitor connected between the negative input end and the output end of the operational amplifier in series and a second integrating capacitor of which one end is connected with the first resistor and the second resistor and the other end is grounded;
the positive input end of the operational amplifier inputs an external input voltage signal Vin, and the negative input end thereof inputs a feedback signal VFBI.e. a high-frequency pulse-width modulated signal PWM1, the output of which outputs a voltage signal VINTEG。
The dual-clock signal generating circuit comprises:
a fixed frequency oscillator that outputs a fixed frequency second clock signal CLK 1;
voltage controlled oscillator with input voltage signal VINTEGAt a voltage signal VINTEGThe voltage controlled oscillator adaptively adjusts and outputs the first clock signal CLK0 having a proper frequency.
The output end of the arithmetic circuit also outputs a frequency modulation pulse width modulation signal PWM2, and the average duty ratio of the frequency modulation pulse width modulation signal PWM2 is equal to the average duty ratio of the high-frequency pulse width modulation signal PWM 1.
The arithmetic circuit comprises:
the input end of the frequency modulation pulse width modulation algorithm module inputs a first clock signal CLK0 and a second clock signal CLK1, and the output end of the frequency modulation pulse width modulation algorithm module outputs a frequency modulation pulse width modulation signal PWM2 as an output signal of the whole voltage-to-pulse width modulation signal circuit for a post-stage circuit to use;
and the high-frequency pulse width modulation algorithm module inputs the first clock signal CLK0 and the second clock signal CLK1 at the input end, and outputs a high-frequency pulse width modulation signal PWM1 to the negative input end of the integrating filter 101 at the output end for feedback control of the system.
The algorithm relationship between the average duty cycle of the high frequency pulse width modulation signal PWM1 and the first clock signal CLK0 and the second clock signal CLK1 includes:
DUTYPWM1＝DUTYPWM2＝k×T0/T1；
DUTYPWM1＝DUTYPWM2＝1-k×T0/T1；
DUTYPWM1＝DUTYPWM2＝(1-k×T0/T1)×2；
where DUTY is the average DUTY cycle, T0 is the period of the first clock signal CLK0, T1 is the period of the second clock signal CLK1, and k 1/2nAnd the variable n is an integer.
The average voltage of the high-frequency pulse width modulation signal PWM1 is equal to the voltage value of the external input voltage signal Vin input at the positive input terminal:
Vin＝VFBPWM1 average value DUTYPWM1×VREF++(1-DUTYPWM1)×VREF-；
Where Vin is the external input voltage, VREF+Is the high level, V, of the high frequency pulse width modulated signal PWM1REF-Is the low level of the high frequency pulse width modulated signal PWM 1.
The average duty cycle of the high frequency pulse width modulation signal PWM1 and the average duty cycle of the frequency modulated pulse width modulation signal PWM2 are linear with respect to the external input voltage: DUTYPWM1＝DUTYPWM2＝(Vin-VREF-)/(VREF+-VREF-)。
The frequency of the high-frequency pulse width modulation signal PWM1 and the frequency of the frequency modulation pulse width modulation signal PWM2 are in a multiple relation, the frequency of the high-frequency pulse width modulation signal PWM1 is F, the frequency of the frequency modulation pulse width modulation signal PWM2 is F/m, and m is an integer.
The invention is a negative feedback system integrating an integrating circuit, and has the advantages of higher precision, stable system and easy calibration.
Drawings
Fig. 1 is a circuit diagram of a voltage-to-pulse width modulation signal circuit provided by the present invention.
Fig. 2 is a circuit diagram of an integrating filter.
Fig. 3 is a circuit diagram of a two-way clock signal generating circuit.
Fig. 4 is a circuit diagram of an arithmetic circuit.
Detailed Description
The preferred embodiment of the present invention will be described in detail below with reference to fig. 1 to 4.
As shown in fig. 1, the present invention provides a voltage-to-pulse width modulation signal circuit, comprising:
an integrating filter 101 having a positive input terminal receiving an external input voltage signal Vin, a negative input terminal receiving a high frequency pulse width modulation signal PWM1, and an output terminal outputting a voltage signal VINTEG；
A two-way clock signal generating circuit 102 having an input terminal for inputting a voltage signal VINTEGOutput terminals thereof output a first clock signal CLK0 and a second clock signal CLK 1;
the arithmetic circuit 103 has inputs to which the first clock signal CLK0 and the second clock signal CLK1 are input, and an output to which the high-frequency pulse width modulation signal PWM1 and the frequency modulation pulse width modulation signal PWM2 are output.
An input voltage signal Vin is connected to the positive input terminal of the integrating filter 101, and a voltage signal V output from the integrator circuitINTEGThe two-way clock signal generating circuit 102 is controlled to generate two-way clock signals, namely a first clock signal CLK0 and a second clock signal CLK1, and the two-way clock signals generate two-way pulse width modulation signals after passing through the algorithm circuit 103, namely a high-frequency pulse width modulation signal PWM1 and a frequency modulation pulse width modulation signal PWM2, a high-frequency pulse width modulation signal PWM1 is connected to the negative input signal end of the integrator, so that negative feedback closed-loop control of the whole circuit is realized. The average duty ratio of the pulse width modulation signal (PWM) and the two paths of clock signals have an algorithm relation, and the amplification of the frequency of the pulse width modulation signal (PWM) can be realized according to application requirements under the condition of keeping the algorithm relation.
As shown in fig. 2, the integration filter 101 includes: the operational amplifier 202, the first resistor 204 and the second resistor 206 connected in series at the negative input end of the operational amplifier 202, the first integrating capacitor 203 connected in series between the negative input end and the output end of the operational amplifier 202, and the second integrating capacitor 205 with one end connected with the first resistor 204 and the second resistor 206 and the other end grounded, the resistor-capacitor string in the integrating filter realizes the function of a low-pass filter, and more resistor-capacitor strings (such as the connection mode of the first resistor and the first integrating capacitor) can be inserted at the input end in order to optimize the filtering effect. The integrating filter functions as follows: the first input signal is a voltage signal, the second input signal is a PWM signal, the output signal is a voltage signal, and when the system works normally, the average voltage of the PWM signal of the second input signal is equal to the voltage value of the first input signal.
The operational amplifier 202 has a positive input terminal receiving an external input voltage signal Vin and a negative input terminal receiving a feedback signal VFBI.e. a high-frequency pulse-width modulated signal PWM1, the output of which outputs a voltage signal VINTEG。
As shown in fig. 3, the two-way clock signal generating circuit 102 includes:
a fixed frequency oscillator 302 that outputs a fixed frequency second clock signal CLK 1;
a voltage-controlled oscillator 303 with an input terminal for a voltage signal VINTEGAt a voltage signal VINTEGThe voltage controlled oscillator 303 adaptively adjusts and outputs the first clock signal CLK0 having an appropriate frequency.
As shown in fig. 4, the arithmetic circuit 103 includes:
the input end of the fm PWM algorithm module 402 inputs the first clock signal CLK0 and the second clock signal CLK1, and the output end of the fm PWM algorithm module outputs the fm PWM signal PWM2 as the output signal of the entire voltage-to-PWM signal circuit for the use of the subsequent circuit;
the high frequency PWM algorithm module 403 has its inputs receiving the first clock signal CLK0 and the second clock signal CLK1, and its output outputting the high frequency PWM signal PWM1 to the negative input of the integrating filter 101 for feedback control of the system.
The average duty cycle of the high frequency pulse width modulated signal PWM1 is equal to the average duty cycle of the frequency modulated pulse width modulated signal PWM 2.
The average duty cycle of the high frequency pulse width modulated signal PWM1 has a fixed algorithmic relationship with the period of the first clock signal CLK0 and the second clock signal CLK 1:
DUTYPWM1＝DUTYPWM2＝k×T0/T1；
or, DUTYPWM1＝DUTYPWM2＝1-k×T0/T1；
Or, DUTYPWM1＝DUTYPWM2＝(1-k×T0/T1)×2；
Where DUTY is the average DUTY cycle, T0 is the period of the first clock signal CLK0, T1 is the period of the second clock signal CLK1, and k 1/2nAnd the variable n is an integer.
The integration filter 101 makes the average voltage of the high frequency pulse width modulation signal PWM1 equal to the external input voltage:
Vin＝VFBPWM1 average value DUTYPWM1×VREF++(1-DUTYPWM1)×VREF-；
Where Vin is the external input voltage, VREF+Is the high level, V, of the high frequency pulse width modulated signal PWM1REF-Is the low level of the high frequency pulse width modulated signal PWM 1.
Then DUTYPWM1＝DUTYPWM2＝(Vin-VREF-)/(VREF+-VREF-)；
That is, the average duty ratio of the high-frequency pulse width modulation signal PWM1 and the average duty ratio of the frequency modulation pulse width modulation signal PWM2 are in a linear relationship with the external input voltage, and high-precision frequency-adjustable voltage-to-pulse width modulation signal (PWM) output is realized.
With DUTYPWM1＝DUTYPWM2For example, (1-T0/T1). times.2, let VREF-0V, Vin is (1-T0/T1) × 2 × VREF++ 0V; when Vin is equal to VREF+Then DUTYPWM1＝DUTYPWM2100%, T0/T1 0.5; when Vin is 0V, DUTYPWM1＝DUTYPWM20%, T0/T1 1; when Vin is equal to V REF+2, then DUTYPWM1＝DUTYPWM2＝50％，T0/T1＝0.75。
The frequency of the high-frequency pulse width modulation signal PWM1 and the frequency of the frequency modulation pulse width modulation signal PWM2 are in a multiple relation, the frequency of the high-frequency pulse width modulation signal PWM1 is F, the frequency of the frequency modulation pulse width modulation signal PWM2 is F/m, m is an integer, and the value of m can be adjusted according to the requirements of a rear-stage circuit.
The invention is a negative feedback system integrating an integrating circuit, and has the advantages of higher precision, stable system and easy calibration.
While the present invention has been described in detail with reference to the preferred embodiments, it should be understood that the above description should not be taken as limiting the invention. Various modifications and alterations to this invention will become apparent to those skilled in the art upon reading the foregoing description. Accordingly, the scope of the invention should be determined from the following claims.
Claims (7)
1. A voltage to pulse width modulation signal circuit, comprising:
an integrating filter (101) having a positive input terminal receiving an external input voltage signal Vin, a negative input terminal receiving a high frequency pulse width modulation signal PWM1, and an output terminal outputting a voltage signal VINTEG；
A two-way clock signal generating circuit (102) having an input terminal for inputting a voltage signal VINTEGOutput terminals thereof output a first clock signal CLK0 and a second clock signal CLK 1;
an arithmetic circuit (103) having inputs for inputting the first clock signal CLK0 and the second clock signal CLK1 and an output for outputting the high frequency pulse width modulated signal PWM1 and the frequency modulated pulse width modulated signal PWM2, the average duty cycle of the frequency modulated pulse width modulated signal PWM2 being equal to the average duty cycle of the high frequency pulse width modulated signal PWM1, the average duty cycle of the high frequency pulse width modulated signal PWM1 having an arithmetic relationship with the periods of the first clock signal CLK0 and the second clock signal CLK 1;
the algorithm relationship between the average duty ratio of the high-frequency pulse width modulation signal PWM1 and the first clock signal CLK0 and the second clock signal CLK1 is as follows:
DUTYPWM1＝DUTYPWM2＝K×T0/T1；
or, DUTYPWM1＝DUTYPWM2＝1-K×T0/T1；
Or, DUTYPWM1＝DUTYPWM2＝(1-k×T0/T1)×2；
Wherein, DUTYPWM1Is the average DUTY cycle, DUTY, of the high frequency pulse width modulated signal PWM1PWM2Is the average duty cycle of the fm PWM signal PWM2, T0 is the period of the first clock signal CLK0, T1 is the period of the second clock signal CLK1, k 1/2nAnd the variable n is an integer.
2. The voltage to pulse width modulation signal circuit of claim 1, wherein the integrating filter (101) comprises: the operational amplifier (202), connect in series the first resistance (204) and second resistance (206) of the negative input end of the operational amplifier (202), connect in series the first integral capacitor (203) between negative input end and output end of the operational amplifier (202), and one end connects the first resistance (204) and second resistance (206), the second integral capacitor (205) of the earthing of another end;
the positive input end of the operational amplifier (202) inputs an external input voltage signal Vin, and the negative input end thereof inputs a feedback signal VFBI.e. a high-frequency pulse-width modulated signal PWM1, the output of which outputs a voltage signal VINTEG。
3. The voltage to pulse width modulation signal circuit of claim 1, wherein said two-way clock signal generating circuit (102) comprises:
a fixed frequency oscillator (302) that outputs a fixed frequency second clock signal CLK 1;
a voltage controlled oscillator (303) having an input terminal for a voltage signal VINTEGAt a voltage signal VINTEGControls the voltage controlled oscillator (303) to adaptively adjust the output of the first clock signal CLK0 having an appropriate frequency.
4. The voltage to pulse width modulation signal circuit of claim 1, wherein the algorithm circuit (103) comprises:
the input end of the frequency modulation pulse width modulation algorithm module (402) inputs a first clock signal CLK0 and a second clock signal CLK1, and the output end of the frequency modulation pulse width modulation algorithm module outputs a frequency modulation pulse width modulation signal PWM2 as an output signal of the whole voltage-to-pulse width modulation signal circuit for a post-stage circuit to use;
and the high-frequency pulse width modulation algorithm module (403) inputs the first clock signal CLK0 and the second clock signal CLK1, and outputs a high-frequency pulse width modulation signal PWM1 to the negative input end of the integrating filter (101) for the feedback control of the system.
5. The voltage-to-pulse width modulation signal circuit of claim 1, wherein the average voltage of the high frequency pulse width modulation signal PWM1 is equal to the voltage value of the external input voltage signal Vin input at its positive input terminal:
Vin＝VFBPWM1 average value DUTYPWM1×VREF++(1-DUTYPWM1)×VREF-；
Where Vin is the external input voltage, VFBIs a feedback signal, VREF+Is the high level, V, of the high frequency pulse width modulated signal PWM1REF-Is the low level of the high frequency pulse width modulated signal PWM 1.
6. The voltage-to-pulse width modulation signal circuit of claim 1, wherein the average duty cycle of the high frequency pulse width modulation signal PWM1 and the average duty cycle of the frequency modulated pulse width modulation signal PWM2 are linear with respect to the external input voltage: DUTYPWM1＝DUTYPWM2＝(Vin-VREF-)/(VREF+-VREF-)。
7. The voltage-to-pulse width modulation signal circuit of claim 1, wherein the frequency of the high frequency PWM signal PWM1 is a multiple of the frequency modulated PWM signal PWM2, the frequency of the high frequency PWM signal PWM1 is F, the frequency of the frequency modulated PWM signal PWM2 is F/m, and m is an integer.
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| CN201811107827.7A CN109104172B (en) | 2018-09-21 | 2018-09-21 | Voltage-to-pulse width modulation signal circuit |
| PCT/CN2019/104381 WO2020057371A1 (en) | 2018-09-21 | 2019-09-04 | Voltage-to-pulse width modulation signal circuit |
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| CN201811107827.7A CN109104172B (en) | 2018-09-21 | 2018-09-21 | Voltage-to-pulse width modulation signal circuit |
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| US5397945A (en) * | 1992-08-04 | 1995-03-14 | Samsung Semiconductor, Inc. | Duty cycle control circuit |
| CN101610086A (en) * | 2008-06-20 | 2009-12-23 | 瑞昱半导体股份有限公司 | The integral triangle modulator and the correlation technique thereof of may command output speed |
| CN101958691A (en) * | 2008-10-31 | 2011-01-26 | 成都芯源系统有限公司 | Class D audio amplifier and method |
| CN102948078A (en) * | 2010-04-23 | 2013-02-27 | Pr电子公司 | A delta sigma modulator |
| CN205142179U (en) * | 2015-11-23 | 2016-04-06 | 常熟理工学院 | Low frequency analog signal keeps apart change power transmission way |
| CN107645233A (en) * | 2016-07-20 | 2018-01-30 | 德州仪器公司 | For producing the method and circuit of pulse-width signal |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100725985B1 (en) * | 2006-06-02 | 2007-06-08 | 삼성전자주식회사 | High-linearity modulation system and modulation method |
| CN109104172B (en) * | 2018-09-21 | 2021-08-17 | 上海客益电子有限公司 | Voltage-to-pulse width modulation signal circuit |
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Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397945A (en) * | 1992-08-04 | 1995-03-14 | Samsung Semiconductor, Inc. | Duty cycle control circuit |
| CN101610086A (en) * | 2008-06-20 | 2009-12-23 | 瑞昱半导体股份有限公司 | The integral triangle modulator and the correlation technique thereof of may command output speed |
| CN101958691A (en) * | 2008-10-31 | 2011-01-26 | 成都芯源系统有限公司 | Class D audio amplifier and method |
| CN102948078A (en) * | 2010-04-23 | 2013-02-27 | Pr电子公司 | A delta sigma modulator |
| CN205142179U (en) * | 2015-11-23 | 2016-04-06 | 常熟理工学院 | Low frequency analog signal keeps apart change power transmission way |
| CN107645233A (en) * | 2016-07-20 | 2018-01-30 | 德州仪器公司 | For producing the method and circuit of pulse-width signal |
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Effective date of registration: 20220803 Address after: 201306 building C, No. 888, Huanhu West 2nd Road, Lingang New Area, Pudong New Area, Shanghai Patentee after: SHANGHAI XIANJI INTEGRATED CIRCUIT CO.,LTD. Address before: 201210 room 415, No. 2, Lane 666, China (Shanghai) pilot Free Trade Zone, Pudong New Area, Shanghai Patentee before: SHANGHAI GUESTGOOD ELECTRONICS Co.,Ltd. |