CN109103144B - Array substrate, preparation method thereof and display panel - Google Patents
Array substrate, preparation method thereof and display panel Download PDFInfo
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- CN109103144B CN109103144B CN201810972621.4A CN201810972621A CN109103144B CN 109103144 B CN109103144 B CN 109103144B CN 201810972621 A CN201810972621 A CN 201810972621A CN 109103144 B CN109103144 B CN 109103144B
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70216—Mask projection systems
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
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- Condensed Matter Physics & Semiconductors (AREA)
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- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Liquid Crystal (AREA)
Abstract
The invention provides an array substrate, a preparation method thereof and a display panel, belongs to the technical field of display, and can solve the problem that signals cannot be normally transmitted when two metal wires are connected together due to insufficient exposure between the two metal wires. According to the preparation method of the array substrate, the plurality of strip-shaped bulges arranged at intervals are arranged in the formed insulating layer, the bulges can be used for heightening the part of the metal layer formed subsequently, namely the bulges corresponding to the metal layer can be closer to an exposure machine, so that the exposure is larger, and the connection condition between the adjacent metal wires formed after exposure can not occur.
Description
Technical Field
The invention belongs to the technical field of display, and particularly relates to an array substrate, a preparation method of the array substrate and a display panel.
Background
The liquid crystal display panel includes a display (Active Area) Area and a wiring (Fan-out) Area at the edge of the display Area. With the development of display technologies, display products need to achieve a perfect visual effect with a narrow-bezel, full-screen design, which requires a reduction in the line pitch of the wiring area. When the wiring design reaches the resolution limit of the exposure machine, defects are easy to occur in the wiring area, such as insufficient exposure or failure to be exposed between two adjacent metal wires, which can cause that the two wires are connected together and cannot normally transmit signals.
Disclosure of Invention
The invention provides an array substrate, a preparation method thereof and a display panel, aiming at the problem that the two wires cannot normally transmit signals when the two wires are connected together due to insufficient exposure between the two existing metal wires.
The technical scheme adopted for solving the technical problem of the invention is as follows:
a preparation method of an array substrate comprises the following preparation steps:
forming an insulating layer on a substrate, wherein at least part of the edge of the substrate comprises a wiring area; in the wiring area, the surface of the insulating layer, which is far away from the substrate, is provided with a plurality of strip-shaped bulges arranged at intervals;
forming a metal layer over the insulating layer after the step;
and patterning the metal layer of the wiring area, so that the exposure quantity received in the patterning process at the position between two corresponding bulges and the position of the corresponding bulge of the metal layer are different.
Optionally, the size of the protrusion in the direction perpendicular to the surface of the substrate is in the range of 200-4000 angstroms.
Optionally, the forming the insulating layer includes the following steps:
forming an insulating coating on a substrate by using an insulating material;
and patterning the insulating coating by using a half-tone exposure process to obtain the insulating layer with a plurality of strip-shaped bulges on the surface of the wiring area, which is far away from the substrate.
Optionally, the size of the insulating coating in the direction perpendicular to the substrate surface is in the range of 4200-8000 angstrom.
Optionally, a metal line is formed at a position of the metal layer corresponding to the two protrusions, so that a space of the metal line is formed at the position of the metal layer corresponding to the two protrusions; the distance between two adjacent metal lines is 1-10 μm, and the line width of the metal lines is 1-10 μm.
Optionally, the patterning of the metal layer in the wiring area is performed by exposing the metal layer in the wiring area with a mask, the mask includes a plurality of mask strips which are spliced, two adjacent mask strips have overlapping edges, and the insulating layer is provided with the strip-shaped protrusion at a position corresponding to the overlapping edges.
Optionally, a plurality of metal lines arranged at intervals are formed at positions of the metal layer corresponding to the protrusions, a distance between two adjacent protrusions is 70-120 μm, and a width of the protrusion is 5-40 μm.
Optionally, the insulating layer is a gate insulating layer, the metal line is a data line, and the method further includes:
forming a gate electrode in the display region before forming the gate insulating layer;
and forming an active layer and a pixel electrode between the gate insulating layer and the metal layer.
The invention also provides an array substrate prepared by the method.
The invention also provides a display panel comprising the array substrate.
Drawings
Fig. 1 is a schematic top view of an array substrate prepared by the method of example 1 of the present invention;
fig. 2 is a schematic flow chart of an array substrate prepared by the method of embodiment 1 of the present invention;
FIG. 3 is a schematic block diagram of a flow chart of an array substrate prepared by the method of example 2 of the present invention;
fig. 4 is a schematic cross-sectional view of a part of an array substrate manufactured by the method of embodiment 2 of the present invention;
FIG. 5 is a partial cross-sectional view of another array substrate prepared by the method of example 2 of the present invention;
wherein the reference numerals are: 1. a substrate; 2. a wiring area; 30. a gate insulating layer; 3. an insulating layer; 31. a protrusion; 4. a metal layer; 40. a metal wire.
Detailed Description
In order to make the technical solutions of the present invention better understood, the present invention will be described in further detail with reference to the accompanying drawings and specific embodiments.
Example 1:
the embodiment provides a method for manufacturing an array substrate, as shown in fig. 1 and 2, including the following steps:
forming an insulating layer 3 on a substrate 1, said substrate 1 comprising, at the location of at least part of the edge, a wiring region 2; in the wiring area 2, the surface of the insulating layer 3, which is far away from the substrate 1, is provided with a plurality of strip-shaped bulges 31 arranged at intervals;
forming a metal layer 4 over the insulating layer 3 where the above steps are completed;
the metal layer 4 of the wiring region 2 is patterned so that the exposure amount received during the patterning is different at a position between two corresponding bumps 31 and at a position of the corresponding bump 31 of the metal layer 4.
In the method for manufacturing an array substrate of this embodiment, the insulating layer 3 is formed with a plurality of strip-shaped protrusions 31 arranged at intervals, and the protrusions 31 can lift up a part of the metal layer 4 formed subsequently, which is equivalent to that the metal layer 4 is closer to the exposure machine corresponding to the position of the protrusion 31, so that the exposure amount is larger, and thus, after exposure, no connection occurs between the adjacent metal lines 40.
Example 2:
the embodiment provides a method for manufacturing an array substrate, as shown in fig. 3 and 4, including the following steps:
optionally, at S01, a pattern including a Gate and a Gate line is formed through a patterning process using a Gate Mask (Gate Mask). The grid is formed in the display area, and the grid line is formed in the wiring area on the periphery of the display area.
Optionally, S02, forming a pattern including the active layer in the display area by using a patterning process on the substrate after the above steps are completed; specifically, a polysilicon film may be formed first, then a layer of photoresist may be formed on the polysilicon film, the photoresist may be exposed and developed, and then the polysilicon film may be dry etched to form a pattern including an active layer.
Optionally, S03, forming a pixel electrode in the display region on the substrate after the above steps are completed; specifically, the transparent conductive metal film may be formed first, and a pattern including the pixel electrode may be formed by using a patterning process. The transparent conductive metal film is formed of at least one transparent conductive material such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), or indium gallium tin oxide (InGaSnO).
And S04, forming a gate insulating layer 30 on the substrate after the above steps are completed, wherein in the wiring region, the surface of the gate insulating layer 30, which faces away from the substrate 1, is provided with a plurality of strip-shaped bulges 31 arranged at intervals.
As an alternative implementation in the present embodiment, the forming of the gate insulating layer 30 includes the following preparation steps:
s04a, forming an insulating coating on the substrate by adopting an insulating material; specifically, the insulating coating may be formed by a plasma enhanced chemical vapor deposition method, a low pressure chemical vapor deposition method, an atmospheric pressure chemical vapor deposition method, an electron cyclotron resonance chemical vapor deposition method, or a sputtering method.
More specifically, the size of the insulating coating in the direction perpendicular to the substrate surface is in the range of 4200-8000 angstrom.
That is, compared to the prior art, the thickness of the insulating coating in the present embodiment is thicker, for example, if the thickness of the insulating coating in the prior art is 4000 angstroms, the thickness of the insulating coating in the present embodiment is increased by about 200 angstroms and about 4000 angstroms, wherein the increased thickness portion is used for forming the stripe-shaped protrusion 31 in the following.
S04b, patterning the insulating coating by using a halftone exposure process, so as to obtain the gate insulating layer 30 having a plurality of stripe-shaped protrusions 31 on the surface of the wiring region 2 facing away from the substrate 1.
Specifically, a halftone mask including a non-transmission region, a semi-transmission region, and a transmission region may be used in the step. The via hole of the gate insulating layer 30 corresponds to the transmissive region, the metal line 40 of the wiring region 2 corresponds to the non-transmissive region, and the metal lines 40 correspond to the semi-transmissive region. After the gate insulating layer 30 is exposed and etched for one time, ashing is carried out, and etching is carried out again until the thickness of the gate insulating layer 30 corresponding to the position of the metal wire 40 is 4000 angstroms and the thickness of the gate insulating layer 30 corresponding to the position of the protrusion 31 is 4200-8000 angstroms; i.e. in the direction perpendicular to the plane of the substrate 1, the size of the protrusion 31 is in the range of 200-4000 angstroms.
S05a, forming a source drain metal layer above the gate insulation layer 30 after the step is completed; specifically, the source-drain metal electrode film may be formed using at least one of molybdenum, a molybdenum-niobium alloy, aluminum, an aluminum-neodymium alloy, titanium, or copper.
S05b, patterning the metal layer of the wiring region 2 to form metal lines 40 at positions of the metal layer corresponding to two bumps 31 and to form spaces of the metal lines 40 at positions of the metal layer corresponding to the bumps 31.
In one embodiment, as shown in FIG. 4, the spacing h1 between two adjacent metal lines is 1-10 μm, and the line width h2 of the metal lines is 1-10 μm.
That is, in the present embodiment, one protrusion corresponds to the interval between two metal lines, i.e., one metal line is defined between two adjacent protrusions.
The inventor finds that, in the mask manufacturing process in the prior art, a laser is generally divided into a plurality of scanning areas along the Y direction of the mask and then the mask is drawn, and the scanning areas of two adjacent mask strips are overlapped to a certain extent so as to ensure the formation of a mask pattern; therefore, a plurality of overlapping areas generate periodic difference, after exposure, the exposure amount of the position corresponding to the overlapping area is insufficient, and two lines are connected together and cannot normally transmit signals.
As an optional implementation in this embodiment, the patterning of the metal layer in the wiring region 2 is performed by exposing the metal layer in the wiring region 2 with a mask, where the mask includes a plurality of mask strips, two adjacent mask strips have overlapping edges, and the insulating layer 3 is provided with the strip-shaped protrusions 31 at positions corresponding to the overlapping edges.
In the embodiment, the strip-shaped protrusions 31 are correspondingly arranged at the positions which are easy to cause the insufficient exposure, so that the problem of insufficient periodic exposure caused by the overlapping of the scanning areas of two adjacent mask strips can be solved.
Specifically, a pattern including a source electrode, a drain electrode, and a data line may be formed by a single patterning process. The source and drain electrodes are formed in the display region, and the data line is formed in the wiring region 2 around the display region.
As shown in fig. 4, in the present embodiment, the protrusion 31 of the gate insulating layer 30 is used to raise a portion of the source/drain metal layer, which is equivalent to that the protrusion 31 can make the position of the source/drain metal layer corresponding to the protrusion 31 closer to the exposure machine, so that the exposure amount is larger, and thus, after exposure, no connection occurs between adjacent metal lines 40, and the distance between the metal data lines that can be formed is h 1.
In another embodiment, as shown in fig. 5, a plurality of metal lines are formed at intervals at the positions of the corresponding protrusions of the metal layer, the distance between two adjacent protrusions is 70-120 μm, and the width of the protrusion is 5-40 μm.
That is, one protrusion formed by the method of this embodiment corresponds to a plurality of data lines, and the width of the protrusion is 5 to 40 μm. It will be appreciated that adjacent two of the projections define a plurality of wires therebetween.
Optionally, S06, forming a passivation layer on the substrate 1 after the above steps are completed; specifically, the passivation film may be formed first, and then a pattern including the passivation layer may be formed by using a one-step patterning process.
Optionally, S07, forming a common electrode on the substrate 1 after the above steps are completed; specifically, the transparent conductive metal film may be formed first, and then a pattern including the common electrode may be formed by using a patterning process. The transparent conductive metal film is formed of at least one transparent conductive material such as Indium Gallium Zinc Oxide (IGZO), Indium Zinc Oxide (IZO), Indium Tin Oxide (ITO), or indium gallium tin oxide (InGaSnO).
In the drawings corresponding to the present embodiment, the size, thickness, and the like of each structural layer shown in the drawings are only schematic. In the process implementation, the projection areas of the structural layers on the substrate can be the same or different, and the required projection areas of the structural layers can be realized through an etching process; meanwhile, the structure shown in the drawings is not limited to the geometric shape of each structural layer, and may be, for example, a rectangle shown in the drawings, a trapezoid, or other shapes formed by etching, and may also be realized by etching.
Example 3:
the embodiment provides an array substrate which is prepared and formed by adopting the method.
The array substrate of the embodiment comprises a substrate, an insulating layer arranged above the substrate and a metal wire arranged above the insulating layer; the metal wire is formed by the aid of the strip-shaped bulges, so that the metal wire is formed at the position between the two bulges, and the interval of the metal wire is formed at the position corresponding to the bulge. The connection between adjacent metal wires of the array substrate of the embodiment does not occur.
Example 4:
the embodiment provides a display panel, which comprises any one of the array substrates. The display array substrate may be: the display device comprises any product or component with a display function, such as a liquid crystal display panel, electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
It will be understood that the above embodiments are merely exemplary embodiments taken to illustrate the principles of the present invention, which is not limited thereto. It will be apparent to those skilled in the art that various modifications and improvements can be made without departing from the spirit and substance of the invention, and these modifications and improvements are also considered to be within the scope of the invention.
Claims (9)
1. The preparation method of the array substrate is characterized by comprising the following preparation steps of:
forming an insulating layer on a substrate, wherein at least part of the edge of the substrate comprises a wiring area; in the wiring area, the surface of the insulating layer, which is far away from the substrate, is provided with a plurality of strip-shaped bulges arranged at intervals;
forming a metal layer over the insulating layer after the step;
patterning the metal layer of the wiring area to enable the position of the metal layer corresponding to two bulges to be different from the exposure received in the patterning process at the position of the corresponding bulge;
the step of patterning the metal layer of the wiring area is to expose a mask to pattern the metal layer of the wiring area, the mask comprises a plurality of spliced mask strips, two adjacent mask strips are provided with overlapping edges, and the insulating layer is provided with strip-shaped bulges corresponding to the overlapping edges;
and a plurality of metal wires arranged at intervals are formed at the positions of the metal layer corresponding to the bulges.
2. The method as claimed in claim 1, wherein the protrusion has a dimension in the range of 200-4000 angstroms in a direction perpendicular to the surface of the substrate.
3. The method for manufacturing the array substrate according to claim 1, wherein the forming the insulating layer comprises the following steps:
forming an insulating coating on a substrate by using an insulating material;
and patterning the insulating coating by using a half-tone exposure process to obtain the insulating layer with a plurality of strip-shaped bulges on the surface of the wiring area, which is far away from the substrate.
4. The method as claimed in claim 3, wherein the insulating layer has a dimension in the range of 4200 and 8000 Angstrom in the direction perpendicular to the substrate.
5. The method for manufacturing the array substrate according to claim 1, wherein a metal line is formed at a position between two corresponding protrusions of the metal layer, so that a space of the metal line is formed at the position of the corresponding protrusion of the metal layer; the distance between two adjacent metal lines is 1-10 μm, and the line width of the metal lines is 1-10 μm.
6. The method for preparing the array substrate of claim 1, wherein the pitch between two adjacent protrusions is 70-120 μm, and the width of the protrusions is 5-40 μm.
7. The method for manufacturing an array substrate according to claim 1, wherein the insulating layer is a gate insulating layer, and the metal line is a data line, the method further comprising:
forming a gate electrode in the display region before forming the gate insulating layer;
and forming an active layer and a pixel electrode between the gate insulating layer and the metal layer.
8. An array substrate prepared by the method of any one of claims 1 to 7.
9. A display panel comprising the array substrate according to claim 8.
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| CN107026121A (en) * | 2017-05-17 | 2017-08-08 | 京东方科技集团股份有限公司 | Preparation method, array base palte and the display device of array base palte |
| CN108321088A (en) * | 2018-02-05 | 2018-07-24 | 京东方科技集团股份有限公司 | Manufacturing method, touch base plate and the display device of touch base plate |
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| CN106024808A (en) * | 2016-06-08 | 2016-10-12 | 京东方科技集团股份有限公司 | Array substrate and preparation method therefor, and display device |
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| CN107026121A (en) * | 2017-05-17 | 2017-08-08 | 京东方科技集团股份有限公司 | Preparation method, array base palte and the display device of array base palte |
| CN108321088A (en) * | 2018-02-05 | 2018-07-24 | 京东方科技集团股份有限公司 | Manufacturing method, touch base plate and the display device of touch base plate |
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