CN109087682B - Global memory sequence detection system and method - Google Patents
Global memory sequence detection system and method Download PDFInfo
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- CN109087682B CN109087682B CN201710447322.4A CN201710447322A CN109087682B CN 109087682 B CN109087682 B CN 109087682B CN 201710447322 A CN201710447322 A CN 201710447322A CN 109087682 B CN109087682 B CN 109087682B
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- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
Abstract
The invention provides a system and a method for detecting the sequence of a global memory. The system comprises: the input instruction monitor is used for sending the information of the instruction to the instruction execution state recorder when monitoring that a new instruction is transmitted to the access memory unit; the Cache monitor, the write Cache monitor and the bus monitor are used for monitoring the operation condition of each memory access unit on the instruction and transmitting the monitored information to the instruction execution state recorder; the instruction execution state recorder is used for recording state information of the instruction, analyzing whether the instruction is executed completely or not, updating the state information of the instruction when the instruction is executed completely and sending the updated state information to the sequence detection unit; and the sequence detection unit is used for detecting whether the instructions are finished according to the correct sequence according to the state information of the instructions and the state information of all the executing instructions. The invention can dynamically and accurately detect whether the global memory executes the access instruction according to the specified correct sequence in real time.
Description
Technical Field
The invention relates to the technical field of CPU design, in particular to a system and a method for detecting the sequence of a global memory.
Background
An Advanced RISC Machine (ARM) architecture has strict regulations on the execution sequence of memory access instructions, in order to achieve higher performance and ensure the correctness of the memory sequence, particularly the memory access instruction operation, when a multi-core processor is designed, hardware can ensure the memory sequence according to ARMv8 architecture specifications, and in order to verify that the behaviors and constraints specified by ARMv8 are correctly executed between the multi-core processors, a powerful logic detection and error correction tool is required.
The increase in processor system performance may improve overall throughput or provide a better user experience. Increasing processor CPU core data in a system may increase the total number of instructions for a multi-core processor system, however, rather than merely interconnecting multiple processors, it is desirable to divide multiple tasks and programs so that they span parallel execution processing resources.
Multithreading supports simultaneous or staggered execution of multiple threads, and threads in the same multithreading program share the same resources including memory as part of the execution of the same process. With multi-threaded processing, multiple programs share cache memory so that data or instructions for one thread can overwrite data or instructions for another thread, which increases the probability of cache misses.
Memory consistency refers to a read operation returning the value of the last write operation to the memory location. In a single core processor system, the "last time" is the last memory operation that occurred in the program. In the multi-core processor shared memory system, the multi-core processor performs interleaving operation, so that the value returned by the read operation cannot be guaranteed to be the last written value in the program. Maintaining memory coherency is therefore a major difficulty in multi-core processor sharing systems.
The multi-core processor system may use hardware or a combination of hardware and software to maintain memory coherency. The hardware design can guarantee the memory order, and ensure that the order requirement of the access of the program memory is guaranteed according to the requirement of an ARMv8 architecture in a system layer of the multi-core processor. There are also some multi-core processor systems that may be limited by software constraints to ensure that memory ordering requirements are guaranteed at a desired time.
The current application software programs have higher and higher requirements on the memory operation sequence, so that the synchronization between different software programs or multiple tasks of the same software program and the use of effective memory instructions are required to be executed according to the execution sequence specified by the ARMv8 architecture. The guarantee of effective memory ordering is very important to the performance of the processor, and once a memory ordering problem occurs, problem location and development progress are difficult.
The prior scheme is to use a software simulation mode to verify the sequence of a memory, write a constraint model in a manual mode and simultaneously carry out random test with constraint, verify the sequence of the memory and feed back the correctness and the defects of a protocol.
In the process of implementing the invention, the inventor finds that at least the following technical problems exist in the prior art:
the scheme cannot dynamically cover the detection of all application scenes of a real system in real time, and cannot dynamically and accurately detect the correctness of the execution result of the memory access unit in real time.
Disclosure of Invention
The system and the method for detecting the sequence of the global memory can dynamically and accurately detect whether the global memory executes the memory access instruction according to the specified correct sequence in real time.
In a first aspect, the present invention provides a system for detecting the order of a global memory, which comprises an input instruction monitor, a Cache monitor, a write Cache monitor, a bus monitor, an instruction execution state recorder and an order detection unit,
the input instruction monitor is used for monitoring an instruction input port of the memory access unit in the design to be verified, and when a new instruction is transmitted to the memory access unit, acquiring the information of the instruction and transmitting the information to the instruction execution state recorder;
the Cache monitor, the write Cache monitor and the bus monitor are used for monitoring the operation condition of each memory access unit in the design to be verified on the instruction and transmitting the monitored information to the instruction execution state recorder;
the instruction execution state recorder is used for recording the state information of the instruction sent by the input instruction monitor, analyzing whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and updating the state information of the instruction and sending the updated state information to the sequence detection unit when the instruction is executed;
and the sequence detection unit is used for detecting whether the instructions are finished according to a correct sequence according to the state information of the instructions sent by the instruction execution state recorder and the state information of all the instructions which are executed in the instruction execution state recorder.
Optionally, the state information of the instruction includes an instruction type, an instruction issue number, an instruction issue time, an instruction completion number, an instruction completion time, an instruction completion event, an instruction completion flag, and an instruction valid bit.
Optionally, the instruction execution state recorder is configured to analyze whether the instruction completion event occurs according to information monitored by the Cache monitor, the write Cache monitor, and the bus monitor, and if the instruction completion event occurs, it indicates that the instruction has been executed.
Optionally, the instruction execution state recorder is configured to update an instruction completion flag, an instruction completion time, an instruction completion number, and an instruction completion event of the instruction when the instruction has been executed and completed.
Optionally, the instruction execution state recorder is further configured to delete the state information of the instruction when the instruction has been executed.
In a second aspect, the present invention provides a method for detecting a global memory sequence, including:
the input instruction monitor monitors an instruction input port of an access unit in the design to be verified, and when a new instruction is transmitted to the access unit, the input instruction monitor acquires the information of the instruction and transmits the information to an instruction execution state recorder;
the Cache monitor, the write Cache monitor and the bus monitor the operation condition of each memory access unit in the design to be verified on the instruction, and transmit the monitored information to the instruction execution state recorder;
the instruction execution state recorder records the state information of the instruction sent by the input instruction monitor, analyzes whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, updates the state information of the instruction when the instruction is executed, and sends the state information to the sequence detection unit;
and the sequence detection unit detects whether the instructions are finished according to a correct sequence according to the state information of the instructions sent by the instruction execution state recorder and the state information of all the instructions being executed in the instruction execution state recorder.
Optionally, the state information of the instruction includes an instruction type, an instruction issue number, an instruction issue time, an instruction completion number, an instruction completion time, an instruction completion event, an instruction completion flag, and an instruction valid bit.
Optionally, the analyzing whether the instruction is executed and completed according to the information monitored by the Cache monitor, the write Cache monitor, and the bus monitor includes: and analyzing whether the instruction completion event occurs according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and if the instruction completion event occurs, indicating that the instruction is executed completely.
Optionally, the updating the state information of the instruction includes: and updating the instruction completion mark, the instruction completion time, the instruction completion number and the instruction completion event of the instruction.
Optionally, after the updating the state information of the instruction and sending the updated state information to the sequence detection unit, the method further includes:
and the instruction execution state recorder deletes the state information of the instruction.
The system and the method for detecting the sequence of the global memory provided by the embodiment of the invention do not need to write a complex global memory sequence model, can dynamically cover the detection of all application scenes of a real system in real time, accurately detect whether the global memory executes the memory access instruction according to a specified correct sequence, make up the defects of low efficiency, long development period and high complexity of the traditional verification method based on a software simulation mode, and shorten the chip design and verification period. When an error occurs, the designer can be informed of the error instruction address, the error time, the error data and the correct data, and meanwhile, the reason of the error can be automatically analyzed, so that the designer is helped to quickly locate the problem.
Drawings
FIG. 1 is a schematic structural diagram of a global memory sequence detection system according to an embodiment of the present invention;
FIG. 2 is a diagram illustrating an instruction status entry in an instruction execution status recorder according to an embodiment of the present invention;
FIG. 3 is a flowchart illustrating a sequential detection unit for performing global memory sequential detection according to an embodiment of the present invention;
fig. 4 is a flowchart of a method for detecting a global memory sequence according to an embodiment of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The ARMv8 architecture has specific requirements on access memory behavior, and designing a processor compatible with ARMv8 needs to ensure that the execution of all access instructions is in accordance with the behavior and constraints specified by ARMv 8. The ARMv8 architecture has detailed requirements on execution order for different memory instructions and different types of memory.
The memory order check is to verify that the designed CPU conforms to the ARMv8 architecture definition in terms of execution order. If the CPU design violates ARMv8 architectural specifications and constraints, memory order detection will detect an error and report which instruction violates the ARMv8 protocol specification.
An embodiment of the present invention provides a system for detecting a global memory sequence, as shown in fig. 1, where the system includes an input instruction monitor, a Cache monitor, a write Cache monitor, a bus monitor, an instruction execution state recorder, and a sequence detection unit,
the input instruction monitor is used for monitoring an instruction input port of a memory access unit in the design to be verified, acquiring information of an instruction and sending the information to the instruction execution state recorder when a new instruction is transmitted to the memory access unit, setting an instruction effective bit to be high, and allocating the instruction to a transmission sequence number;
the Cache monitor, the write Cache monitor and the bus monitor are used for monitoring the operation condition of each memory access unit in the design to be verified on the instruction, acquiring the completion state of the instruction and transmitting the monitored information to the instruction execution state recorder;
the instruction execution state recorder is used for recording the state information of the instruction sent by the input instruction monitor, analyzing whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and updating the state information of the instruction and sending the updated state information to the sequence detection unit when the instruction is executed;
the state information of the instruction includes an instruction type, an instruction transmission number, instruction transmission time, an instruction completion number, instruction completion time, an instruction completion event, an instruction completion flag, and an instruction valid bit, and the specific state content is as shown in fig. 2.
Specifically, in the instruction execution state recorder, there is a data structure that can record the states of 1024 instructions at the same time. Each instruction state entry includes the following:
an instruction valid bit indicating whether an instruction has been launched into an input port of the CPU access unit;
the instruction transmitting number indicates that when the input instruction monitor finds a new instruction, a transmitting number is allocated to the instruction, and the transmitting number is stored in the instruction execution state recorder along with other information of the instruction;
an instruction issue time, representing a time at which an instruction is issued to the memory access unit;
an instruction completion number indicating that an instruction completion number is assigned when the instruction is detected to have been executed in the design to be verified;
an instruction completion time representing a time at which execution of the instruction is completed;
an instruction completion event, which represents a flag when the instruction execution is completed, for example, a flag when the access instruction hits the Cache or a request for accessing the instruction is accepted by an external device;
and an instruction completion flag indicating a flag indicating completion of execution of the instruction.
The instruction transmission number and the instruction completion number are calculated as follows: there are two global variables in the instruction execution state recorder, which are a current transmission number and a current completion number, respectively, where the current transmission number represents a currently unused minimum transmission number, and the current completion number represents an unused minimum completion number. When a new instruction is issued, the current issue number is assigned to the instruction, and the current issue number is automatically incremented by 1, and when an instruction is marked as completed, the current completion number is assigned to the instruction, and the current completion number is automatically incremented by 1.
Specifically, the instruction execution state recorder is configured to analyze whether the instruction completion event occurs according to information monitored by the Cache monitor, the write Cache monitor, and the bus monitor, and if the instruction completion event occurs, it indicates that the instruction has been executed.
And the instruction execution state recorder is used for updating the instruction completion mark, the instruction completion time, the instruction completion number and the instruction completion event of the instruction when the instruction is completely executed.
And the sequence detection unit is used for detecting whether the instructions are finished according to a correct sequence according to the state information of the instructions sent by the instruction execution state recorder and the state information of all the instructions which are executed in the instruction execution state recorder.
Further, when an instruction is marked as complete, the instruction execution state logger may set the instruction valid bit of the instruction low, indicating that the instruction has been executed and may delete the instruction from the instruction execution state logger.
Regarding the completion of the execution of the instruction, different instructions have different completion events, which is specifically described as follows:
(1) a Load (access) instruction, which cannot be changed any more if the return value of the Load instruction is determined, indicating that the Load instruction has been completed, for example, the Load instruction hits the Cache and takes data from the Cache, or the Load instruction bypasses data of a Store instruction from a write Cache monitor, or the Load instruction issues a request to the bus, and the bus accepts the request;
(2) a Store instruction, wherein if the Store instruction is written into the Cache from the write Cache monitor, the Store instruction execution is completed, and the instruction completion flag is set to high;
(3) a DMB (Data Memory Barrier) instruction, wherein after the DMB instruction executes the pipeline in the Memory access unit, the DMB instruction represents that the DMB instruction is executed, and an instruction completion mark is set to be high;
(4) a DSB (Data Synchronization Barrier) instruction, when it is evicted from the write buffer, indicates that execution of the DSB instruction is complete and the instruction completion flag is set high.
Specifically, the sequence detection unit will perform sequence detection on the completed instructions, and the flow of the detection is shown in fig. 3:
in step S101, when an instruction is marked as complete, the sequence detection unit obtains information of the instruction.
Step S102, determining whether the instruction is for accessing the device type memory, if so, executing step S103, otherwise, executing step S104.
In step S103, the sequence detection unit detects the device type access instruction with the instruction valid bit being high and the instruction completion flag being low in the instruction execution state recorder, and goes to step S107.
Step S104, detecting whether the instruction is a special instruction of DMB, DSB, STLR (Segment-table Length Register) type, if so, executing step S105, otherwise, executing step S106.
Step S105, the sequence detection unit detects that all the instruction valid bits are high and the instruction completion flag bit is low, and then the step S107 is carried out;
step S106, the sequence detection unit detects DMB, DSB, LDA instructions with all instruction valid bits high and instruction completion flag bits low, and goes to step S107.
And step S107, judging whether the emission sequence number of the instruction is smaller than that of the finished instruction, if so, printing an error report, otherwise, returning to the step S101.
If none of the above checks are problematic, the sequential checking of the instructions is complete.
The global memory sequence detection system provided by the embodiment of the invention does not need to write a complex global memory sequence model, can dynamically cover the detection of all application scenes of a real system in real time, accurately detects whether the global memory executes the memory access instruction according to a specified correct sequence, overcomes the defects of low efficiency, long development period and high complexity of the traditional verification method based on a software simulation mode, and shortens the chip design and verification period. When an error occurs, the designer can be informed of the error instruction address, the error time, the error data and the correct data, and meanwhile, the reason of the error can be automatically analyzed, so that the designer is helped to quickly locate the problem.
An embodiment of the present invention further provides a method for detecting a global memory sequence, as shown in fig. 4, where the method includes:
s201, an input instruction monitor monitors an instruction input port of a memory access unit in the design to be verified, and when a new instruction is transmitted to the memory access unit, information of the instruction is collected and sent to an instruction execution state recorder.
S202, a Cache monitor, a write Cache monitor and a bus monitor the operation condition of each memory access unit in the design to be verified on the instruction, and transmit the monitored information to the instruction execution state recorder.
S203, the instruction execution state recorder records the state information of the instruction sent by the input instruction monitor, analyzes whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and updates the state information of the instruction and sends the state information to the sequence detection unit when the instruction is executed.
The state information of the instruction comprises an instruction type, an instruction transmitting number, instruction transmitting time, an instruction finishing number, instruction finishing time, an instruction finishing event, an instruction finishing mark and an instruction effective bit.
Specifically, the instruction execution state recorder may analyze whether the instruction completion event occurs according to information monitored by the Cache monitor, the write Cache monitor, and the bus monitor, and if the instruction completion event occurs, it indicates that the instruction has been executed.
Specifically, the updating, by the instruction execution state recorder, the state information of the instruction includes: and updating the instruction completion mark, the instruction completion time, the instruction completion number and the instruction completion event of the instruction.
S204, the sequence detection unit detects whether the instructions are finished according to a correct sequence according to the state information of the instructions sent by the instruction execution state recorder and the state information of all the instructions being executed in the instruction execution state recorder.
Further, after the updating the state information of the instruction and sending the state information to the sequence detection unit, the method further comprises:
and the instruction execution state recorder deletes the state information of the instruction.
The method for detecting the sequence of the global memory provided by the embodiment of the invention does not need to write a complex global memory sequence model, can dynamically cover the detection of all application scenes of a real system in real time, accurately detects whether the global memory executes the memory access instruction according to a specified correct sequence, overcomes the defects of low efficiency, long development period and high complexity of the traditional verification method based on a software simulation mode, and shortens the chip design and verification period. When an error occurs, the designer can be informed of the error instruction address, the error time, the error data and the correct data, and meanwhile, the reason of the error can be automatically analyzed, so that the designer is helped to quickly locate the problem.
It will be understood by those skilled in the art that all or part of the processes of the methods of the embodiments described above can be implemented by a computer program, which can be stored in a computer-readable storage medium, and when executed, can include the processes of the embodiments of the methods described above. The storage medium may be a magnetic disk, an optical disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), or the like.
The above description is only for the specific embodiment of the present invention, but the scope of the present invention is not limited thereto, and any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope of the present invention are included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (10)
1. A global memory sequence detection system is characterized in that the system comprises an input instruction monitor, a Cache monitor, a write Cache monitor, a bus monitor, an instruction execution state recorder and a sequence detection unit, wherein,
the input instruction monitor is used for monitoring an instruction input port of the memory access unit in the design to be verified, and when a new instruction is transmitted to the memory access unit, acquiring the information of the instruction and transmitting the information to the instruction execution state recorder;
the Cache monitor, the write Cache monitor and the bus monitor are used for monitoring the operation condition of each memory access unit in the design to be verified on the instruction and transmitting the monitored information to the instruction execution state recorder;
the instruction execution state recorder is used for recording the state information of the instruction sent by the input instruction monitor, analyzing whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and updating the state information of the instruction and sending the updated state information to the sequence detection unit when the instruction is executed;
and the sequence detection unit is used for comparing the transmitting sequence number of the finished instruction with the transmitting sequence number of the unfinished instruction according to different instruction types and judging whether the instructions are finished according to the correct sequence.
2. The system of claim 1, wherein the status information of the instruction comprises an instruction type, an instruction issue number, an instruction issue time, an instruction completion number, an instruction completion time, an instruction completion event, an instruction completion flag, and an instruction valid bit.
3. The system according to claim 2, wherein the instruction execution state recorder is configured to analyze whether the instruction completion event occurs according to information monitored by the Cache monitor, the write Cache monitor, and the bus monitor, and if the instruction completion event occurs, indicate that the instruction has been executed.
4. The system of claim 3, wherein the instruction execution state logger is configured to update an instruction completion flag, an instruction completion time, an instruction completion number, and an instruction completion event for the instruction when the instruction has completed execution.
5. The system of claim 4, wherein the instruction execution status logger is further configured to delete the status information of the instruction when the instruction has completed execution.
6. A global memory sequence detection method is characterized by comprising the following steps:
the input instruction monitor monitors an instruction input port of an access unit in the design to be verified, and when a new instruction is transmitted to the access unit, the input instruction monitor acquires the information of the instruction and transmits the information to an instruction execution state recorder;
the Cache monitor, the write Cache monitor and the bus monitor the operation condition of each memory access unit in the design to be verified on the instruction, and transmit the monitored information to the instruction execution state recorder;
the instruction execution state recorder records the state information of the instruction sent by the input instruction monitor, analyzes whether the instruction is executed or not according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, updates the state information of the instruction when the instruction is executed, and sends the state information to the sequence detection unit;
the sequence detection unit compares the transmission sequence number of the finished instruction with the transmission sequence number of the unfinished instruction according to different instruction types, and judges whether the instructions are finished according to a correct sequence.
7. The method of claim 6, wherein the state information of the instruction comprises an instruction type, an instruction issue number, an instruction issue time, an instruction completion number, an instruction completion time, an instruction completion event, an instruction completion flag, and an instruction valid bit.
8. The method of claim 7, wherein analyzing whether the instruction has been executed and completed according to the information monitored by the Cache monitor, the write Cache monitor, and the bus monitor comprises: and analyzing whether the instruction completion event occurs according to the information monitored by the Cache monitor, the write Cache monitor and the bus monitor, and if the instruction completion event occurs, indicating that the instruction is executed completely.
9. The method of claim 8, wherein updating the state information of the instruction comprises: and updating the instruction completion mark, the instruction completion time, the instruction completion number and the instruction completion event of the instruction.
10. The method of claim 9, wherein after the updating and sending the state information of the instruction into the order detection unit, the method further comprises:
and the instruction execution state recorder deletes the state information of the instruction.
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