CN102880770A - Central processing unit (CPU) access sequence simulation model based on macro-instruction queue - Google Patents
Central processing unit (CPU) access sequence simulation model based on macro-instruction queue Download PDFInfo
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Abstract
The invention discloses a central processing unit (CPU) access sequence simulation model based on a macro-instruction queue. The CPU access sequence simulation model comprises an instruction buffer module, a secondary cache and elimination buffer module, a secondary request processing module, a flow control module, an instruction scheduling module and an instruction decoding module, wherein the instruction buffer module comprises instruction buffers of which the number is the same as that of the suspended buffers in a Cache non-hit request inside the CPU, wherein the transmitted instruction carries a buffer number where the instruction buffers are positioned by utilizing the redundant field, so that the correctness is checked according to the instruction buffer number returned by the original response sample; the secondary cache and elimination buffer module is used for simulating the operation of secondary cache and elimination buffer and checking the validity of the secondary request and response; the secondary request processing module is used for simulating the processing function of the secondary request, receiving the secondary request and returning the response of corresponding types; the flow control module is used for simulating the flow control functions of the primary request queue and response queue; the instruction scheduling module is used for scheduling an instruction from multiple instruction buffers for execution; and the instruction decoding module is used for executing conversion from an instruction format of the instruction buffers to a format packet of logic interfaces between the CPU and consistency protocol hardware.
Description
Technical field
The present invention relates to the computing technique field, more particularly, the present invention relates to a kind of CPU memory access sequence realistic model based on the macro instruction formation.
Background technology
Develop rapidly along with semiconductor fabrication process, the dominant frequency of single core processor has been approached the limit gradually, in order further to improve the arithmetic speed of processor, people are integrated in a plurality of processor cores and form on-chip multi-processor (Chip Multi one Processor, CMP) on the chip.
In CMP, a plurality of processor cores are shared so that the contradiction of the gaps between their growth rates between processor and the primary memory is more outstanding the single internal memory space, therefore the CMP design must be adopted multilevel cache (Cache), alleviates this contradiction by the storage organization of stratification.The CMP system must solve Cache consistency problem and the consistency checking problem that causes therefrom.
The Cache consistency protocol directly has influence on correctness design and the performance of polycaryon processor as the important component part in the polycaryon processor, and Cache consistency protocol verification technique becomes one of the gordian technique in polycaryon processor design verification stage.
The checking of consistency protocol need to have a CPU model to come the memory access behavior of emulation CPU, and real CPU model is very complicated.So, be desirable to provide a kind of CPU memory access sequence realistic model carrying out can simplifying when consistency protocol verified the true CPU model.
Summary of the invention
Technical matters to be solved by this invention is for there being defects in the prior art, and a kind of CPU memory access sequence realistic model based on the macro instruction formation carrying out can simplifying when consistency protocol verified the true CPU model is provided.
According to the present invention, a kind of CPU memory access sequence realistic model based on the macro instruction formation is provided, it comprises: the instruction buffer module, it comprises the Cache a plurality of instruction buffers that hit requests suspension buffering number quantity is not identical with CPU inside, the instruction of sending utilizes redundant field to carry the buffering number of place instruction buffer, so that this instruction buffer that returns according to the response former state number carries out Correctness checking; Second-level cache and superseded buffer module are used for the simulation second-level cache and eliminate the operation of buffering, and the legitimacy of secondary request and response is checked; The secondary request processing module is used for simulation to the processing capacity of secondary request, receives secondary request, and returns replying of respective type; The Flow Control module is used for simulating the Flow Control function of a request queue and response queue; The instruction scheduling module is used for carrying out from instruction of a plurality of instruction buffer scheduling; Instruction decode module is used for carrying out instruction buffer order format to the conversion of the form bag of the logic interfacing between CPU and the consistency protocol hardware.
Preferably, load one group of instruction sequence in each instruction buffer, the instruction sequences of filling in the instruction buffer module will satisfy the real behavior rule of CPU.
Preferably, load the instruction sequence that a group address has correlativity in each instruction buffer, the instruction in the same instruction buffer is launched by serial, only has last instruction to receive after the response instruction after the just emission.
Preferably, the transmission that can circulate of the instruction in each instruction buffer of instruction buffer module.
Preferably, the instruction of different instruction buffer does not have address correlations, parallel emission.
Preferably, test and excitation is configured to Random Test Stimulus or the special test and excitation of focus.
Preferably, the Flow Control module is used for controlling, so that when only having a response of once asking to return, have the next one of address correlations once to ask and could send from CPU.
Preferably, the Flow Control module is used for controlling, if so that a request queue in the consistency protocol hardware logic has not had the space, cpu instruction can not be launched.
Preferably, the Flow Control module is used for controlling, if so that the response queue of CPU inside does not have the space, then the response in the consistency protocol hardware logic can't be returned, and corresponding once request also can't be finished processing.
Preferably, the time-delay that secondary request is processed and response unloads can be configured to fixed value or random value, to simulate different congestion situations.
Thus, the invention provides a kind of CPU memory access sequence realistic model based on the macro instruction formation carrying out to simplify when consistency protocol verified the true CPU model.
Description of drawings
By reference to the accompanying drawings, and by with reference to following detailed description, will more easily to the present invention more complete understanding be arranged and more easily understand its advantage of following and feature, wherein:
Fig. 1 schematically shows the CPU memory access sequence realistic model based on the macro instruction formation according to the embodiment of the invention.
Need to prove that accompanying drawing is used for explanation the present invention, and unrestricted the present invention.
Embodiment
In order to make content of the present invention more clear and understandable, below in conjunction with specific embodiments and the drawings content of the present invention is described in detail.
When carrying out consistency protocol verified, the embodiment of the invention has made up a CPU simplified model based on the macro instruction formation, comes the memory access behavior of emulation CPU.
Be provided with a plurality of instruction buffers in this model, can fill in according to testing requirement a request sequence of memory access in the buffering, the instruction sequence between a plurality of instruction buffers can be launched at random or according to specified order.Whole model construction is comparatively simple, and manual compiling instruction sequence control excitation can be carried out specially testing to focus, also can carry out random test.
And this model is only simulated the cpu instruction excitation relevant with consistency protocol, relative true CPU model, and model is simple, and full software programming more is added with preferably can be handling, can test preferably the various extreme cases of consistency protocol.
Specifically, Fig. 1 schematically shows the CPU memory access sequence realistic model MODEL1 based on the macro instruction formation that software is realized that passes through according to the embodiment of the invention.The main body of this CPU memory access sequence realistic model MODEL1 is a plurality of instruction buffers, the verifier can fill in different cpu instruction sequences according to testing requirement, the instruction sequences of wherein filling in will satisfy the real behavior rule of CPU, and the instruction sequence between a plurality of instruction buffers can be launched at random or according to specified order by instruction scheduling.
Generally speaking, CPU has the bag of four kinds of different Virtual Channels mutual with the consistency protocol hardware logic: once request, the replying of response, secondary request and secondary request of request once.Emission situation for real simulation cpu instruction, CPU memory access sequence realistic model MODEL1 not only wants the emission of consistance request that is virtually reality like reality, also need to simulate consistency function relevant with the consistance processing element among the CPU, can jointly finish complete process flow to consistency protocol with consistency protocol hardware module H1 thus.
More particularly, as shown in Figure 1, comprise according to the CPU memory access sequence realistic model MODEL1 based on the macro instruction formation of the embodiment of the invention:
Instruction buffer module: comprise the Cache instruction buffer that hit requests suspension buffering number quantity is not identical with CPU inside; Specifically, if the Cache of CPU inside not hit requests to hang the buffering number be n, then the instruction buffer number corresponding be set to n (the first instruction buffer 1, the second instruction buffer 2 ... n instruction buffer n); And, can load the relevant instruction sequence of a group address in each instruction buffer, there is not any address correlationship between the instruction of different bufferings, emission can walk abreast; Instruction is the random schedule emission between instruction buffer, or launches according to specified order.The complete serial emission of instruction process in each instruction buffer is sent out next instruction after the response of i.e. previous instruction is returned again.Executing instructions between instruction buffer.The transmission capable of circulation of each instruction buffer.The instruction of sending utilizes redundant field to carry the buffering number of place instruction buffer, also can carry this instruction buffer number (, request and response thereof carry identical buffering number) when response is returned, and carries out Correctness checking with this.And the instruction sequences of filling in the instruction buffer module will satisfy the real behavior rule of CPU.
Second-level cache and superseded buffer module M1: be used for the simulation second-level cache and eliminate the operation of buffering, and the legitimacy of secondary request and response is checked; Specifically, some cpu instruction can cause second-level cache and eliminate the action of buffering, therefore needs the simulation correlation function, and the legitimacy of secondary request and response is checked.
Secondary request processing module M2: once ask for some, consistency protocol can generate secondary request and mail to CPU, CPU should return and reply, this module simulation to the processing capacity of secondary request, receive secondary request, and return replying of respective type, so that processing, consistance is able to complete carrying out.
Flow Control module M3: the Flow Control function of having simulated a request queue and response queue; Specifically, for example, Flow Control module M3 controls, so that when only having a response to return, could send from CPU the next instruction of identical address, so the restriction that whether can launch the request address that not yet is disposed of the instruction in the instruction buffer; In addition, Flow Control module M3 controls, if so that a request queue among the consistency protocol hardware logic H1 has not had the space, cpu instruction can not be launched; And Flow Control module M3 controls, if so that the response queue of CPU inside does not have the space, then the response among the consistency protocol hardware logic H1 can't be returned, and corresponding once request also can't be finished processing.
Instruction scheduling module M4: from a plurality of instruction buffers, dispatch an instruction execution at random or according to specified order; As mentioned above, the instruction in the same instruction buffer is the relevant instruction in address, is entirely serial and carries out, an instruction after only having last instruction to receive just to carry out after the response, the executing instructions between different instruction buffer.
Instruction decode module M5: because what fill in is cpu instruction in the instruction buffer, and the processing of consistency protocol hardware logic is the consistency protocol bag, this module is responsible for finishing instruction buffer order format to the conversion of the form bag of the logic interfacing between CPU and the consistency protocol hardware, generates the manageable once request of consistency protocol hardware logic bag.
Thus, in the CPU memory access sequence realistic model MODEL1 based on the macro instruction formation according to the embodiment of the invention, but secondary request processing module M2 secondary request is processed with the time-delay flexible configuration of response unloading and is become fixed value also to can be configured to random value, to simulate different congestion situations, can realize thus multiple congestion situations test.
And in the CPU memory access sequence realistic model MODEL1 based on the macro instruction formation according to the embodiment of the invention, test and excitation can be configured to Random Test Stimulus and two kinds of patterns of the special test and excitation of focus;
1. Random Test Stimulus: what fill in each instruction buffer is at random excitation, relative " at random " specifically, the instruction sequences of namely filling in will satisfy the real behavior rule of CPU and the fill request of instruction buffer, some parameter of instruction can generate at random, instruction scheduling is arranged at random dispatch command from different instruction buffers, and the instruction that so each change is filled in or change random pattern can obtain a different set of CPU arbitrary excitation;
2. the special test and excitation of focus: for some function point of hardware logic, fill in the instruction sequence of particular sequence or particular address in the instruction buffer, the order of designated order scheduling generates the required specific instruction stream of verifier.
Can be configured to easily the test environment of single CPU or many CPU according to the embodiment of the invention based on the CPU memory access sequence realistic model MODEL1 of macro instruction formation.
The CPU memory access sequence realistic model MODEL1 based on the macro instruction formation according to the embodiment of the invention is simply controlled, specifically, the verifier need to fill the content in the instruction buffer at the beginning of checking, and after specifying the configuration parameter such as scheduling method, model can generate required instruction stream automatically, mailing to consistency protocol hardware logic H1 processes, in the instruction stream processing procedure if any behavior and expection repugnancy (instruction buffer at the instruction buffer that returns such as certain response number and corresponding requests instruction place number inconsistent) can automatically report an error stop to check on-the-spot, otherwise can finish rear check result at instruction stream, whole proof procedure does not need more human intervention.
Thus, as mentioned above, the above embodiment of the present invention provides a kind of CPU memory access sequence realistic model based on the macro instruction formation carrying out can simplifying when consistency protocol verified the true CPU model.
In addition, need to prove, unless otherwise indicated, otherwise the term in the instructions " first ", " second ", " the 3rd " etc. describe each assembly of only being used for distinguishing instructions, element, step etc., rather than are used for logical relation between each assembly of expression, element, the step or ordinal relation etc.
Be understandable that although the present invention with the preferred embodiment disclosure as above, yet above-described embodiment is not to limit the present invention.For any those of ordinary skill in the art, do not breaking away from the technical solution of the present invention scope situation, all can utilize the technology contents of above-mentioned announcement that technical solution of the present invention is made many possible changes and modification, or be revised as the equivalent embodiment of equivalent variations.Therefore, every content that does not break away from technical solution of the present invention according to any simple modification, equivalent variations and the modification that technical spirit of the present invention is done above embodiment, all still belongs in the scope of technical solution of the present invention protection.
Claims (10)
1. CPU memory access sequence realistic model based on the macro instruction formation is characterized in that comprising:
The instruction buffer module, it comprises the Cache a plurality of instruction buffers that hit requests suspension buffering number quantity is not identical with CPU inside, the instruction of sending utilizes redundant field to carry the buffering number of place instruction buffer, so that this instruction buffer that returns according to the response former state number carries out Correctness checking;
Second-level cache and superseded buffer module are used for the simulation second-level cache and eliminate the operation of buffering, and the legitimacy of secondary request and response is checked;
The secondary request processing module is used for simulation to the processing capacity of secondary request, receives secondary request, and returns replying of respective type;
The Flow Control module is used for simulating the Flow Control function of a request queue and response queue;
The instruction scheduling module is used for carrying out from instruction of a plurality of instruction buffer scheduling;
Instruction decode module is used for carrying out instruction buffer order format to the conversion of the form bag of the logic interfacing between CPU and the consistency protocol hardware.
2. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 is characterized in that, loads one group of instruction sequence in each instruction buffer, and the instruction sequences of filling in the instruction buffer module will satisfy the real behavior rule of CPU.
3. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2, it is characterized in that, load the instruction sequence that a group address has correlativity in each instruction buffer, instruction in the same instruction buffer is launched by serial, only has last instruction to receive after the response instruction after the just emission.
4. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2 is characterized in that, the transmission that can circulate of the instruction in each instruction buffer of instruction buffer module.
5. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2 is characterized in that the instruction of different instruction buffer does not have address correlations, and emission can walk abreast.
6. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2 is characterized in that, test and excitation can be configured to Random Test Stimulus or the special test and excitation of focus.
7. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2, it is characterized in that, the Flow Control module is used for controlling, so that when only having a response of once asking to return, have the next one of address correlations once to ask and could send from CPU.
8. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2, it is characterized in that, the Flow Control module is used for controlling, if so that a request queue in the consistency protocol hardware logic has not had the space, cpu instruction can not be launched.
9. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2, it is characterized in that, the Flow Control module is used for controlling, so that if the response queue of CPU inside does not have the space, then the response in the consistency protocol hardware logic can't be returned, and corresponding once request also can't be finished processing.
10. the CPU memory access sequence realistic model based on the macro instruction formation according to claim 1 and 2, it is characterized in that, the secondary request processing module secondary request can be processed and the time-delay of response unloading is configured to fixed value or random value, to simulate different congestion situations.
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