CN109085908A - A kind of implementation method and server that multichannel cpu power is synchronous - Google Patents

A kind of implementation method and server that multichannel cpu power is synchronous Download PDF

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Publication number
CN109085908A
CN109085908A CN201810813477.XA CN201810813477A CN109085908A CN 109085908 A CN109085908 A CN 109085908A CN 201810813477 A CN201810813477 A CN 201810813477A CN 109085908 A CN109085908 A CN 109085908A
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cpld
signal
transmission
gives
cpu
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CN201810813477.XA
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张文峰
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Shenzhen Guo Xinheng Space Science And Technology Ltd
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Shenzhen Guo Xinheng Space Science And Technology Ltd
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Priority to CN201810813477.XA priority Critical patent/CN109085908A/en
Publication of CN109085908A publication Critical patent/CN109085908A/en
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/266—Arrangements to supply power to external peripherals either directly from the computer or under computer control, e.g. supply of power through the communication port, computer controlled power-strips
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2273—Test methods
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
    • G06F11/2284—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing by power-on test, e.g. power-on self test [POST]

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  • Engineering & Computer Science (AREA)
  • General Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)

Abstract

A kind of multichannel cpu power provided by the invention synchronous implementation method and server, the method that signal communication between two CPLD is realized using CPLD simulation SGPIO, first CPLD transmits POWER_EN signal to the 2nd CPLD, the method that the POWER OK signal that first CPLD receives the 2nd CPLD carries out the transmission of next POWER EN again later, it solves to solve the unreliable of multi -CPU power supply synchronization in the prior art, it is asynchronous, complicated technical problem, realize that CPLD simulates SGPIO, the signal communication between two CPLD may be implemented, both simple, the synchronization of power supply can be reliably solved again, the technical effect being simple and efficient.

Description

A kind of implementation method and server that multichannel cpu power is synchronous
Technical field
The present invention relates to server fields, in particular to a kind of multichannel cpu power synchronous implementation method and service Device.
Background technique
The function of server is stronger and stronger, and integrated level is also higher and higher, and the interconnection technique of CPU is very mature, one The phenomenon that two CPU interconnection even four CPU, is more and more in a narrow space, and CPU's and affiliated memory power supply is multiple It is miscellaneous；On multi -CPU interconnected server, on each CPU and memory bar corresponding power supply need it is synchronous realize, and server is upper Electricity, which is substantially by CPLD, to be completed, and since the pin of CPLD is limited, and is possible to CPU not on the same mainboard, is needed It is attached by connector, so being all many times to realize powering on for multi -CPU by multiple CPLD, but how to solve Certainly not only simply but also reliably realize that synchronizing for power supply is a difficult point.
SGPIO is mainly used for the control of hard disk lamp, it one shares four signal wires, and one is clock signal Sclock, and one Root is to start over signal Sload, and one to be host send data signal line SdataOut to slave, and one is slave to host Send data signal line SdataIn.
Summary of the invention
The present invention provides a kind of implementation method and server that multichannel cpu power is synchronous, is realized using CPLD simulation SGPIO The method of signal communication between two CPLD, the first CPLD transmit POWER EN signal and receive to the 2nd CPLD, the first CPLD The method for carrying out the transmission of next POWER EN after to the POWER OK signal of the 2nd CPLD again, solution solve in the prior art Certainly multi -CPU power supply synchronization is unreliable, asynchronous, complicated technical problem.
The synchronous implementation method of this multichannel cpu power that the present invention provides to solve above-mentioned technical problem, including with Lower step,
Be switched on detecting step: booting is powered, and whether detection service device upper cover plate has CPU, if it is not, re-starting booting inspection Step is surveyed, if so, then carrying out rise and fall along step；
Rising edge failing edge step: the first CPLD sends clock to the 2nd CPLD, meanwhile, in first rising of Sclock Along when, high level is lower level by Sload, while SdataOut transmission S3 status information gives the 2nd CPLD, described First CPLD transmits the signal of P5V EN=1 to the 2nd CPLD, and receives the signal of the P5V PG of the 2nd CPLD, carries out Judge P5V PG step；
Judge P5V PG step: the first CPLD judges whether the signal value of the P5V PG is 1, if it is not, then transmission The signal of EN=0 P3V3 gives the 2nd CPLD, if it is, the transmission signal of P3V3 EN=1 gives the 2nd CPLD, and receives The signal of the P3V3 PG of 2nd CPLD carries out judging P3V3 PG step；
Judge P3V3 PG step: the first CPLD judges whether the signal value of the P3V3 PG is 1, if it is not, then passing The defeated signal of PVPP EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVPP EN=1 gives the 2nd CPLD, and receives The signal of the PVPP PG of 2nd CPLD carries out judging PVPP PG step；
Judge PVPP PG step: the first CPLD judges whether the signal value of the PVPP PG is 1, if it is not, then passing The defeated signal of PVDDQ EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVDDQ EN=1 gives the 2nd CPLD, and connects By the signal of the PVDDQ PG of the 2nd CPLD, carry out judging PVPP PG step；
Judge PVDDQ PG step: the first CPLD judges whether the signal value of the PVDDQ PG is 1, if it is not, then The signal of PVCCIO EN=0 is transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIO EN=1 gives the 2nd CPLD, And receive the signal of the PVCCIO PG of the 2nd CPLD, it carries out judging PVCCIO PG step；
Judge PVCCIO PG step: the first CPLD judges whether the signal value of the PVCCIO PG is 1, if it is not, The signal of PVCCIN EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIN EN=1 gives described second CPLD, and receive the signal of the PVCCIN PG of the 2nd CPLD, it carries out judging PVCCIN PG step；
Judge PVCCIN PG step: the first CPLD judges whether the signal value of the PVCCIN PG is 1, if it is not, The signal of PVCCSA EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCSA EN=1 gives described second CPLD, and receive the signal of the PVCCSA PG of the 2nd CPLD, it carries out judging PVCCSA PG step；
Judge PVCCSA PG step: the first CPLD judges whether the signal value of the PVCCSA PG is 1, if it is not, The PWRGD PCH signal of OK=0 is then transmitted to the 2nd CPLD, if it is, the transmission PWRGD PCH signal of OK=1 is to described 2nd CPLD carries out judging PWRGD CPUPWRGD step；
Judge PWRGD CPUPWRGD step: the first CPLD judges whether the signal value of the PWRGD CPUPWRGD is 1, If it is not, then the transmission PWRGD SYS signal of PWROK=0 gives the 2nd CPLD, and step is carried out, if it is transmission RST PLTRST N step then transmits the PWRGD SYS signal of PWROK=1 to the 2nd CPLD, carries out transmission RST PLTRST N step Suddenly；
Transmit RST PLTRST N step: the 2nd CPLD transmission RST PLTRST n-signal is tied to the first CPLD Beam.
First CPLD be the first CPU in CPLD, the 2nd CPLD be the 2nd CPU in CPLD, described first It is communicated between CPLD and the 2nd CPLD by simulating SGPIO, the SGPIO includes CLK signal line, SLOAD signal Line, the first CPLD data signal line, the 2nd CPLD data signal line, the SLOAD signal wire transmission starts over signal, described First CPLD data signal line transmits the data-signal of the first CPLD to the 2nd CPLD, the 2nd CPLD data letter Number line transmits the data-signal of the 2nd CPLD to the first CPLD.
It is communicated between first CPLD and the 2nd CPLD by Sclock, Sload, Sdataln, SdataOut.
First CPLD is connect with first power supply chip, and the first CPLD can transmit POWER EN signal to electricity Source chip, the power supply chip can transmit POWER OK signal to the first CPLD.
First CPLD is connect with the second source chip, and the first CPLD can transmit POWER EN signal to electricity Source chip, the power supply chip can transmit POWER OK signal to the first CPLD.
First power supply chip supplies electricity to the first CPU.
The second source chip supplies electricity to the 2nd CPU.
First CPLD described in the rising edge failing edge step sends the clock to described second by Sclock CPLD。
A kind of multichannel cpu server, the multichannel cpu server can be the step of realizing the method.
The utility model has the advantages that simulating SGPIO using CPLD possessed by of the invention, the signal that may be implemented between two CPLD is logical Letter, not only simply, but also can reliably solve the synchronization of power supply, be simple and efficient.
Detailed description of the invention
Fig. 1 is the connection schematic diagram between multichannel cpu power CPLD of the present invention.
Fig. 2 is the synchronous implementation method flow chart of multichannel cpu power of the present invention.
Specific embodiment
In conjunction with above-mentioned Detailed description of the invention specific embodiments of the present invention.
As shown in Figure 1, a kind of implementation method that multichannel cpu power is synchronous is provided by invention, comprising the following steps:
Be switched on detecting step: booting is powered, and whether detection service device upper cover plate has CPU, if it is not, re-starting booting inspection Step is surveyed, if so, then carrying out rise and fall along step；
Rising edge failing edge step: the first CPLD sends clock to the 2nd CPLD, meanwhile, in first rising of Sclock Along when, high level is lower level by Sload, while SdataOut transmission S3 status information gives the 2nd CPLD, described First CPLD transmits the signal of P5V EN=1 to the 2nd CPLD, and receives the signal of the P5V PG of the 2nd CPLD, carries out Judge P5V PG step；
Judge P5V PG step: the first CPLD judges whether the signal value of the P5V_PG is 1, if it is not, then transmission The signal of EN=0 P3V3 gives the 2nd CPLD, if it is, the transmission signal of P3V3 EN=1 gives the 2nd CPLD, and receives The signal of the P3V3 PG of 2nd CPLD carries out judging P3V3 PG step；
Judge P3V3 PG step: the first CPLD judges whether the signal value of the P3V3 PG is 1, if it is not, then passing The defeated signal of PVPP EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVPP EN=1 gives the 2nd CPLD, and receives The signal of the PVPP PG of 2nd CPLD carries out judging PVPP PG step；
Judge PVPP PG step: the first CPLD judges whether the signal value of the PVPP PG is 1, if it is not, then passing The defeated signal of PVDDQ EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVDDQ EN=1 gives the 2nd CPLD, and connects By the signal of the PVDDQ PG of the 2nd CPLD, carry out judging PVPP PG step；
Judge PVDDQ PG step: the first CPLD judges whether the signal value of the PVDDQ PG is 1, if it is not, then The signal of PVCCIO EN=0 is transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIO EN=1 gives the 2nd CPLD, And receive the signal of the PVCCIO PG of the 2nd CPLD, it carries out judging PVCCIO PG step；
Judge PVCCIO PG step: the first CPLD judges whether the signal value of the PVCCIO PG is 1, if it is not, The signal of PVCCIN EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIN EN=1 gives described second CPLD, and receive the signal of the PVCCIN PG of the 2nd CPLD, it carries out judging PVCCIN PG step；
Judge PVCCIN PG step: the first CPLD judges whether the signal value of the PVCCIN PG is 1, if it is not, The signal of PVCCSA EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCSA EN=1 gives described second CPLD, and receive the signal of the PVCCSA PG of the 2nd CPLD, it carries out judging PVCCSA PG step；
Judge PVCCSA PG step: the first CPLD judges whether the signal value of the PVCCSA PG is 1, if it is not, The PWRGD PCH signal of OK=0 is then transmitted to the 2nd CPLD, if it is, the transmission PWRGD PCH signal of OK=1 is to described 2nd CPLD carries out judging PWRGD CPUPWRGD step；
Judge PWRGD CPUPWRGD step: the first CPLD judges whether the signal value of the PWRGD CPUPWRGD is 1, If it is not, then the transmission PWRGD SYS signal of PWROK=0 gives the 2nd CPLD, and step is carried out, if it is transmission RST PLTRST N step then transmits the PWRGD SYS signal of PWROK=1 to the 2nd CPLD, carries out transmission RST PLTRST N step Suddenly；
Transmit RST PLTRST N step: the 2nd CPLD transmission RST PLTRST n-signal is tied to the first CPLD Beam.
First CPLD be the first CPU in CPLD, the 2nd CPLD be the 2nd CPU in CPLD, described first It is communicated between CPLD and the 2nd CPLD by simulating SGPIO, the SGPIO includes CLK signal line, SLOAD signal Line, the first CPLD data signal line, the 2nd CPLD data signal line, the SLOAD signal wire transmission starts over signal, described First CPLD data signal line transmits the data-signal of the first CPLD to the 2nd CPLD, the 2nd CPLD data letter Number line transmits the data-signal of the 2nd CPLD to the first CPLD.
It is communicated between first CPLD and the 2nd CPLD by Sclock, Sload, Sdataln, SdataOut.
First CPLD is connect with first power supply chip, and the first CPLD can transmit POWER EN signal to electricity Source chip, the power supply chip can transmit POWER OK signal to the first CPLD.
First CPLD is connect with the second source chip, and the first CPLD can transmit POWER EN signal to electricity Source chip, the power supply chip can transmit POWER OK signal to the first CPLD.
First power supply chip supplies electricity to the first CPU.
The second source chip supplies electricity to the 2nd CPU.
First CPLD described in the rising edge failing edge step sends the clock to described second by Sclock CPLD。
A kind of multichannel cpu server, the multichannel cpu server can be the step of realizing the method.
The synchronous implementation method of this multichannel cpu power provided by the invention has described the first of the first CPU CPLD is main CPLD, and as the host of SGPIO, the 2nd CPLD is as slave；Host sends CLK, and SLOAD starts over signal, Transmit first POWER EN signal；The slave receives the CLK, the SLOAD, the POWER EN signal it Afterwards, the POWER EN signal is parsed；The signal parsed is transmitted to the second source chip controls end by the slave, and The second source chip POWER OK signal is sent to the host；The host receive the POWER OK signal it Carry out the transmission of next POWER EN again afterwards.
SGPIO is mainly used for the control of hard disk lamp, it one shares four signal wires, and one is CLK, and one is to start over Signal, one to be host send data signal line to slave, and one is that slave to host sends data signal line.If using CPLD SGPIO is simulated, the signal communication between two CPLD may be implemented, not only simply, but also can reliably solve the synchronization of power supply, letter It is single efficient.
The above content is a further detailed description of the present invention in conjunction with specific preferred embodiments, and it cannot be said that Present invention specific implementation is only limited to these instructions, for those of ordinary skill in the art to which the present invention belongs, not Under the premise of being detached from present inventive concept, a number of simple deductions or replacements can also be made, all shall be regarded as belonging to the protection of invention Range.

Claims (9)

1. a kind of synchronous implementation method of multichannel cpu power, which comprises the following steps:
Be switched on detecting step: booting is powered, and whether detection service device upper cover plate has CPU, if it is not, re-starting booting inspection Step is surveyed, if so, then carrying out rise and fall along step；
Rising edge failing edge step: the first CPLD sends clock to the 2nd CPLD, meanwhile, in first rising of Sclock Along when, high level is lower level by Sload, while SdataOut transferring status data gives the 2nd CPLD, described the One CPLD transmits the signal of P5V EN=1 to the 2nd CPLD, and receives the signal of the P5V PG of the 2nd CPLD, is sentenced Disconnected P5V PG step；
Judge P5V PG step: the first CPLD judges whether the signal value of the P5V PG is 1, if it is not, then transmission The signal of EN=0 P3V3 gives the 2nd CPLD, if it is, the transmission signal of P3V3_EN=1 gives the 2nd CPLD, and receives The signal of the P3V3_PG of 2nd CPLD carries out judging P3V3 PG step；
Judge P3V3 PG step: the first CPLD judges whether the signal value of the P3V3 PG is 1, if it is not, then passing The defeated signal of PVPP EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVPP EN=1 gives the 2nd CPLD, and receives The signal of the PVPP PG of 2nd CPLD carries out judging PVPP PG step；
Judge PVPP PG step: the first CPLD judges whether the signal value of the PVPP PG is 1, if it is not, then passing The defeated signal of PVDDQ EN=0 gives the 2nd CPLD, if it is, the transmission signal of PVDDQ EN=1 gives the 2nd CPLD, and connects By the signal of the PVDDQ PG of the 2nd CPLD, carry out judging PVPP PG step；
Judge PVDDQ PG step: the first CPLD judges whether the signal value of the PVDDQ PG is 1, if it is not, then The signal of PVCCIO EN=0 is transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIO EN=1 gives the 2nd CPLD, And receive the signal of the PVCCIO PG of the 2nd CPLD, it carries out judging PVCCIO PG step；
Judge PVCCIO PG step: the first CPLD judges whether the signal value of the PVCCIO PG is 1, if it is not, The signal of PVCCIN EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCIN EN=1 gives described second CPLD, and receive the signal of the PVCCIN PG of the 2nd CPLD, it carries out judging PVCCIN PG step；
Judge PVCCIN PG step: the first CPLD judges whether the signal value of the PVCCIN PG is 1, if it is not, The signal of PVCCSA EN=0 is then transmitted to the 2nd CPLD, if it is, the transmission signal of PVCCSA EN=1 gives described second CPLD, and receive the signal of the PVCCSA PG of the 2nd CPLD, it carries out judging PVCCSA PG step；
Judge PVCCSA PG step: the first CPLD judges whether the signal value of the PVCCSA PG is 1, if it is not, The PWRGD PCH signal of OK=0 is then transmitted to the 2nd CPLD, if it is, the transmission PWRGD PCH signal of OK=1 is to described 2nd CPLD carries out judging PWRGD CPUPWRGD step；
Judge PWRGD CPUPWRGD step: the first CPLD judges whether the signal value of the PWRGD CPUPWRGD is 1, If it is not, then the transmission PWRGD SYS signal of PWROK=0 gives the 2nd CPLD, and step is carried out, if it is transmission RST PLTRST N step then transmits the PWRGD SYS signal of PWROK=1 to the 2nd CPLD, carries out transmission RST PLTRST N step Suddenly；
Transmit RST PLTRST N step: the 2nd CPLD transmission RST PLTRST n-signal is tied to the first CPLD Beam.
2. the synchronous implementation method of multichannel cpu power according to claim 1, it is characterised in that: the first CPLD is CPLD in first CPU, the 2nd CPLD are the CPLD in the 2nd CPU, between the first CPLD and the 2nd CPLD By simulate SGPIO communicated, the SGPIO include CLK signal line, SLOAD signal wire, the first CPLD data signal line, 2nd CPLD data signal line, the SLOAD signal wire transmission start over signal, the first CPLD data signal line transmission The data-signal of first CPLD gives the 2nd CPLD, and the 2nd CPLD data signal line transmits the 2nd CPLD's Data-signal gives the first CPLD.
3. the synchronous implementation method of multichannel cpu power according to claim 2, it is characterised in that: the first CPLD with It is communicated between 2nd CPLD by Sclock, Sload, Sdataln, SdataOut.
4. the synchronous implementation method of multichannel cpu power according to claim 1, it is characterised in that: the first CPLD with The first power supply chip connection, the first CPLD can transmit POWER EN signal to power supply chip, and the power supply chip can POWER OK signal is transmitted to the first CPLD.
5. the synchronous implementation method of multichannel cpu power according to claim 1, it is characterised in that: the first CPLD with The second source chip connection, the first CPLD can transmit POWER EN signal to power supply chip, and the power supply chip can POWER OK signal is transmitted to the first CPLD.
6. the synchronous implementation method of multichannel cpu power according to claim 4, it is characterised in that: the first power supply core Piece supplies electricity to the first CPU.
7. the synchronous implementation method of multichannel cpu power according to claim 5, it is characterised in that: the second source core Piece supplies electricity to the 2nd CPU.
8. the synchronous implementation method of multichannel cpu power according to claim 1, it is characterised in that: the rising edge decline The 2nd CPLD to is sent the clock by Sclock along the first CPLD described in step.
9. a kind of multichannel cpu server, it is characterised in that: the multichannel cpu server can be any in realization claim 1-8 The step of method described in item.
CN201810813477.XA 2018-07-23 2018-07-23 A kind of implementation method and server that multichannel cpu power is synchronous Withdrawn CN109085908A (en)

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CN201810813477.XA CN109085908A (en) 2018-07-23 2018-07-23 A kind of implementation method and server that multichannel cpu power is synchronous

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Application Number Priority Date Filing Date Title
CN201810813477.XA CN109085908A (en) 2018-07-23 2018-07-23 A kind of implementation method and server that multichannel cpu power is synchronous

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Inventor after: Zhang Wenfeng

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Application publication date: 20181225