CN109074780B

CN109074780B - Panel driving system and source driver

Info

Publication number: CN109074780B
Application number: CN201780026412.4A
Authority: CN
Inventors: 李相珉; 郑敏永; 金元; 崔正熙
Original assignee: Silicon Works Co Ltd
Current assignee: LX Semicon Co Ltd
Priority date: 2016-04-29
Filing date: 2017-04-11
Publication date: 2022-10-04
Anticipated expiration: 2037-04-11
Also published as: WO2017188625A1; KR102634474B1; CN109074780A; KR20170123973A

Abstract

The present invention provides a technique capable of adjusting the frequency of a sampling clock for pixel sensing according to configuration information.

Description

Panel driving system and source driver

Technical Field

The present disclosure relates to a technique for sensing a characteristic of a pixel disposed on a display panel and a technique for driving the display panel.

Background

The display device includes a panel driving device that controls the luminance of pixels disposed on a panel, such as a driving device including a source driver and a timing controller.

The panel driving device determines a data voltage according to image data and supplies the data voltage to the pixels, thereby controlling the luminance of each pixel.

Even when receiving the same data voltage, the luminance of the pixel may vary depending on the characteristics of the pixel. For example, a pixel includes a driving transistor, and when a threshold voltage of the driving transistor is changed, even though the same data voltage is supplied, the luminance of the corresponding pixel may be changed. If the panel driving apparatus does not consider such a characteristic change of the pixel, the pixel may be driven with an undesired luminance, resulting in deterioration of image quality.

In particular, the characteristics of the pixels may change over time or may vary depending on the surrounding environment. Here, when the panel driving device supplies the data voltage without considering the change characteristics of the pixels, deterioration of image quality, such as line defect, may occur.

To resolve the degradation of image quality, the display device may further include a pixel sensing device to sense the characteristics of the pixels. The pixel sensing device may periodically or aperiodically inspect the characteristics of each pixel and may emit the characteristics to the panel driving device. The panel driving device calibrates the data voltage in view of the characteristic value of each pixel emitted from the pixel sensing device, thereby solving the deterioration of image quality due to the characteristic change of the pixel.

The pixel sensing device may be configured as a stand-alone device, but may also be included in a source driver. In addition, the pixel sensing device can be included in a panel driving device to form a panel driving system.

The pixel sensing device periodically senses the pixels according to a sampling clock. When the frequency of the sampling clock exceeds the operating range of an Analog-to-Digital Converter (ADC) included in the pixel sensing device, the pixel sensing device may malfunction. In addition, electromagnetic Interference (EMI) noise may be inserted into the sensing data when the sampling clock has a frequency equal to or similar to a clock for image data.

Disclosure of Invention

Technical problem

In this context, aspects of the present disclosure will provide a technique capable of adjusting the frequency of a sampling clock for pixel sensing according to setting information.

Technical solution

To achieve the foregoing aspects, aspects of the present disclosure provide a source driver including a data driver, a clock generator, a sensor, and an output unit.

In the source driver, the data driver may generate the data voltage by converting image data received according to the first clock signal. The clock generator may generate a second clock signal having a frequency different from that of the first clock signal according to the external setting information. The sensor may periodically sense the pixel according to the second clock signal. The output unit may transmit sensing data regarding the pixels to the timing controller.

Another aspect of the present disclosure provides a panel driving system including a timing controller and a source driver.

In the panel driving system, the timing controller may receive sensing data with respect to each pixel, and may transmit an embedded clock signal including image data calibrated according to the sensing data. The source driver may receive an embedded clock signal from the timing controller, may recover the first clock signal, the control signal, and the image data by isolating the first clock signal, the control signal, and the image data from the received embedded clock signal, may generate a second clock signal having a frequency different from the first clock signal according to setting information included in the control signal, may generate sensing data by sensing pixels according to the second clock signal, and may transmit the generated sensing data to the timing controller.

ADVANTAGEOUS EFFECTS OF INVENTION

As described above, according to the present disclosure, it is possible to adjust the frequency of the sampling clock for pixel sensing according to the setting information. Further, according to the present disclosure, it is possible to prevent malfunction of a pixel sensing device (or a source driver and a panel driving system including the source driver) from occurring and reduce electromagnetic interference (EMI) noise.

Drawings

Fig. 1 illustrates a configuration of a display device according to an embodiment of the present disclosure.

Fig. 2 illustrates the structure of each pixel in fig. 1.

Fig. 3 illustrates a configuration of a source driver according to an embodiment of the present disclosure.

Fig. 4 illustrates an embodiment in which the clock generator obtains setting information.

Fig. 5 is a flow chart illustrating a first exemplary method for generating a second clock signal according to setup information and for transmitting and receiving sensing data and image data.

Fig. 6 is a flow chart illustrating a second exemplary method for generating a second clock signal according to setting information and for transmitting and receiving sensing data and image data.

Fig. 7 illustrates a first exemplary configuration of a clock generator.

Fig. 8 illustrates a second exemplary configuration of a clock generator.

Fig. 9 illustrates an exemplary configuration of the frequency synthesizer illustrated in fig. 8.

Fig. 10 illustrates a third exemplary configuration of the clock generator.

Fig. 11 illustrates waveforms of a plurality of reference signals generated in a CDR circuit.

Fig. 12 illustrates waveforms resulting from an exclusive-or operation of multiple reference signals.

Fig. 13 illustrates a fourth exemplary configuration of the clock generator.

Fig. 14 illustrates waveforms of the multiplied signals according to the example shown in fig. 13.

Detailed Description

Hereinafter, some embodiments of the present disclosure will be described in detail with reference to the illustrative drawings. It should be noted that, in terms of adding reference numerals to constituent elements in the drawings, similar constituent elements are denoted by similar reference numerals whenever possible even when shown in different drawings. In the following description of the present disclosure, when it is determined that a detailed description of a related known configuration or function makes the present disclosure ambiguous, the detailed description will be omitted accordingly.

In describing the constituent elements of the present disclosure, terms such as first, second, A, B, (a) and (b) may be used. These terms are only used to distinguish one constituent element from another constituent element, and are not intended to limit the nature, sequence, or order of the constituent elements. It will be understood that when a constituent element is described as being "coupled", "combined", or "connected" to another constituent element, the element may be directly coupled or connected to the other element, or intervening elements may also be "coupled", "combined", or "connected" to the element and the other element.

Referring to fig. 1, the display device (100) may include a panel (110), a source driver (120), a gate driver (130), and a timing controller (140).

A plurality of Data Lines (DL), a plurality of Gate Lines (GL), and a plurality of Sensing Lines (SL) may be disposed on the panel (110), and a plurality of pixels (P) may be disposed on the panel.

The gate driver (130) may supply a scan signal of an on voltage or an off voltage to the Gate Line (GL). When a scan signal of an on voltage is supplied to the pixel (P), the pixel (P) is connected to the Data Line (DL). When a scan signal of an off voltage is supplied to the pixel (P), the pixel (P) is disconnected from the Data Line (DL).

The source driver (120) supplies a data voltage to the Data Line (DL). The data voltage supplied to the Data Line (DL) is supplied to the pixel (P) connected to the Data Line (DL) according to the scan signal.

The source driver (120) senses electrical characteristic values, such as voltage and current, formed in each pixel (P). The source driver (120) may be connected to each pixel (P) according to a scan signal, or may be connected to each pixel (P) according to a separate sensing signal. Here, the sensing signal may be generated by a gate driver (130).

The timing controller (140) may supply various control signals to the gate driver (130) and the source driver (120). The timing controller (140) may generate a Gate Control Signal (GCS) to start scanning according to timing implemented in each frame, and may transmit the gate control signal to the gate driver (120). The timing controller (140) may output image DATA (RGB _ DATA), which is obtained by converting an image DATA input from the outside according to a DATA signal format for the source driver (120), to the source driver (120). The timing controller (140) may also emit a Data Control Signal (DCS) controlling the source driver (120) according to each timing to supply a data voltage to each pixel (P).

The timing controller (140) may calibrate the image DATA (RGB _ DATA) according to the characteristics of the pixel (P), and may transmit the calibrated image DATA. Here, the timing controller (140) may receive sensing DATA (SENSE _ DATA) from the source driver (120) in order to identify characteristics of the pixel (P).

The panel (110) may be an organic light emitting display panel. Here, the pixels (P) disposed on the panel (110) may include Organic Light Emitting Diodes (OLEDs) and one or more transistors. Characteristics of the Organic Light Emitting Diode (OLED) and the transistor included in each pixel (P) may vary with time or according to ambient environments. The source driver (120) may sense characteristics of these components included in each pixel (P) and may transmit the characteristics to the timing controller (140).

Fig. 2 illustrates the structure of each pixel in fig. 1.

Referring to fig. 2, the pixel (P) may include an (OLED), a driving transistor (DRT), a switching transistor (SWT), a sensing transistor (SENT), and a storage capacitor (Cstg).

An Organic Light Emitting Diode (OLED) may include an anode electrode, an organic layer, and a cathode electrode. When the anode electrode is connected to a driving voltage (EVDD) and the cathode electrode is connected to a ground voltage (EVSS) under the control of the driving transistor (DRT), the Organic Light Emitting Diode (OLED) emits light.

The driving transistor (DRT) may control a driving current supplied to the Organic Light Emitting Diode (OLED), thereby controlling the luminance of the Organic Light Emitting Diode (OLED).

The first node (N1) of the driving transistor (DRT) may be electrically connected to an anode electrode of the Organic Light Emitting Diode (OLED), and may be a source node or a drain node. The second node (N2) of the driving transistor (DRT) may be electrically connected to the source node or the drain node of the switching transistor (SWT), and may be a gate node. The third node (N3) of the driving transistor (DRT) may be electrically connected to a Driving Voltage Line (DVL) for supplying a driving voltage (EVDD), and may be a drain node or a source node.

The switching transistor (SWT) is electrically connected to the Data Line (DL) and to the second node (N2) of the driving transistor (DRT) therebetween, and may be turned on by receiving a scan signal through the Gate Line (GL).

When the switching transistor (SWT) is turned on, the data voltage (Vdata) supplied from the source driver (120) through the Data Line (DL) is emitted to the second node (N2) of the driving transistor (DRT).

The storage capacitor (Cstg) may be electrically connected to the first node (N1) and to a second node (N2) of the driving transistor (DRT) therebetween.

The storage capacitor (Cstg) may take the form of a parasitic capacitance existing between the first node (N1) and the second node (N2) of the driving transistor (DRT), or may be an external capacitor intentionally designed outside the driving transistor (DRT).

The sense transistor (SENT) may electrically connect the first node (N1) of the drive transistor (DRT) to a Sense Line (SL) that supplies a reference voltage (Vref) to the first node (N1) and senses an electrical characteristic value, such as a voltage, of the first node (N1). The source driver (120) senses the pixel (P) using a sensing signal (Vsense) emitted through the Sensing Line (SL).

When the voltage of the first node (N1) is sensed, the threshold voltage and mobility of the driving transistor (DRT) may be identified. In addition, when the voltage of the first node (N1) is sensed, a degree of degradation of the Organic Light Emitting Diode (OLED), for example, a parasitic capacitance of the Organic Light Emitting Diode (OLED), may be identified.

The source driver (120) may sense a voltage of the first node (N1) and may transmit the voltage to the timing controller (see 140 in fig. 1). The timing controller (see 140 in fig. 1) may analyze the voltage of the first node (N1) and thus identify the characteristics of each pixel (P).

Referring to fig. 3, the source driver 120 may include a data driver 310, a clock generator 320, a sensor 330, a memory 340, and an output unit 350.

The DATA driver (310) converts the image DATA (RGB _ DATA) to generate a DATA voltage (Vdata).

The DATA driver (310) may receive the image DATA (RGB _ DATA) according to the first clock signal (CLK _ DATA). The first clock signal (CLK _ DATA) may be embedded in the image DATA (RGB _ DATA), and this type of clock signal may also be referred to as an embedded clock (embedded clock) signal.

The source driver (120) may receive the embedded Clock signal from the timing controller, and may use a CDR (Clock Data Recovery) circuit to separate the embedded Clock signal into a Clock signal and Data, thereby reconstructing the Clock signal and Data. The reconstructed DATA may include image DATA (RGB _ DATA) and control signals (see DCS in fig. 1).

The clock generator (320) may generate a second clock signal (CLK _ SP) having a different frequency from the first clock signal (CLK _ DATA) according to the setting information. The second clock signal (CLK _ SP) is a clock signal used as a sampling clock to indicate a sensing period for the pixel.

Conventional source drivers use the first clock signal (CLK _ DATA) to indicate the sensing period for the pixel without components such as a clock generator (320). However, such a general source driver has several problems. For example, when the frequency of the first clock signal (CLK _ DATA) is higher than a frequency that the source driver can sense, the source driver malfunctions. In addition, when the frequency of the first clock signal (CLK _ DATA) is significantly lower than the frequency that the source driver can sense, the sensing performance of the source driver is deteriorated. In addition, when a clock for image data and a sampling clock have the same frequency, electromagnetic interference (EMI) noise is inserted into the image data or the sensing data.

Since the clock generator (320) generates the second clock signal (CLK _ SP) according to the setting information, these problems can be solved. For example, the clock generator (320) generates the second clock signal (CLK _ SP) using the setting information so that the source driver operates in an appropriate range, thereby preventing the source driver malfunction from occurring and preventing the sensing performance of the source driver from being deteriorated. In addition, the clock generator (320) may generate the second clock signal (CLK _ SP) having a frequency different from that of the first clock signal (CLK _ DATA) using the setting information, thereby reducing electromagnetic interference (EMI) noise.

The sensor 330 may periodically sense the pixel according to a second clock signal (CLK _ SP) generated by the clock generator 320. When the sensing signal (Vsense) of the pixel is an Analog signal (e.g., a voltage signal or a current signal), the sensor 330 may include an Analog-to-Digital Converter (ADC) for converting the Analog signal into a Digital signal.

The sensor 330 may generate sensing data according to the second clock signal (CLK _ SP) and may store the sensing data in the memory 340. The output unit (350) may transmit the sensing DATA (SENSE _ DATA) stored in the memory (340) to the timing controller.

The clock generator (320) can obtain the setting information from the outside.

Referring to fig. 4, the setting information may be obtained from the outside.

Referring to (a) of fig. 4, the setting information may be included in a control signal (DCS) received from the timing controller. The clock generator (320 a) may obtain setting information from the control signal (DCS), and may generate the second clock signal (CLK _ SP) according to the setting information. For example, the control signal (DCS) may include setting information indicating a frequency for the second clock signal (CLK _ SP), and the clock generator (320 a) may set the frequency for the second clock signal (CLK _ SP) according to the setting information.

Referring to (B) of fig. 4, the clock generator (320B) may obtain the setting information through a setting value of an external circuit connected to a specific pin (pin). For example, an impedance circuit may be connected to a specific pin of the source driver, and the clock generator (320 b) may set a frequency for the second clock signal (CLK _ SP) according to an impedance value of the impedance circuit.

Referring to (C) of fig. 4, the setting information stored in the clock generator (320C) may be programmed according to an external signal. The clock generator (320 c) may generate the second clock signal (CLK _ SP) according to the programmed setting information.

Fig. 5 is a flow chart illustrating a first exemplary method for generating a second clock signal according to setting information and for transmitting and receiving sensing data and image data.

Referring to fig. 5, the timing controller (140) may transmit setting information to the source driver (S502). The setting information may be included in the control signal or may be transmitted as a separate signal.

The source driver (120) may generate a second clock signal (CLK _ SP) according to the received setting information (S504). The received setting information may include frequency information. The source driver (120) may set a frequency for the second clock signal (CLK _ SP) according to the received frequency information.

The source driver (120) may sense the pixels according to the second clock signal (CLK _ SP), and may generate sensing data (S506).

The source driver (120) may transmit sensing data about the pixels to the timing controller (140) (S508).

The timing controller (140) may identify a feature value of each pixel using the sensing data, and may calibrate the image data (S510).

The timing controller (140) may transmit the calibrated image data to the source driver (120) (S512). The source driver (120) may supply data voltages to the pixels according to the received image data.

The timing controller (140) may transmit the changed setting information to the source driver (120) at an arbitrary time or at a predetermined time (S514).

The source driver (120) may change the setting of the second clock signal (CLK _ SP) according to the changed setting information (S516). For example, the source driver (120) may change the frequency of the second clock signal (CLK _ SP) according to the changed setting information.

The source driver (120) may sense the pixels according to the changed second clock signal (CLK _ SP) (S518), and may transmit the sensing data to the timing controller (140) (S520).

Referring to fig. 6, the source driver (120) may check external setting information (S602), and may generate a second clock signal (CLK _ SP) according to the setting information (S604).

The source driver (120) may sense the pixels according to the second clock signal (CLK _ SP), and may generate sensing data (S606).

The source driver (120) may transmit sensing data about the pixels to the timing controller (140) (S608).

The timing controller (140) may identify a feature value of each pixel using the sensing data, and may calibrate the image data (S610).

The timing controller (140) may transmit the calibrated image data to the source driver (120) (S612). The source driver (120) may supply data voltages to the pixels according to the received image data.

The external setting information may be changed at an arbitrary time or at a predetermined time.

The source driver (120) may check the changed setting information (S614), and may change the setting of the second clock signal (CLK _ SP) according to the setting information (S616). For example, the source driver (120) may change the frequency of the second clock signal (CLK _ SP) according to the changed setting information.

The source driver (120) may sense the pixels according to the changed second clock signal (CLK _ SP) (S618), and may transmit the sensing data to the timing controller (140) (S620).

Fig. 7 illustrates a first exemplary configuration of a clock generator.

The clock generator 700 may include a Voltage generator 710, a Voltage selector 720, and a VCO (Voltage-Controlled Oscillator).

The voltage generator 710 may generate a plurality of voltages (Vref), and may provide the generated voltages to the voltage selector 720. For example, the voltage generator (710) may include a voltage distribution circuit including a plurality of resistors, and a plurality of voltages (Vref) may be generated by the voltage distribution circuit.

The voltage selector (720) may select one of the plurality of voltages (Vref) as the set voltage (Vset) according to the setting information (CONTROL).

The VCO (730) may determine a frequency according to the set voltage (Vset), and may generate a second clock signal (CLK _ SP).

Fig. 8 illustrates a second exemplary configuration of the clock generator.

Referring to fig. 8, the Clock generator (800) may include a CDR (Clock Data Recovery) circuit (810) and a frequency synthesizer (820).

The CDR circuit (810) may recover a first clock signal (CLK _ DATA) from image DATA (RGB _ DATA) received from the timing controller.

The frequency synthesizer (820) may generate a second clock signal (CLK _ SP) having a different frequency based on the first clock signal (CLK _ DATA). Here, the frequency of the second clock signal (CLK _ SP) may be determined according to the setting information (CONTROL) received from the timing controller.

When the panel driving system has a plurality of source drivers, each of which generates the second clock signal (CLK _ SP) according to a separation rule (e.g., a set voltage), there may be a difference between the second clock signals (CLK _ SP) generated by the respective source drivers. For example, multiple source drivers may have variations across PVT (Process, voltage, temperature). Even if a plurality of source drivers input the same set voltage to the VCO, different second clock signals (CLK _ SP) may be generated due to PVT variations.

However, when the clock generator (800) generates the second clock signal (CLK _ SP) based on the first clock signal (CLK _ DATA), as shown in fig. 8, the second clock signal (CLK _ SP) is generated based on the first clock signal (CLK _ DATA) that all source drivers typically receive from the timing controller, and thus the aforementioned difference may be eliminated.

Referring to fig. 9, the frequency synthesizer (820) may include a first counter (910), a comparator (920), a charge pump (930), a VCO (940), and a second counter (950), and may be configured in the form of a PLL (phase locked LOOP).

The output from the VCO (940) in the PLL circuit may be used as the second clock signal (CLK _ SP).

The frequency synthesizer (820) may generate a second clock signal (CLK _ SP) having a frequency M/N times that of the first clock signal (CLK _ DATA) based on the first clock signal (CLK _ DATA). Here, M may be a natural number, and N may be a natural number greater than M.

The first counter 910 counts the first clock signal CLK _ DATA, thereby generating a reference signal iREF having a frequency 1/N (N is a natural number) times the first clock signal.

The second counter (950) may count the second clock signal (CLK _ SP) output from the VCO (940), thereby generating the feedback signal (iFB) having a frequency 1/M (M is a natural number) times the second clock signal (CLK _ SP).

The first counter (910) and the second counter (950) may be referred to as DIVIDERs (DIVIDERs) because the frequency is divided by an amount corresponding to 1/N or 1/M.

The comparator (920) may control the VCO (940) by comparing the phases of the reference signal (iREF) and the feedback signal (iFB). Specifically, the comparator (920) may generate UP/DOWN (UP/DOWN) signals by comparing phases of the reference signal (iREF) and the feedback signal (iFB), and may transmit the UP/DOWN signals to the charge pump (930). The charge pump (930) may control the VCO (940) according to the up/down signals.

After passing through the frequency synthesizer (820), a second clock signal (CLK _ SP) is generated having a frequency M/N times the frequency of the first clock signal (CLK _ DATA). For example, when the first clock signal (CLK _ DATA) has a frequency of 100 mhz, N =2, and M =1, the frequency of the second clock signal (CLK _ SP) is 50 mhz. In another example, when the first clock signal (CLK _ DATA) has a frequency of 100 megahertz, N =3, and M =2, the frequency of the second clock signal (CLK _ SP) is 66.6 megahertz.

The setting values N and M for the first counter (910) and the second counter (950) may be included in the setting information (CONTROL), described with reference to fig. 8. For example, when the setting information (CONTROL) is received from the timing controller, the timing controller may transmit the setting values of N and M through the setting information (CONTROL), and the source driver may determine the frequency of the second clock signal (CLK _ SP) according to the setting information (CONTROL).

Fig. 10 illustrates a third exemplary configuration of a clock generator.

Referring to fig. 10, the clock generator (1000) may include a CDR circuit (1010) and a signal combiner (1020).

The CDR circuit (1010) may recover a first clock signal (CLK _ DATA) from image DATA (RGB _ DATA) received from a timing controller, and may generate a plurality of reference signals (MULTI-phase clock _ DATA) having the same frequency and a certain phase difference with respect to the first clock signal (CLK _ DATA), and may transmit the reference signals to a signal combiner (1020).

The signal combiner (1020) may generate the second clock signal (CLK _ SP) by performing an Exclusive OR (XOR) operation on the plurality of reference signals (MULTI-PHASE CLK _ DATA). Here, the exclusive or operation may be performed according to the setting information (CONTROL).

Fig. 11 illustrates waveforms of a plurality of reference signals generated in the CDR circuit, and fig. 12 illustrates waveforms generated by an exclusive or operation of the plurality of reference signals.

The CDR circuit may include a DLL (DELAY LOCKING LOOP) circuit that may generate a plurality of reference signals having different phases to the reference signals (ck.ph 0 to ck.ph 23) using the first clock signal.

The signal combiner may perform an exclusive-or operation on some of the plurality of reference signals (ck.ph 0 to ck.ph 23) generated by the DLL circuit. For example, the signal combiner may generate the first output signal (2 xCKa) by performing an exclusive-or operation on the first reference signal (ck.ph0) and the seventh reference signal (ck.ph6). The signal combiner may generate the second output signal (2 xCKb) by performing an exclusive-or operation on the fourth reference signal (ck.ph 3) and the tenth reference signal (ck.ph 9). The first output signal (2 xCKa) or the second output signal (2 xCKb) may actually be used as the second clock signal.

When the exclusive-or operation is performed by the signal combiner, an output signal having a frequency twice that of the reference signal is generated. Subsequently, when the exclusive-or operation is performed again on this output signal, an output signal having a frequency four times that of the reference signal is generated.

For example, an exclusive-or operation of the first output signal (2 xCKa) and the second output signal (2 xCKb) may generate a third output signal (4 xCK) having a frequency four times that of the reference signal.

The signal combiner may generate the second clock signal having a frequency that is a power of L of 2 (L is a natural number) times the frequency of the first clock signal by an exclusive or operation. Here, the setting value L may be determined based on the setting information.

Fig. 13 illustrates a fourth exemplary configuration of a clock generator.

Referring to fig. 13, the clock generation unit 1300 may include a CDR circuit 1010, a signal combiner 1320, and a counter 1330.

The CDR circuit (1010) may recover a first clock signal (CLK _ DATA) from image DATA (RGB _ DATA) received from a timing controller, may generate a plurality of reference signals (MULTI-PHASE CLK _ DATA) having the same frequency and a certain PHASE difference with respect to the first clock signal (CLK _ DATA), and may transmit the reference signals to a signal combiner (1320).

The signal combiner (1320) may generate a multiplication (multiplication) signal having a frequency P (P is a natural number) times of the first clock signal by combining a plurality of reference signals (MULTI-phase _ DATA). Here, the combining performed by the signal combiner (1320) may include AND operations, OR operations, AND the like.

The counter (1330) may count the multiplied signal, thereby generating a second clock signal (CLK _ SP) having a frequency of 1/Q (Q is a natural number) times the multiplied signal.

Here, P is a fixed value, and Q may be a value determined according to the setting information.

Fig. 14 illustrates waveforms of the multiplied signal according to the example of fig. 13.

The signal combiner may generate the multiplied signal by combining a plurality of reference signals. Waveforms of a plurality of reference signals are shown in fig. 11.

The signal combiner may be for the first reference signal (CK. Ph0) and an inverted signal of the second reference signal

Performing an AND operation to generate a first output signal

Likewise, the signal combiner may be for the third reference signal (ck. Ph 2) and the inverted signal of the fourth reference signal

Performing AND operation to generate a second output signal

With respect to the fifth to twenty-fourth reference signals (ck.ph 4 to ck.ph 23), the signal combiner may sequentially perform an AND operation on two consecutive reference signals, one of which is used as is AND the other of which is used in an inverted form, thereby generating a total of 12 output signals.

The signal combiner may perform an OR operation on all the output signals, thereby generating a multiplied signal (12 × Clock) having a frequency 12 times that of the first Clock signal.

The signal combiner may count the signal multiplied by 12 (12 × Clock) again, thereby generating a second Clock signal corresponding to the setting information.

The embodiments of the present disclosure have been described above. According to this embodiment, it is possible to adjust the frequency of the sampling clock (second clock signal) for pixel sensing according to the setting information. Further, according to this embodiment, it is possible to prevent malfunction of the pixel sensing device (or the source driver and the panel driving system including the source driver) and reduce electromagnetic interference (EMI) noise.

Unless otherwise specified, the term "comprising", "including" or "having" as used herein indicates that a certain constituent element may be included, and thus should be interpreted as not excluding another constituent element but further including another constituent element. Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. It will be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

The foregoing description has been made only for the purpose of illustrating the technical idea of the present disclosure, and various changes and modifications may be made by a person having ordinary skill in the art to which the present disclosure pertains without departing from the essential features of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are not intended to limit and describe the technical idea of the present disclosure, and the technical idea of the present disclosure is not limited by these embodiments. The scope of the present disclosure should be defined by the appended claims, and all technical ideas within the scope of equivalents of the appended claims should be construed as being included in the scope of the present disclosure.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims 2016 priority to korean patent application No. 10-2016-0053397, filed by the korean intellectual property office on 29/4, 2016, the disclosure of which is incorporated herein by reference in its entirety. In addition, when the present application claims priority in countries other than the united states for the same reason, the disclosure of the present application is incorporated herein by reference in its entirety.

Claims

1. A source driver, comprising:

a data driver generating a data voltage by converting image data received according to a first clock signal having a first frequency;

a clock generator generating a second clock signal having a second frequency different from the first frequency based on the setting information received from the timing controller;

a sensor sensing pixels according to the second clock signal; and

an output unit to transmit sensing data corresponding to the pixels to the timing controller,

wherein the clock generator generates the second clock signal having a frequency different from the second frequency and the first frequency in response to receiving changed setting information from the timing controller,

wherein the clock generator generates the second clock signal based on the first clock signal,

wherein the clock generator comprises:

a first counter generating a reference signal having a frequency 1/N times that of the first clock signal by counting the first clock signal, N being a natural number;

a VCO to determine a frequency for the second clock signal;

a second counter generating a feedback signal having a frequency 1/M times the output signal from the VCO by counting the output signal, M being a natural number; and

a comparator to control the VCO by comparing the reference signal with the feedback signal.

2. The source driver of claim 1, wherein the data driver receives image data calibrated according to the sensing data.

3. The source driver of claim 1, wherein the clock generator obtains the setting information through a setting value of an external circuit connected to a specific pin (pin).

4. The source driver of claim 1, wherein the setting information is included in a control signal received from the timing controller.

5. The source driver of claim 1, wherein the setting information comprises setting values for the first counter and the second counter.

6. A source driver, comprising:

a sensor sensing pixels according to the second clock signal; and

wherein the clock generator comprises a signal combiner receiving a plurality of reference signals having the same frequency and a certain phase difference with respect to the first clock signal, and generating the second clock signal by performing an Exclusive OR (XOR) operation on the plurality of reference signals.

7. A source driver, comprising:

a sensor sensing pixels according to the second clock signal; and

wherein the clock generator comprises:

a signal combiner receiving a plurality of reference signals having the same frequency and a certain phase difference with respect to the first clock signal and generating a multiplied (multiplication) signal having a frequency P times that of the first clock signal by combining the plurality of reference signals, P being a natural number; and

a counter generating the second clock signal having a frequency 1/Q times of the multiplied signal by counting the multiplied signal, Q being a natural number.

8. A panel drive system comprising:

a timing controller receiving sensing data corresponding to each pixel and emitting an embedded clock signal including image data calibrated according to the sensing data; and

at least one source driver receiving the embedded clock signal from the timing controller, restoring a first clock signal having a first frequency, a control signal, and the image data by isolating the first clock signal, the control signal, and the image data from the embedded clock signal, generating a second clock signal having a second frequency different from the first frequency based on setting information included in the control signal, generating the sensing data by sensing the pixels according to the second clock signal, and transmitting the sensing data to the timing controller,

wherein the at least one source driver generates the second clock signal having a frequency different from the second frequency and the first frequency in response to receiving changed setting information from the timing controller,

wherein the at least one source driver generates the second clock signal having a frequency M/N times the first clock signal based on the first clock signal, M being a natural number, and N being a natural number greater than M,

wherein the setting information includes setting values indicating M and N.

9. The panel driving system according to claim 8, comprising a plurality of source drivers,

wherein the plurality of source drivers generate the second clock signal based on the first clock signal normally received from the timing controller.

10. The panel driving system according to claim 8, wherein the source driver uses the second clock signal as a sampling clock to indicate a sensing period of the pixel.

11. The source driver of claim 1, wherein the sensor periodically senses the pixel according to the second clock signal.