CN109074780A - Panel driving system and source electrode driver - Google Patents
Panel driving system and source electrode driver Download PDFInfo
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- CN109074780A CN109074780A CN201780026412.4A CN201780026412A CN109074780A CN 109074780 A CN109074780 A CN 109074780A CN 201780026412 A CN201780026412 A CN 201780026412A CN 109074780 A CN109074780 A CN 109074780A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3275—Details of drivers for data electrodes
- G09G3/3291—Details of drivers for data electrodes in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2310/00—Command of the display device
- G09G2310/08—Details of timing specific for flat panels, other than clock recovery
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2330/00—Aspects of power supply; Aspects of display protection and defect management
- G09G2330/06—Handling electromagnetic interferences [EMI], covering emitted as well as received electromagnetic radiation
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Control Of Indicators Other Than Cathode Ray Tubes (AREA)
Abstract
The present invention provides a kind of technology of frequency that the sampling clock for pixels sense can be adjusted according to configuration information.
Description
Technical field
This disclosure relates to which a kind of technology for sensing the feature for the pixel being placed on display panel and one kind are for driving
The technology of dynamic display panel.
Background technique
Display device includes the board driving mchanism of the brightness for the pixel that control is placed on panel, such as drives comprising source electrode
The driving device of dynamic device and timing controller.
Board driving mchanism determines data voltage according to image data and data voltage is supplied to pixel, and then controls
The brightness of each pixel.
Even when receiving identical data voltage, the brightness of pixel can according to pixel feature and change.For example, as
Element includes driving transistor, and when driving the threshold voltage of transistor to change, even if supply identical data voltage, respective pixel
Brightness it is changeable.If board driving mchanism is it is not intended that this feature of pixel changes, pixel can utilize non-required
Brightness drives, and causes the picture quality to deteriorate.
Specifically, the feature of pixel can change over time or can change according to ambient enviroment.Herein, work as panel driving
Device provisioning data voltage without consider pixel change feature when, the deterioration of picture quality, such as line defect can occur
(line defect)。
For the deterioration of resolution image quality, display device can further include pixels sense device with the spy of sensor pixel
Sign.Pixels sense device can periodically or non-periodically check the feature of each pixel and can be by the characteristic emission to panel
Driving device.Board driving mchanism carrys out calibration data voltage in view of the characteristic value of each pixel emitted from pixels sense device,
And then solve the deterioration of the picture quality caused by changing because of the feature of pixel.
Pixels sense device can be configured to self-contained unit, but also may be included in source electrode driver.In addition, pixels sense fills
Setting may be included in board driving mchanism to constitute panel driving system.
Pixels sense device is according to sampling clock come periodically sensor pixel.It is contained in when the frequency of sampling clock exceeds
When the opereating specification of the analog-digital converter (ADC:Analog-Digital Converter) in pixels sense device, pixels sense
Device may break down.In addition, when sampling clock has equivalent or similar to frequency for the clock of image data, electricity
Magnetic disturbance (EMI:Electro-Magnetic Interference) noise can be plugged into sensing data.
Summary of the invention
Technical problem
In this background, the aspect of the disclosure, which will provide one kind, to be used for pixels sense according to setting information to adjust
Sampling clock frequency technology.
Technical solution
To realize aforementioned aspects, the aspect of the disclosure provide it is a kind of comprising data driver, clock generator, sensor with
And the source electrode driver of output unit.
In the source driver, data driver can by conversion according to the first clock signal come received image data come
Generate data voltage.Clock generator can be generated according to external setting information with the frequency different from the first clock signal
Second clock signal.Sensor can be according to second clock signal come periodically sensor pixel.Output unit can will be about pixel
Sensing data be emitted to timing controller.
Another aspect of the present disclosure provides a kind of panel driving system comprising timing controller and source electrode driver.
In panel driving system, timing controller can receive the sensing data about each pixel, and can emit and include
According to sensing data come the clock-embedded signal for the image data calibrated.When source electrode driver can receive insertion from timing controller
Clock signal, can be by being isolated the first clock signal from the received clock-embedded signal of institute, controlling signal and image data
Restore the first clock signal, control signal and image data, can be produced according to the setting information being contained in control signal
The raw second clock signal with the frequency different from the first clock signal, can by according to second clock signal come sensor pixel
It generates sensing data, and the sensing data of generation can be emitted to timing controller.
The effect of invention
As described above, according to the disclosure, it is possible to when adjusting the sampling for pixels sense according to setting information
The frequency of clock.In addition, according to the disclosure, it is possible to prevent pixels sense device (or source electrode driver and comprising the source electrode drive
The panel driving system of dynamic device) failure occur and reduce electromagnetic interference (EMI) noise.
Detailed description of the invention
Fig. 1 illustrates the configuration of display device according to an embodiment of the present disclosure.
The structure of each pixel in Fig. 2 explanatory diagram 1.
Fig. 3 illustrates the configuration of source electrode driver according to an embodiment of the present disclosure.
Fig. 4 illustrates the embodiment of wherein clock generator acquisition setting information.
Fig. 5 be illustrate for generated according to setting information second clock signal and for transmitting and receiving sensing data and
The flow chart of first exemplary method of image data.
Fig. 6 be illustrate for generated according to setting information second clock signal and for transmitting and receiving sensing data and
The flow chart of second exemplary method of image data.
Fig. 7 illustrates the first exemplary configuration of clock generator.
Fig. 8 illustrates the second exemplary configuration of clock generator.
Fig. 9 illustrates the exemplary configuration of frequency synthesizer illustrated in fig. 8.
Figure 10 illustrates the third exemplary configuration of clock generator.
Figure 11 illustrates to result from the waveform of multiple reference signals in ce circuit.
Figure 12 illustrates the waveform generated by the xor operation of multiple reference signals.
Figure 13 illustrates the 4th exemplary configuration of clock generator.
Figure 14 illustrates the waveform of the multiplied signal of the example according to shown in Figure 13.
Specific embodiment
Hereinafter, reference attached drawing is described in detail some embodiments of the present disclosure.It should be noted that will refer to
It in terms of label is added to the composition element in attached drawing, is similarly constructed no matter when element is indicated by similar reference label, or even works as
When showing in different figures.In being described below of the disclosure, when the detailed description for determining related known configurations or function makes
The disclosure it is indefinite when, will thus omit the detailed description.
In the composition element of the description disclosure, term such as first, second, A, B, (a) and (b) can be used.These
Term is only used for distinguishing a composition element and another composition element, and is not intended to limit property, the sequence for constituting element
Column or sequence.It should be understood that when composition element is described as with another composition element " coupling ", " combination " or " connection ", it is described
Element can be directly coupled or connected to another element or intervening element can also be with the element and another element " coupling ", " group
Close " or " connection ".
Fig. 1 illustrates the configuration of display device according to an embodiment of the present disclosure.
With reference to Fig. 1, display device (100) may include panel (110), source electrode driver (120), gate drivers (130)
And timing controller (140).
Multiple data lines (DL), multiple grid lines (GL) and multiple sense wires (SL) can be placed on panel (110), and
Multiple pixels (P) can be placed on panel.
Gate drivers (130) can will turn on voltage or the scanning signal of off voltage is supplied to grid line (GL).As general
When the scanning signal of connection voltage is supplied to pixel (P), pixel (P) is connected to data line (DL).When the scanning that will be switched off voltage
When signal is supplied to pixel (P), pixel (P) is disconnected with data line (DL).
Data voltage is supplied to data line (DL) by source electrode driver (120).The data electricity of data line (DL) will be supplied to
Pressure is supplied to according to scanning signal the pixel (P) for being connected to data line (DL).
Source electrode driver (120) senses the electrical characteristic values being formed in each pixel (P), such as voltage and current.Source electrode
Driver (120) can be connected to each pixel (P) according to scanning signal, or can be connected to according to independent sensing signal each
Pixel (P).Herein, sensing signal can be generated by gate drivers (130).
Various control signals can be supplied to gate drivers (130) and source electrode driver by timing controller (140)
(120).Timing controller (140) can produce grid control signal (GCS) to start according to the timing implemented in each frame
Scanning, and grid control signal can be emitted to gate drivers (120).Timing controller (140) can be by image data (RGB_
DATA it) is output to source electrode driver (120), described image data pass through according to the data-signal for being used for source electrode driver (120)
Format obtains to convert from external image data input.Timing controller (140) can also emit according to each timing
The data controlling signal (DCS) of source electrode driver (120) is controlled so that data voltage is supplied to each pixel (P).
Timing controller (140) can be calibrated image data (RGB_DATA) according to the feature of pixel (P), and can emit school
Quasi- image data.Herein, timing controller (140) can receive sensing data (SENSE_DATA) from source electrode driver (120),
To identify the feature of pixel (P).
Panel (110) can be organic light emitting display panel.Herein, the pixel (P) being placed on panel (110) may include
Organic Light Emitting Diode (OLED:Organic Light Emitting Diode) and one or more transistors.It is contained in each
The feature of Organic Light Emitting Diode (OLED) and transistor in pixel (P) can change over time or become according to ambient enviroment
Change.Source electrode driver (120) can sense the feature for these components being contained in each pixel (P), and can arrive characteristic emission
Timing controller (140).
The structure of each pixel in Fig. 2 explanatory diagram 1.
With reference to Fig. 2, pixel (P) may include (OLED), driving transistor (DRT), switching transistor (SWT), sensing crystal
Manage (SENT) and storage (Cstg).
Organic Light Emitting Diode (OLED) may include anode electrode, organic layer and cathode electrode.When in driving transistor
(DRT) under control, when anode electrode is connected to driving voltage (EVDD) and cathode electrode is connected to ground voltage (EVSS), have
Machine light emitting diode (OLED) shines.
The controllable driving current for being supplied to Organic Light Emitting Diode (OLED) of driving transistor (DRT), and then control has
The brightness of machine light emitting diode (OLED).
The first node (N1) of driving transistor (DRT) can be electrically connected to the anode electricity of Organic Light Emitting Diode (OLED)
Pole, and can be source node or drain node.It is brilliant that the second node (N2) of driving transistor (DRT) can be electrically connected to switch
The source node or drain node of body pipe (SWT), and can be gate node.Drive the third node (N3) of transistor (DRT)
It can be electrically connected to the drive voltage line (DVL) for supplying driving voltage (EVDD), and can be drain node or source electrode section
Point.
Switching transistor (SWT) is electrically connected to data line (DL) and is electrically connected to driving transistor (DRT) therebetween
Second node (N2), and can be connected by receiving scanning signal using grid line (GL).
When switching transistor (SWT) is connected, the data that will be supplied by data line (DL) by source electrode driver (120) are electric
Pressure (Vdata) is emitted to the second node (N2) of driving transistor (DRT).
Storage (Cstg) can be electrically connected to first node (N1), and be electrically connected to driving transistor therebetween
(DRT) second node (N2).
Storage (Cstg) can take the first node (N1) and second node for being present in driving transistor (DRT)
(N2) the parasitic capacitance form between, or can be and be intentionally designed at the external external capacitor of driving transistor (DRT).
Sensing transistor (SENT) can will drive the first node (N1) of transistor (DRT) to be electrically connected to sense wire
(SL), reference voltage (Vref) is supplied to first node (N1) and senses the electrical feature of first node (N1) by the sense wire
Value, such as voltage.Source electrode driver (120) is using the sensing signal (Vsense) emitted by sense wire (SL) come sensor pixel
(P)。
When sensing the voltage of first node (N1), the threshold voltage and mobility of driving transistor (DRT) can recognize.
In addition, can recognize the degradation of Organic Light Emitting Diode (OLED) when sensing the voltage of first node (N1), such as have
The parasitic capacitance of machine light emitting diode (OLED).
Source electrode driver (120) can sense the voltage of first node (N1), and can be by the voltage discharge to timing controlled
Device (see 140 in Fig. 1).Timing controller (see 140 in Fig. 1) can analyze the voltage of first node (N1), and then identify every
The feature of a pixel (P).
Fig. 3 illustrates the configuration of source electrode driver according to an embodiment of the present disclosure.
With reference to Fig. 3, source electrode driver (120) may include data driver (310), clock generator (320), sensor
(330), memory (340) and output unit (350).
Data driver (310) conversion image data (RGB_DATA) is to generate data voltage (Vdata).
Data driver (310) can receive image data (RGB_DATA) according to the first clock signal (CLK_DATA).
First clock signal (CLK_DATA) is embeddable in image data (RGB_DATA), and such clock signal can also claim
For clock-embedded (embeded clock) signal.
Source electrode driver (120) can receive clock-embedded signal from timing controller, and CDR (Clock Data can be used
Recovery) circuit by clock-embedded Signal separator at clock signal and data, and then reconstructing clock signals and data.Reconstruct
Data may include image data (RGB_DATA) and control signal (see the DCS in Fig. 1).
Clock generator (320) can be generated according to setting information with different from the first clock signal (CLK_DATA)
The second clock signal (CLK_SP) of frequency.Second clock signal (CLK_SP) is used as the clock signal of sampling clock to indicate
Sense period for pixel.
Common source electrode driver indicates the sense period for pixel using the first clock signal (CLK_DATA), and
It is not required to component, such as clock generator (320).However, there are some problems for this common source electrode driver.For example,
When the frequency of the first clock signal (CLK_DATA) is higher than the frequency that source electrode driver can sense, event occurs for source electrode driver
Barrier.In addition, source electrode drives when the frequency of the first clock signal (CLK_DATA) is significantly lower than the frequency that source electrode driver can sense
The sensing performance deterioration of dynamic device.In addition, when for image data clock and sampling clock have identical frequency when, electromagnetic interference
(EMI) noise is inserted into image data or sensing data.
Since clock generator (320) generates second clock signal (CLK_SP) according to setting information, can solve
These problems.For example, clock generator (320) generates second clock signal (CLK_SP) using setting information, so that
Source electrode driver operates in proper range, and then prevents source electrode driver failure from occurring and prevent the sensing of source electrode driver
It can deterioration.In addition, setting information can be used to generate to have and be different from the first clock signal (CLK_ in clock generator (320)
DATA the second clock signal (CLK_SP) of frequency), and then reduce electromagnetic interference (EMI) noise.
Sensor (330) can be according to the second clock signal (CLK_SP) generated by clock generator (320) come periodically
Ground sensor pixel.When the sensing signal (Vsense) of pixel is analog signal (such as voltage signal or current signal), sensing
Device 330 may include the analog-digital converter (ADC:Analog-Digital for converting analog signals into digital signal
Converter)。
Sensor (330) can generate sensing data according to second clock signal (CLK_SP), and can deposit sensing data
It is stored in memory (340).Output unit (350) can will be stored in the sensing data (SENSE_DATA) in memory (340)
It is emitted to timing controller.
Clock generator (320) can obtain setting information from outside.
Fig. 4 illustrates the embodiment of wherein clock generator acquisition setting information.
With reference to Fig. 4, setting information can be obtained from outside.
Referring to (A) of Fig. 4, setting information be may be included in from the received control signal (DCS) of timing controller.Clock produces
Raw device (320a) can obtain setting information from control signal (DCS), and second clock signal can be generated according to setting information
(CLK_SP).For example, control signal (DCS) may include setting of the instruction for the frequency of second clock signal (CLK_SP)
Information, and the frequency for second clock signal (CLK_SP) can be arranged in clock generator (320a) according to setting information.
Referring to (B) of Fig. 4, clock generator (320b) can be set by being connected to the external circuit of special pin (pin)
Value is set to obtain setting information.For example, impedance circuit may be connected to the special pin of source electrode driver, and clock generator
The frequency for second clock signal (CLK_SP) can be arranged in (320b) according to the impedance value of impedance circuit.
It, can setting information according to external signal come program storage in clock generator (320c) referring to (C) of Fig. 4.
Clock generator (320c) can generate second clock signal (CLK_SP) according to the setting information of programming.
Fig. 5 be illustrate for generated according to setting information second clock signal and for transmitting and receiving sensing data and
The flow chart of first exemplary method of image data.
Referring to Fig. 5, setting information can be emitted to source electrode driver (S502) by timing controller (140).Setting information can
It is contained in control signal, or can be used as separation signal to emit.
Source electrode driver (120) can generate second clock signal (CLK_SP) according to the received setting information of institute
(S504).The received setting information of institute may include frequency information.Source electrode driver (120) can according to the received frequency information of institute come
Frequency for second clock signal (CLK_SP) is set.
Source electrode driver (120) can be according to second clock signal (CLK_SP) come sensor pixel, and can produce sensing data
(S506)。
Sensing data about pixel can be emitted to timing controller (140) (S508) by source electrode driver (120).
Sensing data can be used to identify the characteristic value of each pixel, and adjustable image data in timing controller (140)
(S510)。
The image data of calibration can be emitted to source electrode driver (120) (S512) by timing controller (140).Source drive
Data voltage can be supplied to pixel according to the received image data of institute by device (120).
The setting information of change place or can be emitted to source electrode at the predetermined time at any time by timing controller (140)
Driver (120) (S514).
Source electrode driver (120) can change the setting of second clock signal (CLK_SP) according to the setting information of change
(S516).For example, source electrode driver (120) can change second clock signal (CLK_SP) according to the setting information of change
Frequency.
Source electrode driver (120) can be according to the second clock signal (CLK_SP) of change come sensor pixel (S518), and can
Sensing data are emitted to timing controller (140) (S520).
Fig. 6 be illustrate for generated according to setting information second clock signal and for transmitting and receiving sensing data and
The flow chart of second exemplary method of image data.
With reference to Fig. 6, source electrode driver (120) can be checked external setting information (S602), and can be produced according to setting information
Raw second clock signal (CLK_SP) (S604).
Source electrode driver (120) can be according to second clock signal (CLK_SP) come sensor pixel, and can produce sensing data
(S606)。
Sensing data about pixel can be emitted to timing controller (140) (S608) by source electrode driver (120).
Sensing data can be used to identify the characteristic value of each pixel, and adjustable image data in timing controller (140)
(S610)。
The image data of calibration can be emitted to source electrode driver (120) (S612) by timing controller (140).Source drive
Data voltage can be supplied to pixel according to the received image data of institute by device (120).
External setting information can place or the change at the predetermined time at any time.
Source electrode driver (120) can check the setting information (S614) of change, and can change second according to setting information
The setting (S616) of clock signal (CLK_SP).For example, source electrode driver (120) can change according to the setting information of change
Become the frequency of second clock signal (CLK_SP).
Source electrode driver (120) can be according to the second clock signal (CLK_SP) of change come sensor pixel (S618), and can
Sensing data are emitted to timing controller (140) (S620).
Fig. 7 illustrates the first exemplary configuration of clock generator.
Clock generator (700) may include voltage generator (710), voltage selector (720) and VCO (Voltage-
Controlled Oscillator)。
Voltage generator (710) can produce multiple voltages (Vref), and can provide the voltage of generation to voltage selector
(720).For example, voltage generator (710) may include the voltage's distribiuting circuit containing multiple resistors, and can pass through voltage
Distributed circuit generates multiple voltages (Vref).
Voltage selector (720) can select one in multiple voltages (Vref) to make according to setting information (CONTROL)
For voltage (Vset) is arranged.
VCO (730) can determine frequency according to setting voltage (Vset), and can produce second clock signal (CLK_SP).
Fig. 8 illustrates the second exemplary configuration of clock generator.
With reference to Fig. 8, clock generator (800) may include CDR (Clock Data Recovery) circuit (810) and frequency
Synthesizer (820).
Ce circuit (810) can restore the first clock signal from the image data (RGB_DATA) received from timing controller
(CLK_DATA)。
Frequency synthesizer (820) can be based on the first clock signal (CLK_DATA) come when generating second with different frequency
Clock signal (CLK_SP).Herein, the frequency of second clock signal (CLK_SP) can be believed according to from the received setting of timing controller
(CONTROL) is ceased to determine.
When panel drive system has multiple source electrode drivers, each of the multiple source electrode driver basis point
Second clock signal (CLK_SP) is generated from rule (for example, setting voltage), in second generated by corresponding source electrode driver
Difference may be present between clock signal (CLK_SP).For example, multiple source electrode drivers can PVT (Process,
Voltage, Temperature) on have variation.Even if multiple source electrode drivers by identical setting voltage input to VCO, but can
Different second clock signals (CLK_SP) is generated since PVT changes.
However, when clock generator (800) generate second clock signal based on the first clock signal (CLK_DATA)
(CLK_SP) when, as shown in Figure 8, based on all source electrode drivers usually from the received first clock letter of timing controller
Number (CLK_DATA) generates second clock signal (CLK_SP), and therefore can eliminate aforementioned difference.
Fig. 9 illustrates the exemplary configuration of frequency synthesizer illustrated in fig. 8.
With reference to Fig. 9, frequency synthesizer (820) may include the first counter (910), comparator (920), charge pump (930),
VCO (940) and the second counter (950), and can be configured to PLL (PHASELOCKING LOOP) form.
The output from VCO (940) in PLL circuit can be used as second clock signal (CLK_SP).
Frequency synthesizer (820) can be generated based on the first clock signal (CLK_DATA) with the first clock signal
(CLK_DATA) the second clock signal (CLK_SP) of M/N times of frequency.Herein, M can be natural number, and N can be greatly
In the natural number of M.
First counter (910) can count the first clock signal (CLK_DATA), so generate have first when
The reference signal (iREF) of the 1/N (N is natural number) of clock signal times of frequency.
Second counter (950) can count the second clock signal (CLK_SP) exported from VCO (940), in turn
Generate the feedback signal (iFB) of 1/M (M is natural number) times of the frequency with second clock signal (CLK_SP).
First counter (910) and the second counter (950) can be referred to as distributor (DIVIDER), reason be frequency with
Amount corresponding to 1/N or 1/M is distributed.
Comparator (920) can control VCO by comparing the phase of reference signal (iREF) and feedback signal (iFB)
(940).Specifically, comparator (920) can be generated by comparing the phase of reference signal (iREF) and feedback signal (iFB)
Uplink/downlink (UP/DOWN) signal, and uplink/downlink signals can be emitted to charge pump (930).Charge pump (930) can basis
Uplink/downlink signals control VCO (940).
After passing through frequency synthesizer (820), M/N times of the frequency with the first clock signal (CLK_DATA) is generated
The second clock signal (CLK_SP) of rate.For example, when the first clock signal (CLK_DATA) has 100 mhz frequency, N
=2, and M=1, the frequency of second clock signal (CLK_SP) they are 50 megahertzs.In another example, when the first clock signal
(CLK_DATA) when there is 100 mhz frequency, N=3, and M=2, the frequency of second clock signal (CLK_SP) they are 66.6 megahertzs.
Setting value N and M for the first counter (910) and the second counter (950) may be included in setting information
(CONTROL) in, with reference to described by Fig. 8.For example, when receiving setting information (CONTROL) from timing controller, timing
Controller can emit the setting value of N and M via setting information (CONTROL), and source electrode driver can be according to setting information
(CONTROL) frequency of second clock signal (CLK_SP) is determined.
Figure 10 illustrates the third exemplary configuration of clock generator.
Referring to Figure 10, clock generator (1000) may include ce circuit (1010) and signal combiner (1020).
Ce circuit (1010) can restore the first clock signal from the image data (RGB_DATA) received from timing controller
(CLK_DATA), and the more of a certain phase difference with identical frequency and relative to the first clock signal (CLK_DATA) be can produce
A reference signal (MULTI-PHASECLK_DATA), and reference signal can be emitted to signal combiner (1020).
Signal combiner (1020) can be by executing exclusive or to multiple reference signals (MULTI-PHASE CLK_DATA)
(XOR:Exclusive OR) operates to generate second clock signal (CLK_SP).It herein, can be according to setting information (CONTROL)
Execute xor operation.
Figure 11 illustrates to result from the waveform of multiple reference signals in ce circuit, and Figure 12 explanation is by multiple reference signals
Xor operation generate waveform.
Ce circuit may include DLL (DELAY LOCKING LOOP) circuit, and the first clock signal can be used for DLL circuit
Generating has multiple reference signals of out of phase to reference signal (CK.Ph0~CK.Ph23).
Signal combiner can be to the multiple reference signals generated by DLL circuit to reference signal (CK.Ph0~CK.Ph23)
In some execution xor operations.For example, signal combiner can be by joining the first reference signal (CK.Ph0) and the 7th
It examines signal (CK.Ph6) and executes xor operation to generate the first output signal (2xCKa).Signal combiner can be by joining to the 4th
It examines signal (CK.Ph3) and the tenth reference signal (CK.Ph9) executes xor operation to generate the second output signal (2xCKb).The
One output signal (2xCKa) or the second output signal (2xCKb) may indeed act as second clock signal.
When executing exclusive or xor operation by signal combiner, the defeated of twice of the frequency with reference signal is generated
Signal out.Then, when executing xor operation to this output signal again, four times of the frequency with reference signal is generated
Output signal.
For example, the xor operation of the first output signal (2xCKa) and the second output signal (2xCKb) can produce and have
The third output signal (4xCK) of four times of frequency of reference signal.
Signal combiner can be generated by xor operation the frequency with the first clock signal 2 L power (L be from
So number) times frequency second clock signal.Herein, setting value L can be determined based on setting information.
Figure 13 illustrates the 4th exemplary configuration of clock generator.
With reference to Figure 13, clock generating unit (1300) may include ce circuit (1010), signal combiner (1320) and meter
Number device (1330).
Ce circuit (1010) can restore the first clock signal from the image data (RGB_DATA) received from timing controller
(CLK_DATA), the multiple of a certain phase difference with identical frequency and relative to the first clock signal (CLK_DATA) be can produce
Reference signal (MULTI-PHASE CLK_DATA), and reference signal can be emitted to signal combiner (1320).
Signal combiner (1320) can have by combining multiple reference signals (MULTI-PHASECLK_DATA) to generate
Multiplication (multiplication) signal of the P (P is natural number) of first clock signal times of frequency.Herein, pass through signal group
The combination that clutch (1320) executes may include AND operation, OR operation and similar operation.
Counter (1330) can count multiplied signal, and then generate the 1/Q (Q is natural number) with multiplied signal
The second clock signal (CLK_SP) of frequency again.
Herein, P is fixed value, and Q can be according to setting information the value determined.
Figure 14 illustrates the waveform of the multiplied signal of the example according to Figure 13.
Signal combiner can generate multiplied signal by combining multiple reference signals.The waveform of multiple reference signals is shown
In Figure 11.
Signal combiner can be to the reverse signal of the first reference signal (CK.Ph0) and the second reference signalIt holds
Capable and operation, and then generate the first output signalSimilarly, signal combiner can be to third reference signal
(CK.Ph2) and the reverse signal of the 4th reference signalExecution and operation, and then generate the second output signalFor the 5th reference signal (CK.Ph4) to the 24th reference signal (CK.Ph23), signal combiner
AND operation can sequentially be executed with continuing reference to signal to two, described two one with continuing reference in signal use as it is and
Therein another is used with reverse form, and then generates 12 output signals in total.
Signal combiner can execute OR operation to all output signals, and then generate 12 times with the first clock signal
Frequency multiplied signal (12 × Clock).
Signal combiner can again count the signal (12 × Clock) multiplied by 12, and then generate and correspond to setting
The second clock signal of information.
Embodiment of the disclosure already described above.According to this embodiment, it is possible to be used for according to setting information to adjust
The frequency of the sampling clock (second clock signal) of pixels sense.In addition, according to this embodiment, it is possible to prevent pixels sense
The failure of device (or source electrode driver and panel driving system comprising the source electrode driver) occurs and reduces electromagnetic interference
(EMI) noise.
Unless specified otherwise herein, otherwise term "comprising" used herein, " comprising " or " having " instruction may include certain
One constitutes element, and therefore should be interpreted that and be not excluded for another composition element and further include another composition element.Unless in addition
Definition, otherwise all technical and scientific terms used herein have logical with disclosure those of ordinary skill in the art
Often understand identical meaning.It will be understood that such as those of defined in common dictionary the term of term should be interpreted that have with
Its consistent meaning of meaning in the context of the relevant technologies, and unless clearly define herein, it otherwise will not be with reason
Wanting or excessively formal sense explain.
Only illustrate the technical concept of the disclosure and make foregoing description, and can be in the essential feature for not departing from the disclosure
In the case of made various changes and modifications by disclosure those of ordinary skill in the art.Therefore, disclosed in the disclosure
Embodiment is not intended to be limited to and describes the technical concept of the disclosure, and the technical concept of the disclosure is not limited by these embodiments.
The scope of the present disclosure should be defined by the independent claims, and all technologies reason in the range of the equivalent of appended claims
Thought, which should be interpreted that, to be contained in the scope of the present disclosure.
The cross reference of related application
The South Korea patent application 10-2016- submitted this application claims on April 29th, 2016 in Korean Intellectual Property Office
The disclosure of No. 0053397 priority, the application is incorporated herein by reference in its entirety.In addition, working as the application
It is required that for the same reason when except priority in countries other than US, disclosure of this application is to be cited in full text
Mode is incorporated herein.
Claims (15)
1. a kind of source electrode driver, comprising:
Data driver generates data voltage according to the first clock signal by conversion come received image data；
Clock generator, when generating second with the frequency different from first clock signal according to external setting information
Clock signal；
Sensor, according to the second clock signal come periodically sensor pixel；And
Sensing data about the pixel are emitted to timing controller by output unit.
2. source electrode driver according to claim 1, wherein the data driver receive according to the sensing data come
The image data of calibration.
3. source electrode driver according to claim 1, wherein the clock generator is by being connected to special pin (pin)
The setting value of external circuit obtain the setting information.
4. source electrode driver according to claim 1 connects wherein the setting information is contained in from the timing controller
In the control signal of receipts.
5. source electrode driver according to claim 1, wherein the clock generator includes:
Voltage generator generates multiple voltages；
Voltage selector selects one in the multiple voltage according to the setting information；And
VCO (Voltage Controlled Oscillator), determines frequency according to selected voltage.
6. source electrode driver according to claim 1, wherein the clock generator based on first clock signal come
Generate the second clock signal.
7. source electrode driver according to claim 6, wherein the clock generator includes:
First counter generates the 1/N with first clock signal by being counted to first clock signal
The reference signal of the frequency of (N is natural number) again；
VCO (Voltage Controlled Oscillator) determines the frequency for being used for the second clock signal；
Second counter generates the 1/M with the output signal from the VCO by being counted to output signal
The feedback signal of the frequency of (M is natural number) again；And
Comparator controls the VCO by comparing the reference signal and the feedback signal.
8. source electrode driver according to claim 7, wherein the setting information include for first counter with
And the setting value of second counter.
9. source electrode driver according to claim 6, wherein the clock generator includes signal combiner, the signal
Combiner receives multiple reference signals with identical frequency and a certain phase difference relative to first clock signal, with
And the second clock signal is generated by executing exclusive or (XOR:Exclusive OR) operation to the multiple reference signal.
10. source electrode driver according to claim 6, wherein the clock generator includes:
Signal combiner, receiving has the more of the identical frequency and a certain phase difference relative to first clock signal
A reference signal, and to generate the P with first clock signal, (P is nature by combining the multiple reference signal
Number) times frequency multiplication (multiplication) signal；And
Counter generates the 1/Q (Q is natural number) with the multiplied signal times by being counted to the multiplied signal
Frequency the second clock signal.
11. a kind of panel driving system, comprising:
Timing controller, receiving about the sensing data of each pixel and transmitting includes being calibrated according to the sensing data
The clock-embedded signal of image data；And
At least one source electrode driver receives the clock-embedded signal from the timing controller, by from when the insertion
The first clock signal, control signal and described image data are isolated in clock signal to restore first clock signal, described
Signal and described image data are controlled, institute is different to generate to have according to the setting information being contained in the control signal
The second clock signal for stating the frequency of the first clock signal is produced by sensing the pixel according to the second clock signal
The raw sensing data, and the sensing data are emitted to the timing controller.
12. panel driving system according to claim 11, including multiple source electrode drivers,
Wherein the multiple source electrode driver is based on usually producing from received first clock signal of the timing controller
The raw second clock signal.
13. panel driving system according to claim 11, wherein at least one described source electrode driver is based on described the
One clock signal and generate the M/N (M is the natural number that natural number and N are greater than M) with first clock signal times
The second clock signal of frequency.
14. panel driving system according to claim 13, wherein the setting information includes indicating the setting of M and N
Value.
15. panel driving system according to claim 11, wherein the source electrode driver is believed using the second clock
The sense period of the pixel number is indicated as sampling clock.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020160053397A KR102634474B1 (en) | 2016-04-29 | 2016-04-29 | Panel driving system and source driver |
| KR10-2016-0053397 | 2016-04-29 | ||
| PCT/KR2017/003890 WO2017188625A1 (en) | 2016-04-29 | 2017-04-11 | Panel driving system and source driver |
Publications (2)
| Publication Number | Publication Date |
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| CN109074780A true CN109074780A (en) | 2018-12-21 |
| CN109074780B CN109074780B (en) | 2022-10-04 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201780026412.4A Active CN109074780B (en) | 2016-04-29 | 2017-04-11 | Panel driving system and source driver |
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| Country | Link |
|---|---|
| KR (1) | KR102634474B1 (en) |
| CN (1) | CN109074780B (en) |
| WO (1) | WO2017188625A1 (en) |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN113053277A (en) * | 2021-04-20 | 2021-06-29 | 合肥京东方显示技术有限公司 | Display panel and driving device and driving method thereof |
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| KR102074470B1 (en) * | 2018-06-28 | 2020-02-06 | 엑셀로 주식회사 | Apparatus for measuring state of a heated member and Controlling method thereof |
| KR102655048B1 (en) * | 2018-12-12 | 2024-04-05 | 엘지디스플레이 주식회사 | Electroluminescence display |
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| KR101981677B1 (en) * | 2012-12-14 | 2019-08-28 | 엘지디스플레이 주식회사 | Organic Light Emitting Display Device and Method for Operating The Same |
| KR101983764B1 (en) * | 2012-12-24 | 2019-05-29 | 엘지디스플레이 주식회사 | Organic light emitting display and method for driving the same |
| KR20150033903A (en) * | 2013-09-25 | 2015-04-02 | 엘지디스플레이 주식회사 | Organic light emitting diode display device and driving method the same |
| KR102102251B1 (en) * | 2013-12-24 | 2020-04-20 | 엘지디스플레이 주식회사 | Organic light emitting display device |
| KR102126546B1 (en) * | 2013-12-30 | 2020-06-24 | 엘지디스플레이 주식회사 | Interface apparatus and method of display device |
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2016
- 2016-04-29 KR KR1020160053397A patent/KR102634474B1/en active IP Right Grant
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- 2017-04-11 WO PCT/KR2017/003890 patent/WO2017188625A1/en active Application Filing
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| CN101567677A (en) * | 2009-04-10 | 2009-10-28 | 曜鹏亿发(北京)科技有限公司 | Reference clock frequency generator |
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Also Published As
| Publication number | Publication date |
|---|---|
| WO2017188625A1 (en) | 2017-11-02 |
| KR102634474B1 (en) | 2024-02-06 |
| CN109074780B (en) | 2022-10-04 |
| KR20170123973A (en) | 2017-11-09 |
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