CN109065544B - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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CN109065544B
CN109065544B CN201810949566.7A CN201810949566A CN109065544B CN 109065544 B CN109065544 B CN 109065544B CN 201810949566 A CN201810949566 A CN 201810949566A CN 109065544 B CN109065544 B CN 109065544B
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layer
pad
pad structures
semiconductor device
layers
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CN109065544A (en
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李起洪
皮昇浩
孙玄洙
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SK Hynix Inc
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SK Hynix Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/50—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the boundary region between the core region and the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/50—EEPROM devices comprising charge-trapping gate insulators characterised by the boundary region between the core and peripheral circuit regions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76895—Local interconnects; Local pads, as exemplified by patent document EP0896365
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49838—Geometry or layout
    • H01L23/49844—Geometry or layout for devices being provided for in H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
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Abstract

A semiconductor device is provided which at least partially achieves a reduction in contact area by forming a pad portion of a word line using an asymmetric stepped shape formed separately in a first pad structure and a second pad structure. The contact area is reduced compared to the manufacturing processes known in the art. This results in improved device integration and reduced manufacturing process complexity.

Description

Semiconductor device and method for manufacturing the same
The present application is a divisional application of a chinese invention patent application with application number 201310166162.8 and the name of "semiconductor device and method of manufacturing the same" filed in the national intellectual property office of the people's republic of China on the 05 th 08 th 2013.
Technical Field
The present invention relates generally to a semiconductor device and a method of manufacturing the same, and more particularly, to a three-dimensional semiconductor device and a method of manufacturing the same.
Background
A nonvolatile memory device is a memory device that can retain data stored therein even if power is removed. Recently, in response to the recognition that two-dimensional memory devices are approaching the limit of device integration, three-dimensional nonvolatile memory devices in which memory cells are vertically stacked on a silicon substrate have been developed. The memory cells are formed as a layer on a silicon substrate of a two-dimensional memory device.
By applying appropriate bias voltages to word lines stacked on a substrate, the three-dimensional nonvolatile memory device accesses a desired memory cell. When manufacturing the memory cell, the pad portions of the respective word lines are defined by patterning the contact regions of the stacked word lines into a stepped structure and then connecting the contact plugs to the pad portions of the word lines. In fabrication, an etching process is repeatedly performed by reducing one mask so as to pattern the stacked word lines into a desired stepped structure. As a result, the process of manufacturing the memory device is complex and difficult to implement smoothly. Because the contact area in the memory device is large, it is difficult to improve the integration of the memory device. In particular, it is difficult to improve the storage capacity while maintaining a high level of performance and reliability.
Disclosure of Invention
Example embodiments of the present invention relate to a semiconductor device featuring an improved device integration and simplified manufacturing process.
The semiconductor device according to the embodiment of the invention comprises: n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1; n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and a unit structure disposed between the first pad structure and the second pad structure. In the first pad structure, at least one uppermost step and at least one lowermost step respectively include one first layer stack, and the other steps include 2n first layer stacks. In the second pad structure, at least one uppermost step and at least one lowermost step respectively include one second layer stack, and the other steps include 2n second layer stacks.
The storage system according to an embodiment of the present invention includes: a memory controller; and a nonvolatile memory device including a semiconductor device, the semiconductor device including: n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1; n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and a unit structure disposed between the first pad structure and the second pad structure; wherein, in the first pad structure, at least one uppermost step and at least one lowermost step respectively include one first layer stack, and the other steps include 2n first layer stacks; and in the second pad structure, at least one uppermost step and at least one lowermost step respectively include one second layer stack, and the other steps include 2n second layer stacks.
The semiconductor device according to the present invention can improve the integration by reducing the contact area. The method of manufacturing the semiconductor device can be simplified in which the pad portions of the lower select line, the upper select line, and the word line can be easily formed.
Drawings
The above and other features and advantages of the present invention will become more readily appreciated by reference to the following detailed description when considered in conjunction with the accompanying drawings, in which:
fig. 1 is a perspective view showing a semiconductor device according to an embodiment of the present invention;
fig. 2a to 4c are views showing a process of manufacturing a semiconductor device according to an embodiment of the present invention;
fig. 5 is a perspective view showing a semiconductor device according to another embodiment of the present invention;
fig. 6a to 9d are views showing a process of manufacturing a semiconductor device according to another embodiment of the present invention;
fig. 10 is a block diagram showing a configuration of a storage system according to an embodiment of the present invention; and
FIG. 11 is a diagram illustrating a computing system according to one embodiment of the invention.
Detailed Description
Hereinafter, embodiments of the present invention will be described in more detail with reference to the accompanying drawings. This invention may, however, be embodied in different forms and should not be construed as limited to the embodiments set forth herein.
Fig. 1 is a perspective view illustrating a semiconductor device according to an embodiment of the present invention. For convenience of description, fig. 1 shows only the cell structure and the pad structure.
As shown in fig. 1, the semiconductor device may include a cell structure C and first and second pad structures P11 to P22 formed on a substrate (not shown). In the substrate, a cell region CR and first and second contact regions CT1-1 to CT1-3 and CT2-1 to CT2-3 located at both sides of the cell region CR are defined.
The first contact regions CT1-1 to CT1-3 should be interpreted as representing regions where the first pad structures P11 and P12 are to be formed. For example, the first contact regions CT 1-CT 1-3 may include a contact region CT1-1 of an upper select line, a contact region CT1-2 of a word line, and a contact region CT1-3 of a lower select line. The second contact regions CT2-1 to CT2-3 should be interpreted as representing regions where the second pad structures P21 and P22 are to be formed. For example, the second contact regions CT2-1 through CT2-3 may include the contact region CT2-1 of the upper select line, the contact region CT2-2 of the word line, and the contact region CT2-3 of the lower select line. The cell region CR represents a region where the cell structure C is to be formed, and may be disposed between the first contact regions CT1-1 to CT1-3 and the second contact regions CT2-1 to CT2-3.
The cell structure C and the first to second pad structures P11 to P22 may be formed by selectively etching one laminated structure. For example, the cell structure C and the first to second pad structures P11 to P22 may be connected to each other. Hereinafter, it is assumed that one laminated structure is divided into a cell structure C and first to second pad structures P11 to P22.
The first pad structures P11 and P12 include a first layer stack, and are connected to one side of the cell structure C. For example, n first pad structures P11 and P12 are formed in the first contact regions CT1-1 to CT1-3, n being, for example, 2 (n must be a natural number greater than or equal to 1). In each of the first pad structures P11 and P12, at least one uppermost step and at least one lowermost step may be formed with one first stacked layer, respectively, while other steps are formed with 2n first stacked layers, n being 2, for example. As a result, the respective first pad structures P11 and P12 are arranged in a stepped structure. The uppermost step and the lowermost step of the other steps in the first pad structures P11 and P12 may be formed using 2n or less first stacked layers, respectively. In this example, n is 2.
The second pad structures P21 and P22 include a second layer stack, and are connected to the other side of the cell structure C. Specifically, the second pad structures P21 and P22 are disposed opposite to the first pad structures P11 and P12. n second pad structures P21 and P22 are formed in the second contact regions CT2-1 to CT2-3, n being, for example, 2. In each of the second pad structures P21 and P22, at least one uppermost step and at least one lowermost step may be formed with one second lamination layer, respectively, while other steps are formed with 2n second lamination layers, n being 2, for example. As a result, the respective second pad structures P21 and P22 are arranged in a stepped structure. The uppermost step and the lowermost step of the other steps in the second pad structures P21 and P22 may be formed using 2n or less second stacked layers, respectively. For example, n is 2.
The cell structure C is formed in the cell region CR and is disposed between the first pad structures P11 and P12 and the second pad structures P21 and P22. The cell structure C may include a third layer stack and a channel layer (not shown) penetrating the third layer stack in a stacking direction of the third layer stack.
Each of the first to third layer stacks may include an interlayer insulating layer and a conductive layer. For example, the first layer stack may include a first interlayer insulating layer and a first conductive layer, the second layer stack may include a second interlayer insulating layer and a second conductive layer, and the third layer stack may include a third interlayer insulating layer and a third conductive layer. The first to third conductive layers formed on the same level are connected to each other, and the first to third interlayer insulating layers formed on the same level are connected to each other. At least one uppermost conductive layer of the first to third conductive layers may be an upper selection line, at least one lowermost conductive layer of the first to third conductive layers may be a lower selection line, and other layers of the first to third conductive layers may be word lines.
The first and second pad structures P11 to P22 extend in a direction opposite to the cell structure and are arranged in a stepped structure. That is, the first and second pad structures P11 to P22 extend in the first direction I-I'. The second pad structures P21 to P22 extend in a direction opposite to the extending direction of the first pad structures P11 and P12.
In the first and second pad structures P11 to P22 arranged in a stepped structure, the ends of the laminated layers are exposed at the upper surfaces of the respective steps. Hereinafter, the portion exposed at the upper surface of the corresponding step will be defined as a pad portion of the stacked layer. For example, in the case where at least one uppermost stacked layer of the stacked structure includes an upper selection line, at least one lowermost stacked layer of the stacked structure includes a lower selection line, and the other stacked layers include word lines, pad portions are defined at end portions of the stacked lower selection line, word line, and upper selection line, respectively.
Specifically, the first pad structures P11 and P12 adjacent in the second direction II-II 'have a one-level step difference, and the second pad structures P21 and P22 adjacent in the second direction II-II' have a one-level step difference. The pair of first and second pad structures P11/P21 and P12/P22 facing each other has an n-level step difference, n being, for example, 2. Thus, the first pad structures P11 and P12 are asymmetric, and the second pad structures P21 and P22 are asymmetric. The first pad structures P11 and P12 and the second pad structures P21 and P22 facing each other are asymmetric.
In the first and second pad structures P11 to P22, at least one of the uppermost step and the lowermost step has a symmetrical stepped shape, and the other steps have asymmetrical stepped shapes. The pad portions of the upper and lower selection lines formed by using the symmetrical step shape have substantially the same height without a step difference. Thus, the lower selection transistor and the upper selection transistor of the memory string included in the same memory block can be easily controlled. Since the pad portions of the word line formed by using the asymmetric stepped shape are separately formed in the first and second pad structures P11 to P22, the area of the contact region according to the present invention is smaller than that of the related art.
In fig. 1, the reference numerals of the etched layer stack are written on the pad portions to show the step differences between the pad portions. For example, the pad portion of the lower select line is defined by etching thirteen of the layers of contact regions CT1-3 and CT2-3, and the pad portion of the upper select line is defined without etching any of the layers of contact regions CT1-1 and CT 2-1. Twelve pad portions for the word line are defined by selectively etching the stacked layers in contact regions CT1-2 and CT 2-2.
The number of layers in fig. 1 is 14, but the number of layers is not limited to 14. The number of layers in a stacked structure may vary depending on the number of select transistors and memory cells in a memory string.
Fig. 2a to 4c are views illustrating a process of manufacturing a semiconductor device according to an embodiment of the present invention. Fig. 2a, 3a and 4a show a layout, and fig. 2B, 3B, 4B and 4c show a section taken along line A-A 'or line B-B'.
As shown in fig. 2a and 2b, the stacked layers 11 to 36 are formed on a substrate (not shown), and the cell region CR, and the first and second contact regions CT1-1 to CT1-3 and CT2-1 to CT2-3 (located at both sides of the cell region CR) are defined in the substrate.
At least one uppermost layer stack 36 of the layer stacks 11 to 36 is a layer for forming an upper select line, at least one lowermost layer stack 11 of the layer stacks 11 to 36 is a layer for forming a lower select line, and the other layer stacks 12 to 35 are layers for forming a word line.
Each of the layer stacks 11 to 36 may comprise a first material layer 1 and a second material layer 2. For example, the second material layer 2 and the first material layer formed under the second material layer 2 form one layer stack 11 to 36, or the second material layer 2 and the first material layer 1 formed on the second material layer 2 form one layer stack 11 to 36. The laminated structure may include the first material layers 1 and the second material layers 2 alternately laminated.
The first material layer 1 is a layer for forming word lines or selection lines, and the second material layer 2 is a layer for dividing stacked conductive layers. The thickness of the first material layer 1 may vary according to the application. The conductive layer for the selection line may be formed to have substantially the same thickness as the conductive layer for the word line. The conductive layer of the selection line may be formed to have a thickness different from that of the conductive layer for the word line, for example, a thickness greater than that of the conductive layer for the word line.
The first material layer 1 is formed using a material having a high etching selectivity with respect to the second material layer 2, and the second material layer 2 is formed using a material having a high etching selectivity with respect to the first material layer 1. For example, the first material layer 1 may be formed using a conductive layer such as a polysilicon layer, and the second material layer 2 may be formed using an insulating layer such as an oxide layer. As another example, the first material layer 1 may be formed using a conductive layer such as a doped polysilicon layer, a doped amorphous silicon layer, or the like, and the second material layer 2 may be formed using a sacrificial layer such as an undoped polysilicon layer, an undoped amorphous silicon layer, or the like. As another example, the first material layer may be formed using a sacrificial layer such as a nitride layer, and the second material layer 2 may be formed using an insulating layer such as an oxide layer.
Subsequently, a process (not shown) of forming the memory cells in the cell structure C may be performed. For example, a hole is formed through the cell structure C, and then a memory layer is formed in the hole. The storage layer may include at least one of a charge blocking layer, a data storage layer, and a tunnel insulating layer. The data storage layer may include at least one of a floating gate (such as a polysilicon layer) for storing charges, a trap layer (such as nitride) for trapping charges, nanodots, and a phase change material layer. The channel layer is formed on the memory layer.
Next, a first mask pattern 37 is formed on the stacked layers 11 to 36, and then the stacked layer 36 is first etched by using the first mask pattern 37 as an etching stopper. For example, the first mask pattern 37 is formed to expose the contact regions CT1-3 and CT2-3 of the lower selection lines among the first contact regions CT1-1 through CT1-3 and the second contact regions CT2-1 through CT2-3.
A first etching is performed so as to form a pad portion of a lower selection line in the nonvolatile memory device. In the case where one memory string includes a plurality of lower selection transistors, a process of reducing the first mask pattern 37 and then first etching one layer stack using the reduced first mask pattern 37 is repeatedly performed to form a pad portion of the lower selection line.
Subsequently, the first mask pattern 37 is reduced, and then the 2n stacked layers 32 to 35 are second etched by using the reduced first mask pattern 37 as an etching stopper, for example, n is 2. In this operation, the laminated layer 36 that was previously etched is etched together with the laminated layers 32 to 35, thereby maintaining the step difference between the laminated layer 36 and the laminated layers 32 to 35. Next, the process of reducing the first mask pattern 37 and then etching 2n layers 28 to 31 using the reduced first mask pattern 37 is repeatedly performed, n being, for example, 2.
Subsequently, the first mask pattern 37 is reduced, and then the layer stack 35 is third etched by using the reduced first mask pattern 37 as an etching stopper. For example, the first mask pattern 37 is reduced to cover the cell region CR and the contact regions CT1-1 and CT2-1 of the upper selection line, and exposes the contact regions CT1-3 and CT2-3 of the lower selection line.
A third etching is performed so as to form a pad portion of an upper select line in the nonvolatile memory device. In the case where one memory string includes a plurality of upper selection transistors, the process of reducing the first mask pattern 37 and then third etching one layer stack 35 using the reduced first mask pattern 37 is repeatedly performed to form a pad portion of the upper selection line.
The stacked structure is patterned into a stepped structure by performing first to third etches such that the pad portion of the lower selection line and the pad portion of the upper selection line are formed. At least one of the first to third etches may be repeatedly performed. The pad portion of the word line is not completed through the above-described process, but is completed through further patterning of the stacked structure as described below.
The individual steps in the laminated structure may have substantially the same or different widths. For example, the lower step may be wider than the upper step in consideration of an alignment margin (alignment margin) between a contact plug and a pad portion formed by the following process. The magnitude of the decrease in the first mask pattern 37 may be decreased or increased every time the first mask pattern 37 is decreased, and thus the width of the pad portion may be adjusted.
As shown in fig. 3a to 3c, a second mask pattern 38 is formed on the laminated structure, and then the laminated layers 15, 19, 23, 27, 31 and 35 are etched by using the second etching mask 38 as an etching stopper. The second mask pattern 38 is used to form a step difference between the adjacent first pad structures P11 and P12 and a step difference between the adjacent second pad structures P21 and P22. Thus, the second mask pattern 38 may be formed to expose the pair of first and second pad structures P11 and P21 facing each other and cover the cell structure C and the other first and second pad structures P12 and P22. In fig. 3a, the reference numerals of the etched stack-up structure are shown on the first and second pad structures P11-P22.
It is contemplated that the second mask pattern 38 may be formed to further cover the end portions of the pair of first and second pad structures P11 and P12 facing each other. The ends may be contact areas CT1-1 and CT2-1 of the upper select line and contact areas CT1-3 and CT2-3 of the lower select line. That is, an etching process is performed while covering the end portions with the second mask pattern 38, and thus pad portions of the upper and lower selection lines, which are formed in advance, are etched. As a result, a step difference may not be formed between the pad portions.
The width of the region of the second mask pattern 38 covering the end portion may be wider than the widths of the contact regions CT1-1, CT2-1, CT1-3, and CT2-3 of the upper and lower selection lines, as indicated by the opposite arrows in fig. 3a, to ensure an etching margin (etch margin). In this case, the lowermost-stepped laminated layer 15 of the laminated structure may be incompletely etched, and a dummy structure (dummy structure) D is formed as shown in fig. 3 b.
As shown in fig. 4a to 4c, a third mask pattern 39 is formed on the laminated structure, and then n laminated layers, n being for example 2, are etched by using the third mask pattern 39 as an etching stopper. The third mask pattern 39 is used to form a step difference between the first pad structures P11 and P12 and the second pad structures P21 and P22 facing each other. Thus, the third mask pattern 39 may be formed to expose the second pad structures P21 and P22 and cover the cell structure C and the first pad structures P11 and P12. In an alternative embodiment, the third mask pattern 39 may be formed to expose the first pad structures P11 and P12 and cover the cell structure C and the second pad structures P21 and P22.
In this instance, the third mask pattern 39 may be formed to further cover the ends of the exposed first pad structures P11 and P12 or to cover the ends of the exposed second pad structures P21 and P22. The ends may be contact areas CT1-1 or CT2-1 of the upper select line and contact areas CT1-3 or CT2-3 of the lower select line. That is, the etching process is performed under the condition that the end portion is covered with the third mask pattern 39, and thus pad portions of the upper and lower selection lines formed in advance are etched. As a result, a step difference may not be formed between the pad portions.
The width of the region of the third mask pattern 39 covering the end portion may be wider than the widths of the contact regions CT1-1, CT2-1, CT1-3 and CT2-3 of the upper and lower selection lines, as indicated by the opposite arrows in fig. 4a, to ensure an etching margin. In this case, the lowermost-stepped lamination layers 13/14/15 and 14/15 of the lamination structure may be incompletely etched, and a dummy structure D is formed as shown in fig. 4b and 4 c. The dummy structure D appears on the lowermost level of the other levels in the first and second pad structures P11 to P22.
As a result, a step difference is formed between the first and second pad structures P11 to P22. That is, a step is formed between adjacent first and second pad structures P11 to P22 in the second direction II-II ', and a step is formed between first and second pad structures P11 to P22 facing in the first direction I-I'.
In an embodiment, a step difference may be formed between the facing first and second pad structures P11 to P22 by using the third mask pattern 39, and then a step difference may be formed between the adjacent first and second pad structures P11 to P22 in the second direction II-II' by using the second mask pattern 38.
Thus, the first and second pad structures P11 to P22 having the asymmetric stepped shape are formed. Specifically, in the first and second pad structures P11 to P22, the stacked layers 12 to 35 for the word lines may have an asymmetric stepped shape, and the stacked layer 11 for the lower selection line and the stacked layer 36 for the upper selection line may have a symmetric stepped shape.
Subsequently, a process (not shown) of forming a memory cell may be further performed. Hereinafter, a process performed according to the properties of the first material layer 1 and the second material layer 2 will be described.
In one embodiment, the first material layer 1 may be formed using a conductive layer, and the second material layer 2 may be formed using an insulating layer. At least one slit is formed through the laminated layers 11 to 36, and then the first material layer 1 exposed through the slit is silicided. Subsequently, the slit is filled with an insulating layer. During this process step, an air gap may be formed in the slit depending on the method of depositing the insulating layer.
In another embodiment, the first material layer 1 may be formed using a conductive layer, and the second material layer 2 may be formed using a sacrificial layer. At least one slit is formed through the laminated layers 11 to 36, and then the exposed second material layer 2 in the slit is removed. Subsequently, the region from which the second material layer 2 is removed and the slit are filled with an insulating layer. In this case, an air gap may be formed in the slit or in the region where the second material layer 2 is removed depending on the method of depositing the insulating layer.
In yet another embodiment, the first material layer 1 may be formed using a sacrificial layer and the second material layer 2 may be formed using an insulating layer. At least one slit is formed through the laminated layers 11 to 36, and then the exposed first material layer 1 in the slit is removed. Subsequently, word lines, selection lines, and the like are formed by filling the region from which the first material layer 1 is removed with a conductive layer such as tungsten W. Next, the slit is filled with the insulating layer 40. In this process step, an air gap may be formed in the slit depending on the method of depositing the insulating layer.
As described above, since the laminated structure in which 2n laminated layers are formed in one step is patterned to have a stepped shape or is provided in a stepped structure, a process of forming the pad portion can be simplified as compared with the conventional art, where n is 2, for example. The pad portion of the upper select line and the pad portion of the lower select line may be symmetrically formed, and then the pad portion of the word line may be asymmetrically formed. As a result, the pad portion can be efficiently formed in a reduced area.
Fig. 5 is a perspective view illustrating a semiconductor device according to another embodiment of the present invention. For convenience of description, fig. 5 only shows the cell structure and the pad structure. Hereinafter, further description about the same elements as in fig. 1 will be omitted.
As shown in fig. 5, the semiconductor device according to the embodiment may include a cell structure in the cell region CR and first and second pad structures P11 to P23 in the first and second contact regions CT1-1 to CT1-3 and CT2-1 to CT 2-3. Here, n first pad structures P11 to P13 are provided in the first contact regions CT1-1 to CT1-3, n being, for example, 3.n second pad structures P21 to P23 are disposed in the second contact regions CT2-1 to CT2-3, n being, for example, 3. In each of the first and second pad structures P11 to P23, at least one uppermost step and at least one lowermost step are formed as one laminated layer, respectively, while the other steps are formed as 2n laminated layers, respectively, n being, for example, 3. The first and second pad structures P11 to P23 are arranged in a stepped structure. The uppermost step and the lowermost step among the other steps may be formed as a stack of 2n or less layers, n being 3, for example.
For example, the pad portion of the lower selection line is formed by etching nineteen stacks of contact regions CT1-3 and CT2-3, and the pad portion of the upper selection line is defined without etching any stack of contact regions CT1-1 and CT 2-1. Eighteen pad portions of the word line are defined by selectively etching the stacked layers in contact regions CT1-2 and CT 2-2.
Fig. 6a to 9d are views illustrating a process of manufacturing a semiconductor device according to another embodiment of the present invention. Fig. 6a, 7a, 8a and 9a show layout diagrams, fig. 6B, 7B and 7C, fig. 8B to 8d, and fig. 9B to 9d show cross-sectional diagrams taken along the line A-A ', B-B ' or C-C '.
As shown in fig. 6a and 6b, the layer stacks 61-86 are formed on a substrate (not shown). A cell region CR, and first and second contact regions CT1-1 to CT1-3 and CT2-1 to CT2-3 (disposed at both sides of the cell region CR) are defined in the substrate.
A first mask pattern 87 is formed on the stacked layers 61 to 86, and then the stacked layers 86 are first etched using the first mask pattern 87 as an etching stopper. Subsequently, the first mask pattern 87 is reduced, and then the 2n stacked layers 80 to 85 are second etched by using the reduced first mask pattern 87 as an etching stopper, n being, for example, 3. Then, the first mask pattern 87 is reduced, and then the third etching of the layer stack 62 is performed using the first mask pattern 87 as an etching barrier. As a result, pad portions of the upper and lower select lines are defined.
As shown in fig. 7a to 7c, a second mask pattern 88 is formed on the laminate layer, and then the laminate layer 85 is etched by using the second mask pattern 88 as an etching stopper. As a result, a one-layer step difference is formed between the first pad structure P11/P12 and the second pad structure P21/P22.
Here, the second pad pattern 88 may be formed to expose the pair of first and second pad structures P11 and P21 facing each other and cover the cell structure C and the other first and second pad structures P12, P13, P22, and P23. The second mask pattern 88 may be formed to further cover the exposed end portions of the pair of first and second pad structures P11 and P21.
The width of the region of the second mask pattern 88 covering the end portion may be wider than the contact regions CT1-1, CT2-1, CT1-3, and CT2-3 of the upper and lower selection lines. As a result, the lowermost-stepped laminated layer 67 of the laminated structure is incompletely etched, so that the dummy structure D is formed.
As shown in fig. 8A to 8d, the second mask pattern 88A is reduced in the second direction II-II' to further expose the facing first and second pad structures P12 and P22, and then the stacked layers 84 and 85 are etched by using the reduced second mask pattern 88A as an etch barrier.
As a result, a level difference of one layer is formed between the adjacent first pad structures P11 to P13 in the second direction II-II ', and a level difference of one layer is formed between the adjacent second pad structures P21 to P23 in the second direction II-II'. The process of reducing the second mask pattern 88A and etching the stacked layers using the reduced second mask pattern 88A is repeatedly performed until a step difference is formed between each of the pad structures P11/P12/P13 and P21/P22/P23 in the same contact region. For example, in the case where the first contact regions CT1-1 to CT1-3 and the second contact regions CT2-1 to CT2-3 each include n first or second pad structures P11 to P23, the etching process is performed in combination with reducing the second mask pattern 88A (n-1) times.
The etching process may be repeatedly performed by forming a new mask pattern instead of reducing the second mask pattern 88A.
As shown in fig. 9a to 9d, a third mask pattern 89 is formed on the laminated structure, and then n laminated layers, n being for example 3, are etched by using the third mask pattern 89 as an etching stopper. Here, the third mask pattern 89 may be formed to expose the second pad structures P21 to P23 and cover the cell structure C and the first pad structures P11 to P13.
The third mask pattern 89 may be formed to further cover further ends of the exposed second pad structures P21 to P23. The width of the region of the third mask pattern 89 covering the end portion may be wider than the contact regions CT1-1, CT2-1, CT1-3, and CT2-3 of the upper and lower selection lines. As a result, the lowermost-stepped laminated layers 65 to 67 of the laminated structure may not be completely etched, so that the dummy structure D may be formed.
As a result, a step difference is formed between each of the first and second pad structures P11 to P23.
In the above description, some steps in the laminated structure include four or six laminated layers. However, the present invention is not limited to the structure described in the above description. Some steps in the laminated structure may include 2n laminated layers, for example, 2 laminated layers, or eight or more laminated layers.
Fig. 10 is a view showing a configuration of a storage system according to an embodiment of the present invention.
In fig. 10, a memory system 100 of an embodiment of the present invention may include a nonvolatile memory device 120 and a memory controller 110.
The nonvolatile memory device 120 may have the above-described structure. The nonvolatile memory device 120 may be a multi-chip package having a plurality of flash memory chips.
The memory controller 110 controls the nonvolatile memory device 120, and may include an SRAM 111, a CPU 112, a host interface 113, an ECC 114, and a memory interface 115. The SRAM 111 serves as an operation memory for the CPU 112. The CPU 112 performs control operations for data exchange of the memory controller 110, and the host interface 113 has a data exchange protocol for accessing a host of the memory system 100. In addition, the ECC 114 detects and corrects errors in the data read from the nonvolatile memory device 120, and the memory interface 115 interfaces with the nonvolatile memory device 120. The memory controller 110 may also include a ROM or the like that stores data for interfacing with a host.
The storage system 100 may be used as a Solid State Disk (SSD) or a memory card through a combination of the nonvolatile memory device 120 and the memory controller 110. When the storage system 100 is an SSD, the memory controller 110 can communicate with an external device (e.g., host) through one of the interface protocols including USB, MMC, PCI-E, SATA, PATA, SCSI, ESDI and IDE, etc.
FIG. 11 is a diagram illustrating a configuration of a computing system of one embodiment of the invention.
In fig. 11, the computing system 200 of the present embodiment may include a CPU 220, a RAM 230, a user interface 240, a modem 250, and a storage system 210 electrically connected to a system bus 260. When computing system 200 is a mobile device, a battery may be further provided that supplies operating voltage to computing system 200. The computing system 200 of the present invention may also include an application chipset, a CMOS image processor (CIS), and a mobile DRAM.
As depicted in fig. 10, the storage system 210 may include a non-volatile storage device 212 and a memory controller 211.
Although specific embodiments have been described, those skilled in the art will appreciate that the embodiments are merely examples. Various modifications, additions and substitutions are possible, without departing from the spirit and scope of the invention. Thus, the semiconductor devices described herein should not be limited based on the described embodiments. Rather, the semiconductor devices described herein should be limited only in light of the claims in connection with the above description and drawings.
As can be seen from the above embodiments, the present application provides the following technical solutions.
Technical solution 1. A semiconductor device includes:
n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1;
n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and
a cell structure disposed between the first pad structure and the second pad structure;
wherein, in the first pad structure, at least one uppermost step and at least one lowermost step respectively include one first layer stack, and the other steps include 2n first layer stacks; and
in the second pad structure, at least one uppermost step and at least one lowermost step respectively include one second layer stack, and the other steps include 2n second layer stacks.
Technical solution the semiconductor device of claim 1, wherein the step difference of n layers is formed between the facing first and second pad structures.
The semiconductor device according to claim 1, wherein a step of one layer is formed between adjacent first pad structures, and a step of one layer is formed between adjacent second pad structures.
Technical solution the semiconductor device of claim 1, wherein at least one uppermost step of the first pad structure and the second pad structure is an upper select line, at least one lowermost step of the first pad structure and the second pad structure is a lower select line, and the other steps are word lines.
Technical solution the semiconductor device of claim 1, wherein an uppermost step or a lowermost step of the other steps in the first pad structure is formed with 2n or less first stacked layers, and an uppermost step or a lowermost step of the other steps in the second pad structure is formed with 2n or less second stacked layers.
Technical solution the semiconductor device according to claim 1, further comprising:
at least one dummy structure located on a lowermost one of the other steps in the first and second pad structures.
Technical solution the semiconductor device of claim 1, wherein the first pad structure and the second pad structure extend in a direction opposite to the cell structure.
Technical solution the semiconductor device of claim 1, wherein the unit structure comprises:
A third layer stack; and
a channel layer passing through the third layer stack.
The semiconductor device according to claim 8, wherein each of the first stacked layers includes a first interlayer insulating layer and a first conductive layer, each of the second stacked layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stacked layers includes a third interlayer insulating layer and a third conductive layer.
Technical solution the semiconductor device according to claim 9, wherein the first conductive layer to the third conductive layer formed at the same level are connected to each other, and the first interlayer insulating layer to the third interlayer insulating layer formed at the same level are connected to each other.
The semiconductor device according to claim 9, wherein at least one uppermost conductive layer among the first conductive layer to the third conductive layer is an upper select line, at least one lowermost conductive layer among the first conductive layer to the third conductive layer is a lower select line, and the other conductive layers are word lines.
Technical solution the semiconductor device according to claim 9, wherein the first to third interlayer insulating layers are formed of substantially the same material, and the first to third conductive layers are formed of substantially the same material.
Technical solution 13. A storage system includes:
a memory controller; and
a nonvolatile memory device including a semiconductor device, the semiconductor device comprising:
n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1;
n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and
a cell structure disposed between the first pad structure and the second pad structure;
wherein, in the first pad structure, at least one uppermost step and at least one lowermost step respectively include one first layer stack, and the other steps include 2n first layer stacks; and
in the second pad structure, at least one uppermost step and at least one lowermost step respectively include one second layer stack, and the other steps include 2n second layer stacks.
The memory system of claim 13, wherein n-layer step differences are formed between the facing first and second pad structures.
The memory system of claim 13, wherein a level difference of one layer is formed between adjacent first pad structures and a level difference of one layer is formed between adjacent second pad structures.
The semiconductor device according to claim 13, wherein at least one uppermost step of the first pad structure and the second pad structure is an upper select line, at least one lowermost step of the first pad structure and the second pad structure is a lower select line, and the other steps are word lines.
Claim 17. The memory system according to claim 13, wherein an uppermost step or a lowermost step of the other steps in the first pad structure is formed with 2n or less first stacked layers, and an uppermost step or a lowermost step of the other steps in the second pad structure is formed with 2n or less second stacked layers.
The storage system of claim 13, further comprising:
at least one dummy structure located on a lowermost one of the other steps in the first and second pad structures.
Technical solution the memory system of claim 13, wherein the unit structure includes:
A third layer stack; and
a channel layer passing through the third layer stack.
The memory system according to claim 19, wherein each of the first stacked layers includes a first interlayer insulating layer and a first conductive layer, each of the second stacked layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stacked layers includes a third interlayer insulating layer and a third conductive layer.

Claims (20)

1. A semiconductor device, comprising:
n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1;
n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and
a cell structure disposed between the first pad structure and the second pad structure;
wherein each of the first pad structures includes an uppermost step having at least one first layer stack, a lowermost step having one first layer stack, and an intermediate step having 2n first layer stacks, the intermediate step having 2n first layer stacks being located between the uppermost step and the lowermost step; and
Wherein each of the second pad structures includes an uppermost step having at least one second lamination layer, a lowermost step having one second lamination layer, and an intermediate step having 2n second lamination layers, the intermediate step having 2n second lamination layers being located between the uppermost step and the lowermost step,
wherein a step difference of n layers is formed between the facing first pad structure and the second pad structure.
2. The semiconductor device of claim 1, wherein a level difference of one layer is formed between adjacent first pad structures and a level difference of one layer is formed between adjacent second pad structures.
3. The semiconductor device of claim 1, wherein an uppermost step in the first and second pad structures is an upper select line, a lowermost step in the first and second pad structures is a lower select line, and an intermediate step is a word line.
4. The semiconductor device of claim 1, wherein each of the first pad structures comprises at least one intermediate step having less than 2n first layer stacks and each of the second pad structures comprises at least one intermediate step having less than 2n second layer stacks.
5. The semiconductor device of claim 4, wherein in each of the first pad structures, the at least one intermediate step is located between the intermediate step having 2n first layer stacks and the uppermost step, or between the intermediate step having 2n first layer stacks and the lowermost step, and
wherein in each of the second pad structures, the at least one intermediate step is located between the intermediate step having 2n second-layer stacks and the uppermost step or between the intermediate step having 2n second-layer stacks and the lowermost step.
6. The semiconductor device of claim 1, further comprising:
at least one dummy structure located on a lowermost step of an intermediate step in the first and second pad structures.
7. The semiconductor device of claim 1, wherein the first pad structure and the second pad structure extend in a direction opposite the cell structure.
8. The semiconductor device of claim 1, wherein the cell structure comprises:
a third layer stack; and
a channel layer passing through the third layer stack.
9. The semiconductor device according to claim 8, wherein each of the first stacked layers includes a first interlayer insulating layer and a first conductive layer, each of the second stacked layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stacked layers includes a third interlayer insulating layer and a third conductive layer.
10. The semiconductor device according to claim 9, wherein the first conductive layer to the third conductive layer formed at the same level are connected to each other, and the first interlayer insulating layer to the third interlayer insulating layer formed at the same level are connected to each other.
11. The semiconductor device according to claim 9, wherein at least one uppermost conductive layer of the first to third conductive layers is an upper selection line, at least one lowermost conductive layer of the first to third conductive layers is a lower selection line, and the other conductive layers are word lines.
12. The semiconductor device according to claim 9, wherein the first interlayer insulating layer to the third interlayer insulating layer are formed of the same material, and wherein the first conductive layer to the third conductive layer are formed of the same material.
13. A storage system, comprising:
A memory controller; and
a nonvolatile memory device including a semiconductor device, the semiconductor device comprising:
n first pad structures, wherein the first pad structures comprise first laminated layers arranged into a stepped structure, step differences are formed among the first pad structures, and n is a natural number greater than or equal to 1;
n second pad structures including second stacked layers arranged in a stepped structure, a step difference being formed between the second pad structures; and
a cell structure disposed between the first pad structure and the second pad structure;
wherein each of the first pad structures includes an uppermost step having at least one first layer stack, a lowermost step having one first layer stack, and an intermediate step having 2n first layer stacks, the intermediate step having 2n first layer stacks being located between the uppermost step and the lowermost step; and
wherein each of the second pad structures includes an uppermost step having at least one second lamination layer, a lowermost step having one second lamination layer, and an intermediate step having 2n second lamination layers, the intermediate step having 2n second lamination layers being located between the uppermost step and the lowermost step,
Wherein a step difference of n layers is formed between the facing first pad structure and the second pad structure.
14. The memory system of claim 13, wherein a level difference is formed between adjacent first pad structures and a level difference is formed between adjacent second pad structures.
15. The memory system of claim 13, wherein an uppermost step of each of the first and second pad structures is an upper select line, a lowermost step of each of the first and second pad structures is a lower select line, and an intermediate step is a word line.
16. The memory system of claim 13, wherein each of the first pad structures includes at least one intermediate step having less than 2n first layers and each of the second pad structures includes at least one intermediate step having less than 2n second layers.
17. The memory system of claim 16, wherein in each of the first pad structures, the at least one intermediate step is located between the intermediate step having 2n first layer stacks and the uppermost step or between the intermediate step having 2n first layer stacks and the lowermost step, and
Wherein in each of the second pad structures, the at least one intermediate step is located between the intermediate step having 2n second-layer stacks and the uppermost step or between the intermediate step having 2n second-layer stacks and the lowermost step.
18. The storage system of claim 13, further comprising:
at least one dummy structure located on a lowermost step of the intermediate steps in the first and second pad structures.
19. The storage system of claim 13, wherein the cell structure comprises:
a third layer stack; and
a channel layer passing through the third layer stack.
20. The memory system according to claim 19, wherein each of the first stacked layers includes a first interlayer insulating layer and a first conductive layer, each of the second stacked layers includes a second interlayer insulating layer and a second conductive layer, and each of the third stacked layers includes a third interlayer insulating layer and a third conductive layer.
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