CN109062843A - A kind of date storage method and system based on iic bus - Google Patents
A kind of date storage method and system based on iic bus Download PDFInfo
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- CN109062843A CN109062843A CN201810759187.1A CN201810759187A CN109062843A CN 109062843 A CN109062843 A CN 109062843A CN 201810759187 A CN201810759187 A CN 201810759187A CN 109062843 A CN109062843 A CN 109062843A
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/06—Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication
- G06F12/0615—Address space extension
- G06F12/0623—Address space extension for memory modules
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- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
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Abstract
The present invention relates to a kind of, and date storage method and system based on iic bus pre-process the data to be written behind distribution address, and pretreated data are stored this method comprises: distributing address to data to be written；If wherein preprocessing process includes: the length that total length of data to be written is greater than IIC peripheral hardware fifo queue in controller, data are written into according to the length of IIC peripheral hardware fifo queue and split into multiple queues；And it is every store a queue by memory Best-case Response Time period, and in each queue data to be written address in a page of memory.The present invention carries out preprocessing process to the data to be written behind distribution address by distributing address to data to be written, avoids automatic page turning phenomenon when data write-in；The design that data are transmitted in batches in the form of queue simultaneously, improves program efficiency, improves hardware efficiency.
Description
Technical field
The present invention relates to a kind of date storage method and system based on iic bus, belongs to technical field of data storage.
Background technique
Solar energy is more and more common in social life as inexhaustible new energy.As light
Tie link between volt power generation and power distribution network, inverter become more and more important in photovoltaic generating system, it is therefore desirable to real
Shi Jilu invertor operation situation.
EEPROM is the modifiable read-only memory of user, can wipe and rearrange by being higher than the effect of common voltage
Journey, therefore EEPROM is widely used.EEPROM has a feature, and write-in data will appear a page flop phenomenon, if passing through (IIC)
I2C bulk transfer data are written to EEPROM, will be unable to be written page by page.In addition, EEPROM receives the data that I2C is transmitted
Afterwards, hardware needs the regular hour to be written.So on the one hand repeating to adjust if calling I2C only to transmit a byte every time
With will increase I2C occupancy and time, the delay regular hour makes EEPROM write-in hard after a byte is on the other hand often finished
Part greatly reduces execution efficiency again.
Summary of the invention
The object of the present invention is to provide a kind of date storage method and system based on iic bus is being written for solving
How to avoid the problem that page is overturn when data.
In order to solve the above technical problems, step is such as the present invention provides a kind of date storage method based on iic bus
Under:
Address is distributed to data to be written, the data to be written behind distribution address are pre-processed, and will pretreatment
Data afterwards are stored；If wherein preprocessing process includes: that total length of data to be written is greater than IIC peripheral hardware FIFO in controller
The length of queue is then written into data according to the length of IIC peripheral hardware fifo queue and splits into multiple queues；And it is every by one
The memory Best-case Response Time period stores a queue, and in each queue data to be written address at one of memory
In the page.
The beneficial effects of the present invention are: address is distributed to data to be written, to the data to be written behind distribution address
Length is judged, if more than the length of IIC peripheral hardware fifo queue in controller, is then written into data according to IIC peripheral hardware
The length of fifo queue splits into multiple queues, and sends memory in batches in the form of queue, when avoiding data write-in
Automatic page turning phenomenon, while improving program efficiency, avoid and be commonly synchronously written after mode transmitted a byte
The operation of the entire control program of delay obstruction, improves hardware efficiency.
Further, in order to improve the speed of data storage, if further including total length of data to be written no more than controller
The length of middle IIC peripheral hardware fifo queue is then directly written into data and stores according to the address of distribution to the corresponding page of memory
In face.
The present invention also provides a kind of data-storage system based on iic bus, including processor and memory, the places
It manages and is connected between device and memory by iic bus；The processor is used to distribute address to data to be written, to distributively
Data to be written behind location are pre-processed, and pretreated data are stored；If wherein preprocessing process include: to
The length that total length of data is greater than IIC peripheral hardware fifo queue in controller is written, then is written into data according to IIC peripheral hardware FIFO
The length of queue splits into multiple queues；And it is every by memory Best-case Response Time period one queue of storage, and often
The address of data to be written is in a page of memory in a queue.
Further, if the processor is also used to total length of data to be written no more than IIC peripheral hardware FIFO in controller
The length of queue is then directly written into data and stores according to the address of distribution into the corresponding page of memory.
Further, the memory is EEPROM.
Detailed description of the invention
Fig. 1 is the logic chart of the date storage method the present invention is based on iic bus；
Fig. 2 is the main program flow chart of the date storage method the present invention is based on iic bus；
Fig. 3 is to write data program flow chart；
Fig. 4 is the step flow chart of present invention data prediction to be written；
Fig. 5 is to read data program flow diagram；
Fig. 6 is interrupt function flow chart.
Specific embodiment
In order to make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with attached drawing and specific implementation
The present invention will be described in further detail for example.
The present invention provides a kind of data-storage system based on iic bus, the data-storage system include processor and
Memory, in the present embodiment, the memory are EEPROM.It is connected between processor and memory by iic bus, passes through phase
Mutually cooperation, to realize a kind of date storage method based on iic bus.
The date storage method based on iic bus is transmitted to EEPROM, every biography after being written into data prediction in batches
Sent a batch, EEPROM write-in a batch, avoid it is every transmit the delay regular hour after one byte allow EEPROM write-in firmly
The problem of part low efficiency, improve program efficiency；It avoids and is commonly synchronously written mode and has transmitted the delay after a byte
The operation of the entire control program of obstruction, improves hardware efficiency.
This saves inverter data using EEPROM based on the date storage method of iic bus, and is passed using IIC form
Transmission of data, to realize the persistence storage of data, wherein the realization of data storage procedure includes main program, writes data program, reads
The programs such as data program, interrupt function, flow chart of steps are as shown in Figure 1, comprising the following steps:
Step 1, after booting powers on, the timer and IIC module of internal system are initialized, circulation is carried out later and sentences
Disconnected control write step.
Step 2, judge every secondary program major cycle after initialization condition it is first determined whether should renewal time information, if
It needs, is then updated temporal information operation, jumps out data storage process after the completion.
Step 3, undated parameter information is decided whether, if it is desired, be then updated parameter information operation, after the completion
Jump out data storage process.
Step 4, decide whether that read failure records, if it is desired, be then read out failure logging operation, after the completion
Jump out data storage process.
Step 5, Write fault record operation is decided whether, if it is desired, Write fault record operation is then carried out, it is complete
Data storage process is jumped out after.
For the ease of being illustrated to data storage procedure, iic bus is abstracted as following seven kinds of states, I2C_
MSGSTAT_INACTIVE unactivated state, I2C_MSGSTAT_SEND_WITHSTOP send band stop position data, I2C_
MSGSTAT_WRITE_BUSY writes data busy condition, I2C_MSGSTAT_SEND_NOSTOP is sent without stop position data, I2C_
MSGSTAT_SEND_NOSTOP_BUSY, which is sent, retransmits start bit without stop position data busy condition, I2C_MSGSTAT_RESTART
State, I2C_MSGSTAT_READ_BUSY read data busy condition.
The main program flow chart of above-mentioned data storage procedure is as shown in Fig. 2, mainly comprise the steps that
(1) before being written, first determine whether iic bus output state is I2C_MSGSTAT_SEND_WITHSTOP hair
Send band stop position data.If so, calling IIC write data function, and obtain the function return value；If it is not, then entering step
(3)。
When the data is written, as shown in figure 3, sending the start bit START first, sending from device address, processing Ack, hair
Byte address, processing Ack are sent, 1 byte data, processing Ack is sent, sends the 2nd byte data, processing Ack, sends the 3rd byte
Data, processing Ack ... are until distributing X byte, sending STOP stop position.
During data storage, need to distribute address to data to be written by processor, after then distributing address
Data prediction to be written after EEPROM is transmitted to by the FIFO in IIC module in batches, EEPROM then will successively be received
Data to be written write-in.Specifically, the step of data prediction to be written, is as shown in figure 4, specifically include:
Step A, if total length of data to be written no more than the length of IIC peripheral hardware fifo queue in controller, directly will
Data to be written are stored into memory EEPROM in the corresponding page according to the address of distribution, no to then follow the steps B.
Step B constructs one if total length of data to be written is greater than the length of IIC peripheral hardware fifo queue in controller
The data transmitted every time, are split as the length of IIC peripheral hardware fifo queue by data transmission queue, that is, are written into data according to outer
If the length of fifo queue splits into multiple queues, every to execute a step A by an EEPROM Best-case Response Time period.
It should be noted that needing the length according to data to be written, outside IIC when to data to be written distribution address
If the length of fifo queue and the length of the EEPROM page specify the addresses of data to be written, to realize in each queue
The address of data to be written is in a page of memory.
By distributing address to data to be written, and preprocessing process is carried out to the data to be written behind distribution address,
Avoid automatic page turning phenomenon when data write-in；The design that data are transmitted in batches in the form of queue simultaneously, improves journey
Sequence efficiency avoids the operation for being commonly synchronously written the entire control program of delay obstruction that mode has transmitted after a byte,
The drawbacks of reducing hardware efficiency.
(2) check whether IIC write data function returns to I2C_SUCCESS, if then changing iic bus state is I2C_
MSGSTAT_WRITE_BUSY；Otherwise, step (3) are directly entered.
(3) check whether iic bus state is I2C_MSGSTAT_INACTIVE, if so, judging that iic bus state is
No is I2C_MSGSTAT_SEND_NOSTOP；Otherwise, (1) is entered step, circulation read-write operation is re-started.
(4) if iic bus state is I2C_MSGSTAT_SEND_NOSTOP, data read operation is carried out.
When reading the data, as shown in figure 5, step 1: sending the start bit START first, sending from device address, processing
Ack, high-order byte address, processing Ack are sent, sends byte address low level, processing Ack, step 2: hair START, sending device
Address, processing Ack, the 1st byte data is received until completing processing Ack, last 1 byte data of reception, sending STOP stop position.
Fig. 6 gives interrupt function flow chart of the present invention, obtains interrupt source from the I2C module status register of DSP, and
Interrupt source is judged whether by SCD, the register stopping indicated detection interruption I2C_SCD_ISRC, if interrupt source is I2C_
SCD_ISRC, then by judging that I2C bus state and setting I2C bus state realize interruption process.In Fig. 6
PassCount indicates that the data read by IIC pass through the quantity of verification after verification, and I2C_NUMBYTES, which refers to, to be passed through
All data counts that I2C bus is read.If interrupt source is not I2C_SCD_ISRC, judge whether interrupt source is register
Access is ready to interrupt I2C_ARDY_ISR, if I2C bus then is arranged in the case where being 1 without response interrupt flag bit NACK
It generates stop position and removes NACK.If interrupt source is I2C_ARDY_ISR, if I2C bus is current in the case where NACK is not 1
State is I2C_MSGSTAT_SEND_NOSTOP_BUSY, then enables I2C bus current state for I2C_MSGSTAT_RESTART weight
Send out start bit state.
Due to the task queue model for having used event to trigger in major cycle, can be very good to reduce is needed in single cycle
The data read-write operation to be carried out accelerates program response speed.
The above-mentioned date storage method based on iic bus is written into data and passes a batch, write-in a batch, this incoming lot number
According to can just avoid from the initial address of write-in to the length of the last one address of current page and generate page when writing batch of data
The phenomenon that overturning, also avoids passing a problem of byte writes a byte low efficiency.
Claims (5)
1. a kind of date storage method based on iic bus, which is characterized in that steps are as follows:
Address is distributed to data to be written, the data to be written behind distribution address are pre-processed, and will be pretreated
Data are stored；If wherein preprocessing process includes: that total length of data to be written is greater than IIC peripheral hardware fifo queue in controller
Length, then be written into data according to the length of IIC peripheral hardware fifo queue and split into multiple queues；And it is every by a storage
The device Best-case Response Time period stores a queue, and in each queue data to be written address memory a page
In.
2. the date storage method according to claim 1 based on iic bus, which is characterized in that if further including to be written
Total length of data is then directly written into data according to the ground of distribution no more than the length of IIC peripheral hardware fifo queue in controller
Location is stored into the corresponding page of memory.
3. a kind of data-storage system based on iic bus, which is characterized in that including processor and memory, the processor
It is connected between memory by iic bus；The processor is used to distribute address to data to be written, behind distribution address
Data to be written pre-processed, and pretreated data are stored；If wherein preprocessing process includes: to be written
Total length of data is greater than the length of IIC peripheral hardware fifo queue in controller, then is written into data according to IIC peripheral hardware fifo queue
Length split into multiple queues；And every one memory Best-case Response Time period of process stores a queue, and each team
The address of data to be written is in a page of memory in column.
4. the data-storage system according to claim 3 based on iic bus, which is characterized in that the processor is also used
If in length of the total length of data to be written no more than IIC peripheral hardware fifo queue in controller, be directly written into data by
It stores according to the address of distribution into the corresponding page of memory.
5. the data-storage system according to claim 3 or 4 based on iic bus, which is characterized in that the memory is
EEPROM。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201810759187.1A CN109062843A (en) | 2018-07-11 | 2018-07-11 | A kind of date storage method and system based on iic bus |
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| CN201810759187.1A CN109062843A (en) | 2018-07-11 | 2018-07-11 | A kind of date storage method and system based on iic bus |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111179993A (en) * | 2019-12-31 | 2020-05-19 | 苏州绿控传动科技股份有限公司 | Data reading/writing method of EEPROM |
| CN112925659A (en) * | 2021-02-24 | 2021-06-08 | 深圳前海微众银行股份有限公司 | Message processing method, device, equipment and computer storage medium |
| CN113515910A (en) * | 2021-07-12 | 2021-10-19 | 合肥芯荣微电子有限公司 | AXI bus-based data preprocessing method |
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Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111179993A (en) * | 2019-12-31 | 2020-05-19 | 苏州绿控传动科技股份有限公司 | Data reading/writing method of EEPROM |
| CN112925659A (en) * | 2021-02-24 | 2021-06-08 | 深圳前海微众银行股份有限公司 | Message processing method, device, equipment and computer storage medium |
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