CN109039340A - A kind of multi-stage noise shaping modulator - Google Patents
A kind of multi-stage noise shaping modulator Download PDFInfo
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- CN109039340A CN109039340A CN201810614082.7A CN201810614082A CN109039340A CN 109039340 A CN109039340 A CN 109039340A CN 201810614082 A CN201810614082 A CN 201810614082A CN 109039340 A CN109039340 A CN 109039340A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
- H03M3/00—Conversion of analogue values to or from differential modulation
- H03M3/30—Delta-sigma modulation
- H03M3/39—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators
- H03M3/412—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution
- H03M3/414—Structural details of delta-sigma modulators, e.g. incremental delta-sigma modulators characterised by the number of quantisers and their type and resolution having multiple quantisers arranged in cascaded loops, each of the second and further loops processing the quantisation error of the loop preceding it, i.e. multiple stage noise shaping [MASH] type
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Abstract
The invention discloses a kind of multi-stage noise shaping modulators, including four nd order modulators, four full adders and three groups of register groups, wherein mainly two nd order modulators are connected in parallel to form first order quantizer, in any case, decimal input can be divided into two unequal odd number values to input from two nd order modulators in parallel, it is attained by the effect of output sequence period growth, wherein odd number input can lengthen the output sequence period.Meanwhile first order quantizer, using form in parallel, first order output is added to obtain by two quantizer output valves, it is equivalent to and joined shake, therefore the output sequence period of modulator can be further increased, inhibits the idle tone of output power spectrum density, to inhibit spuious.
Description
Technical field
The invention belongs to Sigma-Delta modulator fields, are specifically designed a kind of multi-stage noise shaping modulator.
Background technique
Sigma-Delta modulator is widely used in the fractional phase lock loop of RF communication system, traditional Sigma-
Delta modulator structure is mainly multi-stage noise reshaping structure (MASH structure), easily designed, is had good stability, but idle tone
Performance changes with input and is changed.In recent years, as the research to MASH modulator is goed deep into, improve the method for MASH modulator
It is referred in different papers, many researchs are devoted to by injection randomized jitter or by input control in odd ranges
It is interior, enhance the output sequence randomness of MASH modulator, the period increases, so as to improve idle tone performance.Wherein, injection is random
The mode of shake needs additionally to increase random signal generator and multirate digital filter, and the consumption of hardware greatly increases.It will be defeated
Enter control in odd ranges, does not increase hardware consumption and but limit the selection of frequency dividing ratio.
Summary of the invention
Goal of the invention: in view of the problems of the existing technology, the main purpose of the present invention is to provide one kind not by the present invention
The randomness that modulator output sequence can only be increased, reduces idle tone, to reduce spuious, and is avoided that hardware consumption
Excessive multi-stage noise shaping modulator.
Technical solution: to achieve the above object, the present invention provides a kind of multi-stage noise shaping modulators, including four one
Nd order modulator, four full adders and three groups of register groups, wherein the first input signal enters the input terminal of a nd order modulator M1,
Second input signal enters the input terminal of a nd order modulator M2, the first output end of a nd order modulator M1 and a nd order modulator M2's
First output end is connect with two input terminals of full adder FA3 respectively；The second output terminal and single order of one nd order modulator M1 is modulated
The second output terminal of device M2 is connect with two input terminals of full adder FA5 respectively；The output end of full adder FA3 and a nd order modulator
The input terminal of M3 connects, and the first output end of a nd order modulator M3 is connect with the input terminal of a nd order modulator M4, a nd order modulator
The connection that the second output terminal of M3 passes through the first input of the first register group and full adder FA6；One nd order modulator M4 first is defeated
The connection that outlet passes through the second input of the second register group and full adder FA6；The output end and full adder FA7 of full adder FA6
The output end of first input end connection, full adder FA5 is connect by third register group with the second input terminal of full adder FA7,
The output end of full adder FA7 is total output end.
Wherein, the full adder FA3 is 16 full adders, and full adder FA5, full adder FA6 and full adder FA7 are 9
Full adder.
Further, the nd order modulator M1 includes accumulator C1, register Reg1 and full adder FA1；First input letter
Number end is connect with the first input end of accumulator C1, the carry output of accumulator C1 respectively with the first input of full adder FA5
End is connected with the first input end of full adder FA1, and the summation output end of accumulator C1 is connect with the input terminal of register Reg1, tires out
The second input terminal of device C1 is added to connect with the output end of register Reg1；The second input terminal and register Reg1 of full adder FA1
Output end be connected, the output end of full adder FA1 is connect with the first input end of full adder FA3.
Further, the nd order modulator M2 includes accumulator C2, register Reg2 and full adder FA2；Second input letter
Number end is connect with the first input end of accumulator C2, the carry output of accumulator C2 respectively with the second input of full adder FA5
End is connected with the first input end of full adder FA2, and the summation output end of accumulator C2 is connect with the input terminal of register Reg2, tires out
The second input terminal of device C2 is added to connect with the output end of register Reg2；The second input terminal and register Reg2 of full adder FA2
Output end be connected, the output end of full adder FA2 is connect with the second input terminal of full adder FA3.
Further, the nd order modulator M3 includes accumulator C3, register Reg3 and full adder FA4；One nd order modulator M1
It is connect respectively with the input terminal of full adder FA3 with the output end of a nd order modulator M2, the output end and accumulator C3 of full adder FA3
First input end be connected；The carry output of accumulator C3 respectively with the first input end of full adder FA4 and the first register
The input terminal connection of group, the summation output end of accumulator C3 are connected by register Reg3 with the second input terminal of full adder FA4；
The second input terminal of accumulator C3 is connect with the output end of register Reg3；The output end of full adder FA4 and a nd order modulator M4
Input terminal connection.
Further, the nd order modulator M4 includes accumulator C4 and register Reg4；The output end of one nd order modulator M3 with
The first input end of accumulator C4 is connected；The summation output end of accumulator C4 is connected with the input terminal of register Reg4；Accumulator
The second input terminal of C4 is connected with the output end of register Reg4, and the carry output of accumulator C3 and the second register group connect
It connects.
Furthermore full adder FA1, full adder FA2 and full adder FA4 are 16 full adders.
Working principle: two nd order modulators are connected in parallel to form first order quantizer by the present invention, in any situation
Under, decimal input can be divided into two unequal odd number values and be inputted from two nd order modulators in parallel, is attained by
The effect that the output sequence period increases, wherein odd number input can lengthen the output sequence period.Meanwhile first order quantizer is adopted
With form in parallel, first order output is added to obtain, is equivalent to and joined shake by two quantizer output valves, therefore can be into
One step increases the output sequence period of modulator, inhibits the idle tone of output power spectrum density, to inhibit spuious.
The utility model has the advantages that compared with prior art, the invention has the following advantages that 1, realize and can make to adjust under any input
The maximization in device output sequence period processed is reduced spuious；2, the mode of the more traditional injection randomized jitter of hardware consumption obviously subtracts
It is few.
Detailed description of the invention
Fig. 1 is the schematic diagram of this hair；
Fig. 2 is hardware circuit principle figure of the invention；
Fig. 3 is 16bit assembly line carry look ahead accumulator；
Fig. 4 is output noise power spectrum density figure of the invention.
Specific embodiment
Further explanation is done to the present invention with reference to the accompanying drawing.
As shown in Figure 1, the present invention provides a kind of multi-stage noise shaping modulator, including four nd order modulators, four
Full adder and three groups of register groups, wherein the first input signal enter a nd order modulator M1 input terminal, the second input signal into
Enter the input terminal of a nd order modulator M2, the first output end difference of the first output end of a nd order modulator M1 and a nd order modulator M2
It is connect with two input terminals of full adder FA3；Second output of the second output terminal of one nd order modulator M1 and a nd order modulator M2
End is connect with two input terminals of full adder FA5 respectively；The input terminal of the output end of full adder FA3 and a nd order modulator M3 connect
It connects, the first output end of a nd order modulator M3 is connect with the input terminal of a nd order modulator M4, the second output of a nd order modulator M3
The connection that end passes through the first input of the first register group and full adder FA6；One the first output end of nd order modulator M4 passes through second
The connection of the second input of register group and full adder FA6；The output end and full adder FA7 first input end of full adder FA6 connects
It connects, the output end of full adder FA5 is connect by third register group with the second input terminal of full adder FA7, and full adder FA7's is defeated
Outlet is total output end.
As shown in Fig. 2, specific hardware circuit, including four 16bit assembly line carry look ahead accumulator C1~C4,15
A register Reg1~Reg15, four 16bit full adder FA1~FA4 and three 9bit full adder FA5~FA7.
Input X1 [n] connects the first input end of accumulator C1, and the carry output of accumulator C1 is respectively with full adder FA5's
First input end is connected with the first input end of full adder FA1, the input of the summation output end and register Reg1 of accumulator C1
End connection, the second input terminal of accumulator C1 are connect with the output end of register Reg1；Input X2 [n] connects the first of accumulator C2
Input terminal, the carry output of the accumulator C2 first input end with the second input terminal of full adder FA5 and full adder FA2 respectively
It is connected, the summation output end of accumulator C2 is connect with the input terminal of register Reg2, the second input terminal of accumulator C2 and deposit
The output end of device Reg2 connects；The second input terminal of full adder FA1 is connected with the output end of register Reg1, full adder FA1's
Output end is connected with full adder FA3 first input end；The output end phase of the second input terminal of full adder FA2 and register Reg2
Even, the output end of full adder FA2 is connected with the second input terminal of full adder FA3；The of the output end of full adder FA3 and accumulator C3
One input terminal is connected；The carry output of accumulator C3 is connected with the input terminal of register Reg8, the carry-out of accumulator C3
End is connected with the first input end of full adder FA4, and the summation output end of accumulator C3 is connected with the input terminal of register Reg3；Entirely
The output end of device FA4 and the first input end of accumulator C4 is added to be connected；The carry output of accumulator C4 is with register Reg10's
Input terminal is connected, and the summation output end of accumulator C4 is connected with the input terminal of register Reg4；The output end of full adder FA5 with post
The input terminal of storage Reg5 is connected, and the output end of register Reg5 is connected with the input terminal of register Reg6；Register Reg6's
Output end is connected with the input terminal of register Reg7；The output end of register Reg8 is connected with the input terminal of register Reg9；It posts
The output end of storage Reg10 is connected with the input terminal of register Reg13；The output end of register Reg9 is with register Reg12's
Input terminal is connected；The output end of register Reg7 is connected with the input terminal of register Reg11；The output end of register Reg13 with
The input terminal of register Reg14 is connected, and the output end of register Reg13 is connected with the first input end of full adder FA6；FA6's
Second input terminal is connected with the output end of Reg12, and the subtracting input of FA6 is connected with the output end of Reg4, and full adder FA6's is defeated
Outlet is connected with the first input end of full adder FA7, and the output end of full adder FA6 is connected with the input terminal of register Reg15；Entirely
The second input terminal of device FA7 is added to be connected with the output end of register Reg11, the subtracting input and register of full adder FA7
The output end of Reg15 is connected, total output port of the output end of full adder FA7 as modulator.
C1, FA1, Reg1 in Fig. 2 constitute the M1 in Fig. 1, and C2, FA2, Reg2 in Fig. 2 constitute the M2 in Fig. 1, in Fig. 2
C3, FA4, Reg3 constitute the M3 in Fig. 1, C4, Reg4 in Fig. 2 constitute the M4 in Fig. 1.Reg5~Reg13 is to y1[n]+y2
[n]、y3[n]、y4[n] is cached, and guarantees the synchronization of timing.Reg14, Reg15 complete in Fig. 1 (1-z jointly-1)、(1-z-1)2Function.
Four 16bit assembly line carry look ahead accumulators in Fig. 2 are as shown in figure 3, specifically include four 4bit full adders
CLA1~CLA4 and four register Reg16~Reg19.In Fig. 3, addend A, addend B and S are divided into A [n:n+k], B [n:n+
K], S [n:n+k], A [n:n+k], B [n:n+k], S [n:n+k] are expressed as the (n+1)th to the n-th+k of addend A, addend B and S
+ 1, wherein n >=0,15 >=n+k, n and k are integer.
A's [0:3] and B [0:3] is input to CLA1, and the summation of CLA1 exports the S [0:3], CLA1 of output as a whole
Carry output and Reg16 input terminal connect；A's [4:7] and B [4:7] is input to CLA2, and the summation of CLA2 exports conduct
The carry output of the S [4:7] integrally inputted, CLA2 and the input terminal of Reg17 connect；A [8:11] and B [8:11's] is input to
The S [8:11] that the summation output of CLA3, CLA3 input as a whole, the carry output of CLA3 and the input terminal of Reg18 connect；
A's [12:15] and B [12:15] is input to CLA4, the S [12:1] that the summation output of CLA4 inputs as a whole, the carry of CLA4
The connection of the input terminal of output end and Reg19；The output end of Reg16 is connected with the carry input of CLA2；The output end of Reg17 with
The carry input of CLA3 is connected；The output end of Reg18 is connected with the carry input of CLA4；The output end of Reg19 is as whole
The carry-out of a 16bit assembly line carry look ahead accumulator；Always signal CLK is input to the clock signal of Reg16~Reg19
Input terminal, reset signal RST are input to the reset signal input terminal of Reg16~Reg19.
Fig. 4 is a kind of output noise power spectrum density figure of input adjusting type multi-stage noise shaping modulator of the invention.
As seen from Figure 4, the idle tone of output noise power spectrum density of the invention has been substantially reduced.
The above is only a preferred embodiment of the present invention, it should be pointed out that: for the ordinary skill people of the art
For member, various improvements and modifications may be made without departing from the principle of the present invention, these improvements and modifications are also answered
It is considered as protection scope of the present invention.
Claims (7)
1. a kind of multi-stage noise shaping modulator, it is characterised in that: posted including four nd order modulators, four full adders and three groups
Storage group, wherein the first input signal enters the input terminal of a nd order modulator M1, and the second input signal enters a nd order modulator M2
Input terminal, the first output end of the first output end of a nd order modulator M1 and a nd order modulator M2 are respectively with full adder FA3's
Two input terminal connections；The second output terminal of the second output terminal of one nd order modulator M1 and a nd order modulator M2 respectively with full adder
Two input terminals of FA5 connect；The output end of full adder FA3 is connect with the input terminal of a nd order modulator M3, a nd order modulator M3
The first output end connect with the input terminal of a nd order modulator M4, the second output terminal of a nd order modulator M3 passes through the first register
The connection of group and the first input of full adder FA6；One the first output end of nd order modulator M4 passes through the second register group and full adder
The connection of the second input of FA6；The output end of full adder FA6 is connect with full adder FA7 first input end, and full adder FA5's is defeated
Outlet is connect by third register group with the second input terminal of full adder FA7, and the output end of full adder FA7 is total output end.
2. multi-stage noise shaping modulator according to claim 1, it is characterised in that: the full adder FA3 is 16 complete
Add device, full adder FA5, full adder FA6 and full adder FA7 are 9 full adders.
3. multi-stage noise shaping modulator according to claim 1, it is characterised in that: the nd order modulator M1 includes tired
Add device C1, register Reg1 and full adder FA1；First input signal end is connect with the first input end of accumulator C1, accumulator
The carry output of C1 is connected with the first input end of the first input end of full adder FA5 and full adder FA1 respectively, accumulator C1
Summation output end connect with the input terminal of register Reg1, the output end of the second input terminal of accumulator C1 and register Reg1
Connection；The second input terminal of full adder FA1 is connected with the output end of register Reg1, the output end and full adder of full adder FA1
The first input end of FA3 connects.
4. multi-stage noise shaping modulator according to claim 1, it is characterised in that: the nd order modulator M2 includes tired
Add device C2, register Reg2 and full adder FA2；Second input signal end is connect with the first input end of accumulator C2, accumulator
The carry output of C2 is connected with the first input end of the second input terminal of full adder FA5 and full adder FA2 respectively, accumulator C2
Summation output end connect with the input terminal of register Reg2, the output end of the second input terminal of accumulator C2 and register Reg2
Connection；The second input terminal of full adder FA2 is connected with the output end of register Reg2, the output end and full adder of full adder FA2
The second input terminal of FA3 connects.
5. multi-stage noise shaping modulator according to claim 1, it is characterised in that: the nd order modulator M3 includes cumulative
Device C3, register Reg3 and full adder FA4；The output end of one nd order modulator M1 and a nd order modulator M2 respectively with full adder FA3
Input terminal connection, the output end of full adder FA3 is connected with the first input end of accumulator C3；The carry output of accumulator C3
It is connect respectively with the input terminal of the first input end of full adder FA4 and the first register group, the summation output end of accumulator C3 is logical
Register Reg3 is crossed to be connected with the second input terminal of full adder FA4；The second input terminal of accumulator C3 is defeated with register Reg3's
Outlet connection；The output end of full adder FA4 is connect with the input terminal of a nd order modulator M4.
6. multi-stage noise shaping modulator according to claim 1, it is characterised in that: the nd order modulator M4 includes cumulative
Device C4 and register Reg4；The output end of one nd order modulator M3 is connected with the first input end of accumulator C4；Accumulator C4's asks
It is connected with output end with the input terminal of register Reg4；The output end phase of the second input terminal of accumulator C4 and register Reg4
Even, the carry output of accumulator C3 is connect with the second register group.
7. the multi-stage noise shaping modulator according to any one of claim 2~5, it is characterised in that: full adder
FA1, full adder FA2 and full adder FA4 are 16 full adders.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5396248A (en) * | 1992-02-29 | 1995-03-07 | Sony Corporation | Noise shaping circuit |
| US20020145472A1 (en) * | 2000-10-10 | 2002-10-10 | Lee-Sang Oh | Single-bit sigma-delta modulated fractional-N frequency synthesizer |
| CN101473540A (en) * | 2006-06-13 | 2009-07-01 | 丰田自动车株式会社 | A/D converter and A/D converting method |
| CN102959869A (en) * | 2011-06-08 | 2013-03-06 | 旭化成微电子株式会社 | Variable modulus modulator for fractional-n frequency synthesizers |
| CN106656102A (en) * | 2016-12-14 | 2017-05-10 | 东南大学 | Method for adding external disturbance signal of multilevel noise shaping digital Delta-Sigma modulators |
-
2018
- 2018-06-14 CN CN201810614082.7A patent/CN109039340B/en active Active
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5396248A (en) * | 1992-02-29 | 1995-03-07 | Sony Corporation | Noise shaping circuit |
| US20020145472A1 (en) * | 2000-10-10 | 2002-10-10 | Lee-Sang Oh | Single-bit sigma-delta modulated fractional-N frequency synthesizer |
| CN101473540A (en) * | 2006-06-13 | 2009-07-01 | 丰田自动车株式会社 | A/D converter and A/D converting method |
| CN102959869A (en) * | 2011-06-08 | 2013-03-06 | 旭化成微电子株式会社 | Variable modulus modulator for fractional-n frequency synthesizers |
| CN106656102A (en) * | 2016-12-14 | 2017-05-10 | 东南大学 | Method for adding external disturbance signal of multilevel noise shaping digital Delta-Sigma modulators |
Non-Patent Citations (3)
| Title |
|---|
| MA,HONG-WEI等: "Harmonic Distortion Analysis of Switched-Capacitor Based Second-Order Sigma-Delta Modulator induced by Operational Amplifier"s Limited Slew Rate", 《IEEE ADVANCED INFORMATION TECHNOLOGY, ELECTRONIC AND AUTOMATION CONTROL CONFERENCE》 * |
| 张文通: "基于调制技术的小数分频器设计", 《中国优秀硕士学位论文全文数据库信息科技辑》 * |
| 汤黎明等: "四阶连续时间正交带通ΣΔ调制器的设计", 《电子器件》 * |
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