CN109039303A - A kind of method, apparatus and system generating pulse voltage signal - Google Patents
A kind of method, apparatus and system generating pulse voltage signal Download PDFInfo
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- CN109039303A CN109039303A CN201710438355.2A CN201710438355A CN109039303A CN 109039303 A CN109039303 A CN 109039303A CN 201710438355 A CN201710438355 A CN 201710438355A CN 109039303 A CN109039303 A CN 109039303A
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
- H03K3/01—Details
- H03K3/011—Modifications of generator to compensate for variations in physical values, e.g. voltage, temperature
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K4/00—Generating pulses having essentially a finite slope or stepped portions
- H03K4/02—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform
- H03K4/026—Generating pulses having essentially a finite slope or stepped portions having stepped portions, e.g. staircase waveform using digital techniques
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Abstract
This application discloses a kind of method, apparatus and system for generating pulse voltage signal, for generating the pulse voltage signal of high quality, this method comprises: obtaining n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, the integer that the value of i is 0 to n-1；N kind pulse voltage increment △ V is generated according to n kind pulse voltagei, wherein △ Vi=(Vi‑V0)÷2；According to the value m of amplitude selection signal in pulse voltage increment △ ViMiddle selection coded pulse voltage increment △ V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer；Pulse voltage, which is generated, according to coded pulse voltage increment △ V encodes Cj, wherein the integer that the value of j is 0 to n-1；C is encoded according to clock signal circulation voltage pulse outputjTo pulse voltage signal generative circuit to generate pulse voltage signal.
Description
Technical field
This application involves electronic technology fields, and in particular to a kind of method, apparatus and system for generating pulse voltage signal.
Background technique
Pulse voltage refers generally to the of short duration mutation of voltage or electric current, generates high-speed pulse voltage signal in the prior art
Mode is usually the pulse voltage letter for being outputed signal to by programmable logic device and being made of amplifier or power amplification circuit etc.
Number generative circuit is to generate high-speed pulse voltage signal.But the output signal of programmable logic device is if it is energy unevenness
When the signal of weighing apparatus, the fluctuation for inputing to the signal of amplifier or power amplification circuit there are DC component will cause, make direct current point
Amount by amplifier or power amplification circuit, can not cause the high-speed pulse voltage signal distortion of output, signal quality to be deteriorated, nothing
Method meets the requirement of design.
Summary of the invention
In view of this, the application provides a kind of method, apparatus and system for generating pulse voltage signal, to solve existing skill
In art can not outputting high quality high-speed pulse voltage signal the technical issues of.
To solve the above problems, technical solution provided by the embodiments of the present application is as follows:
A method of generating pulse voltage signal, which comprises
Obtain n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, the integer that the value of i is 0 to n-1；
N kind pulse voltage increment △ V is generated according to the n kind pulse voltagei, wherein △ Vi=(Vi-V0)÷2；
According to the value m of amplitude selection signal in the pulse voltage increment △ ViMiddle selection coded pulse voltage increment △
V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer；
Pulse voltage, which is generated, according to the coded pulse voltage increment △ V encodes Cj, wherein the value of j is 0 to n-1's
Integer；
The pulse voltage, which is exported, according to clock signal circulation encodes CjTo pulse voltage signal generative circuit to generate arteries and veins
Rush voltage signal.
Correspondingly, the value m of the amplitude selection signal is remained unchanged, alternatively, the value m of the amplitude selection signal exists
Variation is primary at random after the period of every n clock signal.
Correspondingly, variation is primary at random after the value m of the amplitude selection signal is in the period of every n clock signal
When, one in integer that the value of m is 0 to n-1, alternatively, one in the integer that the value of m is 1 to n-1.
Correspondingly, described generate pulse voltage coding C according to the coded pulse voltage increment △ Vj, wherein the value of j
For 0 to n-1 integer, comprising:
According to coded pulse voltage increment △ V, the value of first function f (x) and the value of second function f (y)
It generates pulse voltage and encodes Cj, wherein Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) be 1 or-
The integer that the value that the value of 1, second function f (y) are 1 or -1, j is 0 to n-1.
Correspondingly, the pulse voltage signal generative circuit includes high-speed A/D converter and high-speed power amplification electricity
Road；Alternatively, the pulse voltage signal generative circuit includes multi-path low speed digital analog converter, multi-path low speed amplifier, multichannel mould
Quasi- switching circuit and single channel high-speed power amplifying circuit.
A kind of device generating pulse voltage signal, described device include:
Acquiring unit, for obtaining n kind pulse voltage Vi, wherein n is integer more than or equal to 1, the value of i be 0 to
The integer of n-1；
First generation unit, for generating n kind pulse voltage increment △ V according to the n kind pulse voltagei, wherein △ Vi
=(Vi-V0)÷2；
Selecting unit, for the value m according to amplitude selection signal in the pulse voltage increment △ ViMiddle selection coding
Pulse voltage increment △ V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer；
Second generation unit encodes C for generating pulse voltage according to the coded pulse voltage increment △ Vj, wherein j
Value be 0 to n-1 integer；
Output unit encodes C for exporting the pulse voltage according to clock signal circulationjIt is generated to pulse voltage signal
Circuit is to generate pulse voltage signal.
Correspondingly, the value m of the amplitude selection signal is remained unchanged, alternatively, the value m of the amplitude selection signal exists
Variation is primary at random after the period of every n clock signal.
Correspondingly, variation is primary at random after the value m of the amplitude selection signal is in the period of every n clock signal
When, one in integer that the value of m is 0 to n-1, alternatively, one in the integer that the value of m is 1 to n-1.
Correspondingly, second generation unit is specifically used for:
According to coded pulse voltage increment △ V, the value of first function f (x) and the value of second function f (y)
It generates pulse voltage and encodes Cj, wherein Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) be 1 or-
The integer that the value that the value of 1, second function f (y) are 1 or -1, j is 0 to n-1.
A kind of system generating pulse voltage signal, the system comprises:
Programmable logic device and pulse voltage signal generative circuit；
The programmable logic device is the device of above-mentioned generation pulse voltage signal；
The pulse voltage signal generative circuit includes high-speed A/D converter and high-speed power amplifying circuit；Alternatively,
The pulse voltage signal generative circuit includes multi-path low speed digital analog converter, multi-path low speed amplifier, multiway analog switch electricity
Road and single channel high-speed power amplifying circuit.
It can be seen that the embodiment of the present application has the following beneficial effects:
The embodiment of the present application obtains required n kind pulse voltage by programmable logic device, generates n kind pulse voltage and increases
Amount generates pulse voltage coding output to pulse voltage signal according to the value strobe pulse voltage increment of amplitude selection signal
Generative circuit is to generate pulse voltage signal, by joining in the variation of amplitude selection signal value and generation pulse voltage coding
Several variations can control the frequency, amplitude and waveform shape of pulse voltage signal generated, to pass through pulse electricity
The periodic signal that the signal or amplitude of pressure coding output amplitude balancing energy symmetrical above and below are certain is believed to pulse voltage
Number generative circuit, making to input to the signal of pulse voltage signal generative circuit, there is no DC component fluctuations, to generate high-quality
The high-speed pulse voltage signal of amount.
Detailed description of the invention
Fig. 1 is the schematic diagram for generating pulse voltage signal result in the prior art；
Fig. 2 is the schematic diagram that pulse voltage signal result is generated in the embodiment of the present application；
Fig. 3 is the schematic diagram that pulse voltage signal result is generated in the embodiment of the present application；
Fig. 4 is the flow chart of the embodiment of the method for the generation pulse voltage signal provided in the embodiment of the present application；
Fig. 5 is the timing diagram of programmable logic device output signal in the embodiment of the present application；
Fig. 6 is the schematic diagram of pulse voltage signal generative circuit in the embodiment of the present application；
Fig. 7 is the schematic diagram of pulse voltage signal generative circuit in the embodiment of the present application；
Fig. 8 is that the exemplary timing diagram of pulse voltage signal one is generated in the embodiment of the present application；
Fig. 9 is that another exemplary timing diagram of pulse voltage signal is generated in the embodiment of the present application；
Figure 10 is that another exemplary timing diagram of pulse voltage signal is generated in the embodiment of the present application；
Figure 11 is that another exemplary timing diagram of pulse voltage signal is generated in the embodiment of the present application；
Figure 12 is that another exemplary timing diagram of pulse voltage signal is generated in the embodiment of the present application；
Figure 13 is the schematic diagram of a scenario that pulse voltage signal is generated in the embodiment of the present application；
Figure 14 is the schematic diagram of pulse voltage signal generated in the embodiment of the present application application scenarios；
Figure 15 is the schematic diagram of the Installation practice of the generation pulse voltage signal provided in the embodiment of the present application；
Figure 16 is the schematic diagram of the system embodiment of the generation pulse voltage signal provided in the embodiment of the present application.
Specific embodiment
In order to make the above objects, features, and advantages of the present application more apparent, with reference to the accompanying drawing and it is specific real
Mode is applied to be described in further detail the embodiment of the present application.
The mode for generating high-speed pulse voltage signal in the prior art is usually by programmable logic device, such as FPGA
(Field-Programmable Gate Array, field programmable gate array) is outputed signal to by digital analog converter, amplification
The pulse voltage signal generative circuit of the compositions such as device or power amplification circuit is to generate high-speed pulse voltage signal.It is patrolled when programmable
When the output signal of volume device is amplitude certain cyclical signal, can with the high-speed pulse voltage signal of outputting high quality, but
It is, when the output signal of programmable logic device signal unbalanced for energy, to input to amplifier or power amplification circuit
Signal there are the fluctuation of DC component, make DC component that can not lead to the height of output by amplifier or power amplification circuit
Fast pulse voltage signal distortion, signal quality are deteriorated, and are unable to satisfy the requirement of design.It is shown in Figure 1, programmable logic device
Output signal be amplitude be gradually increased signal when, there are distortion phenomenons for the high-speed pulse voltage signal of output.
The embodiment of the present application provides a kind of method, apparatus and system for generating pulse voltage signal thus, according to amplifier
Work characteristics, using programmable logic device to output to pulse voltage signal generative circuit signal carry out coded treatment,
So that the recurrent pulses voltage signal that the amplitude for generating high quality is certain, shown in Figure 2；Or generate the random of high quality
Pulse voltage signal, the random pulses voltage signal magnitude is symmetrical above and below, balancing energy, makes to input to pulse voltage signal generation
The signal of circuit is shown in Figure 3 there is no DC component fluctuation.
It is shown in Figure 4, the embodiment of the method for the generation pulse voltage signal provided in the embodiment of the present application is provided, it can
To be applied to programmable logic device, the present embodiment be may comprise steps of:
Step 401: obtaining n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, and the value of i is 0 to n-1's
Integer.
Firstly, obtaining n kind pulse voltage V according to actual needsi, due to the value of i be 0 to n-1 integer, then ViIt can be with
Including V0、V1、……、Vn-1, wherein V0It can indicate the reference voltage of the pulse voltage signal of output.
Step 402: n kind pulse voltage increment △ V is generated according to n kind pulse voltagei, wherein △ Vi=(Vi-V0)÷2。
N kind pulse voltage increment △ V is generated according to n kind pulse voltagei, △ ViIt may include △ V0、△V1、……、△
Vn-1, △ Vi=(Vi-V0) ÷ 2, i.e. △ V0=0, △ V1=(V1-V0)÷2、……、△Vn-1=(Vn-1-V0)÷2.Pulse voltage
Increment △ ViIt can represent relative to reference voltage V0Amplitude absolute value, such as pulse voltage V1Relative to reference voltage V0
Amplitude be (V1-V0) ÷ 2 and-(V1-V0) ÷ 2, in another example V0=0, V1=6, then V1Relative to V0Amplitude be 3 and -3, V0
=2, V1=8, then V1Relative to V0Amplitude be 3 and -3, i.e. V1Amplitude relative to 0 is 5 and -1.
Step 403: according to the value m of amplitude selection signal in pulse voltage increment △ ViMiddle selection coded pulse voltage increases
Measure △ V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer.
Amplitude selection signal can be used to select used pulse voltage increment △ Vi, the value m of amplitude selection signal
It can be chosen in 0 to n-1 integer, the value m of amplitude selection signal can be remained unchanged, and can also be believed in every n clock
Number period after at random variation it is primary, in random variation, can change in 0 to n-1 integer, can also not include 0
1 to n-1 integer in change.Then in pulse voltage increment △ ViIn can choose coded pulse voltage increment △ V, △ V=
△VmIf m changes, △ V also follows variation, for example, m value is 1, then △ V=△ V1, the variation of m value is 2, then △ V=
△V2。
Step 404: pulse voltage being generated according to coded pulse voltage increment △ V and encodes Cj, wherein the value of j is 0 to n-
1 integer.
Pulse voltage coding C can be generated according to coded pulse voltage increment △ Vj, pulse voltage coding CjMay include
C0、C1、……、Cn-1。
In some possible implementations of the embodiment of the present application, the specific implementation of step 404 may include: according to coding
The value of pulse voltage increment △ V, the value of first function f (x) and second function f (y) generate pulse voltage and encode Cj,
In, Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) are 1 or -1, the value of second function f (y)
The integer that value for 1 or -1, j is 0 to n-1.
Wherein, the value of f (x) and f (y) are mutually indepedent, can according to the waveform of the pulse voltage signal to be generated into
Row value.Each pulse voltage encodes CjWhen calculating f (x), f (y) value can be different, such as calculate C1When f (x)=- 1,
F (y)=1 calculates C2When f (x)=1, f (y)=1 etc..
Step 405: encoding C according to clock signal circulation voltage pulse outputjTo pulse voltage signal generative circuit with life
At pulse voltage signal.
A pulse voltage, which is exported, according to clock signal each clock cycle encodes Cj, to recycle voltage pulse output volume
Code CjPulse voltage signal generative circuit is given, it is shown in Figure 5, show the output signal of programmable logic device.
In some possible implementations of the embodiment of the present application, shown in Figure 6, pulse voltage signal generative circuit can
To include high-speed A/D converter and high-speed power amplifying circuit；Pulse voltage is provided by programmable logic device such as FPGA
It encodes and gives high-speed A/D converter DAC, after high-speed power amplifying circuit, export high-speed pulse voltage signal.Alternatively, ginseng
As shown in Figure 7, pulse voltage signal generative circuit may include multi-path low speed digital analog converter, multi-path low speed amplifier, multichannel
Analog switching circuit and single channel high-speed power amplifying circuit.Pulse voltage coding is provided by programmable logic device such as FPGA
Multi-path low speed DAC is given, by multi-path low speed single-channel amplifier, multi-channel analog switch circuit, single channel high-speed power amplifying circuit
Later, high-speed pulse voltage signal is exported.
According to it is provided by the embodiments of the present application generate pulse voltage signal method, control amplitude selection signal value,
The value of change frequency and first function f (x), the value of second function f (y), it can control voltage pulse output signal
Frequency, amplitude and waveform shape, be illustrated respectively below according to example.
It is shown in Figure 8, n=4, the value m=1 of amplitude selection signal are defined, then △ V=△ V1=(V1-V0) ÷ 2, C0
=V0+ (- 1) * (1+1) ÷ 2* △ V=V0-(V1-V0) ÷ 2, i.e. f (x)=- 1, f (y)=1, C1=V0+(1)*(1+1)÷2*△
V=V0+(V1-V0) ÷ 2, i.e. f (x)=1, f (y)=1, C2=V0、C3=V0, i.e. f (y)=- 1.It then can be with output phase for V0On
The equal recurrent pulses voltage signal of lower amplitude.
It is shown in Figure 9, n=3, the value m=1 of amplitude selection signal are defined, then △ V=△ V1=(V1-V0) ÷ 2, C0
=V0+ (1) * (1+1) ÷ 2* △ V=V0+(V1-V0) ÷ 2, i.e. f (x)=1, f (y)=1, another C1=V0、C2=V0, i.e. f (y)=-
1.High level-low level-low level circulation recurrent pulses voltage signal can then be exported.
It is shown in Figure 10, n=3, the value m=1 of amplitude selection signal are defined, then △ V=△ V1=(V1-V0) ÷ 2,
C0=V0, i.e. f (y)=- 1, C1=V0+ (1) * (1+1) ÷ 2* △ V=V0+(V1-V0) ÷ 2, i.e. f (x)=1, f (y)=1, C2=
V0+ (1) * (1+1) ÷ 2* △ V=V0+(V1-V0) ÷ 2, i.e. f (x)=1, f (y)=1.Low level-high level-can then be exported
The recurrent pulses voltage signal of high level circulation.
In the examples described above, the value m of amplitude selection signal is remained unchanged, then can export recurrent pulses voltage letter
Number.In the embodiment of the present application, the value m of amplitude selection signal can also change at random after the period of every n clock signal
Once, m can change in 1 to n-1 integer, can also change in 0 to n-1 integer.
It is shown in Figure 11, n=4 is defined, the value m of amplitude selection signal changes at random in 1,2,3, then △ V=△
Vm, C0=V0+ (1) * (1+1) ÷ 2* △ V, i.e. f (x)=1, f (y)=1, C1=V0+ (- 1) * (1+1) ÷ 2* △ V, i.e. f (x)=-
1, f (y)=1, C2=V0、C3=V0, i.e. f (y)=- 1.It can then be fixed with output frequency, the pulse voltage signal that amplitude is random,
The random pulses voltage signal magnitude is symmetrical above and below, balancing energy, makes to input to the signal of pulse voltage signal generative circuit not
There are DC component fluctuations.
It is shown in Figure 12, n=4 is defined, the value m of amplitude selection signal changes at random in 0,1,2,3, then △ V=
△Vm, C0=V0+ (- 1) * (1+1) ÷ 2* △ V, i.e. f (x)=- 1, f (y)=1, C1=V0+ (1) * (1+1) ÷ 2* △ V, i.e. f (x)
=1, f (y)=1, C2=V0、C3=V0, i.e. f (y)=- 1.When m=0 only exports V0, then can with output frequency random, amplitude also with
The pulse voltage signal of machine, the random pulses voltage signal magnitude is symmetrical above and below, balancing energy, makes to input to pulse voltage signal
There is no DC component fluctuations for the signal of generative circuit.
In this way, the embodiment of the present application obtains required n kind pulse voltage by programmable logic device, the pulse of n kind is generated
Voltage increment generates the output of pulse voltage coding and gives pulse electricity according to the value strobe pulse voltage increment of amplitude selection signal
It presses signal generating circuit to generate pulse voltage signal, is compiled by the variation and generation pulse voltage of amplitude selection signal value
The variation of parameter can control the frequency, amplitude and waveform shape of pulse voltage signal generated in code, to pass through
Pulse voltage encodes the periodic signal of the signal or amplitude of output amplitude balancing energy symmetrical above and below centainly to pulse
Voltage signal generative circuit, making to input to the signal of pulse voltage signal generative circuit, there is no DC component fluctuations, thus raw
At the high-speed pulse voltage signal of high quality.
The high-speed pulse voltage generated in the embodiment of the present application can be used for phase code QKD (Quantum Key
Distribution, quantum key distribution) light phase modulation in system optical-electric module, n is defined in this application equal to 4.
It is shown in Figure 13, the BB84 phase code QKD system of the standard double unequal arm M-Z interferometer side external using phase-modulator
Case, wherein BB84 is a kind of quantum key distribution agreement in quantum communications field.It is shown in Figure 14, phase tune is reached in photon
When device processed, pulse voltage signal is loaded on phase-modulator, so that it may change the phase of photon.Firstly, sender MZa and connecing
Two interferometer of debit MZb all has the arm length difference Δ of a 400mm.Light pulse is after sender's unequal arm M-Z interferometer, shape
Enter the quantum channel of optical fiber link composition at one in front and one in back two light pulses, single photon pulses are dry in sender's unequal arm M-Z
It may be considered random selection at interferometer and walk a laggard applying aspect modulator of paths La or Sa.The external requirement of phase-modulator produces
Raw high-speed pulse voltage signal is to light pulse phase modulation, therefore the pulse voltage signal generated has following requirement: 1, relative magnitude reaches
To 8V, and rising time (0%~100%) and failing edge time (100%~0%) are less than 1.5ns；2, waveform stabilization,
Functional, signal jitter is less than 300ps.It then selects to carry out the light pulse on long-armed phase-modulation, therefore by the steady of generation
Determine on the modulator that high-speed pulse modulation voltage is loaded on long-armed.Single photon pulses are long in launch party's unequal arm M-Z interferometer
Be phase-modulated device on arm and modulated a relative phase φ, wherein φ be four quantum states 0, pi/2, π or 3 π in BB84 agreement/
Random one in 2 phases.Throughput subchannel transmission after light pulse is modulated has been modulated one relatively after reaching recipient again
Phase Φ, Φ are then in BB84 agreement random one in two measurement bases 0 or pi/2 phase.Reach recipient's unequal arm M-Z interference
When instrument, single photon pulses randomly choose paths a Lb or Sb again.Single photon pulses pass through two unequal arm M-Z interferometers
Afterwards, four kinds of path states are formed altogether: | Sa+Sb >, | Sa+Lb >, | La+Sb > with | La+Lb >.Wherein path is walked " launch party is long-armed+it connects
The two-way light pulse of debit's galianconism " and " launch party's galianconism+recipient long-armed " is superimposed, is entering recipient's single-photon detector
It is interfered at BS before D0 and D1.
In addition, it is shown in Figure 15, a kind of device implementation generating pulse voltage signal is also provided in the embodiment of the present application
, may include:
Acquiring unit 1501, for obtaining n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, the value of i
For 0 to n-1 integer.
First generation unit 1502, for generating n kind pulse voltage increment △ V according to n kind pulse voltagei, wherein △ Vi
=(Vi-V0)÷2。
Selecting unit 1503, for the value m according to amplitude selection signal in pulse voltage increment △ ViMiddle selection coding
Pulse voltage increment △ V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer.
Second generation unit 1504 encodes C for generating pulse voltage according to coded pulse voltage increment △ Vj, wherein j
Value be 0 to n-1 integer.
In some possible implementations of the embodiment of the present application, the second generation unit can be specifically used for:
It is generated according to the value of coded pulse voltage increment △ V, the value of first function f (x) and second function f (y)
Pulse voltage encodes Cj, wherein Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) are 1 or -1, the
The integer that the value that the value of two function f (y) is 1 or -1, j is 0 to n-1.
Output unit 1505, for encoding C according to clock signal circulation voltage pulse outputjIt is generated to pulse voltage signal
Circuit is to generate pulse voltage signal.
In some possible implementations of the embodiment of the present application, the value m of amplitude selection signal is remained unchanged, alternatively,
Variation is primary at random after the period of every n clock signal by the value m of amplitude selection signal.
In some possible implementations of the embodiment of the present application, when the value m of amplitude selection signal believes in every n clock
Number period after when changing one time at random, one in integer that the value of m is 0 to n-1, alternatively, the value of m is 1 to n-1's
One in integer.
It is shown in Figure 16, a kind of system embodiment generating pulse voltage signal is also provided in the embodiment of the present application, it can
To include: programmable logic device 1601 and pulse voltage signal generative circuit 1602.
Programmable logic device can be the Installation practice of above-mentioned generation pulse voltage signal.
Pulse voltage signal generative circuit may include high-speed A/D converter and high-speed power amplifying circuit；Alternatively,
Pulse voltage signal generative circuit may include multi-path low speed digital analog converter, multi-path low speed amplifier, multiway analog switch electricity
Road and single channel high-speed power amplifying circuit.
In this way, the embodiment of the present application obtains required n kind pulse voltage by programmable logic device, the pulse of n kind is generated
Voltage increment generates the output of pulse voltage coding and gives pulse electricity according to the value strobe pulse voltage increment of amplitude selection signal
It presses signal generating circuit to generate pulse voltage signal, is compiled by the variation and generation pulse voltage of amplitude selection signal value
The variation of parameter can control the frequency, amplitude and waveform shape of pulse voltage signal generated in code, to pass through
Pulse voltage encodes the periodic signal of the signal or amplitude of output amplitude balancing energy symmetrical above and below centainly to pulse
Voltage signal generative circuit, making to input to the signal of pulse voltage signal generative circuit, there is no DC component fluctuations, thus raw
At the high-speed pulse voltage signal of high quality.
It should be noted that each embodiment in this specification is described in a progressive manner, each embodiment emphasis is said
Bright is the difference from other embodiments, and the same or similar parts in each embodiment may refer to each other.For reality
For applying system or device disclosed in example, since it is corresponded to the methods disclosed in the examples, so being described relatively simple, phase
Place is closed referring to method part illustration.
It should also be noted that, herein, relational terms such as first and second and the like are used merely to one
Entity or operation are distinguished with another entity or operation, without necessarily requiring or implying between these entities or operation
There are any actual relationship or orders.Moreover, the terms "include", "comprise" or its any other variant are intended to contain
Lid non-exclusive inclusion, so that the process, method, article or equipment including a series of elements is not only wanted including those
Element, but also including other elements that are not explicitly listed, or further include for this process, method, article or equipment
Intrinsic element.In the absence of more restrictions, the element limited by sentence "including a ...", it is not excluded that
There is also other identical elements in process, method, article or equipment including the element.
The step of method described in conjunction with the examples disclosed in this document or algorithm, can directly be held with hardware, processor
The combination of capable software module or the two is implemented.Software module can be placed in random access memory (RAM), memory, read-only deposit
Reservoir (ROM), electrically programmable ROM, electrically erasable ROM, register, hard disk, moveable magnetic disc, CD-ROM or technology
In any other form of storage medium well known in field.
The foregoing description of the disclosed embodiments makes professional and technical personnel in the field can be realized or use the application.
Various modifications to these embodiments will be readily apparent to those skilled in the art, as defined herein
General Principle can be realized in other embodiments without departing from the spirit or scope of the application.Therefore, the application
It is not intended to be limited to the embodiments shown herein, and is to fit to and the principles and novel features disclosed herein phase one
The widest scope of cause.
Claims (10)
1. a kind of method for generating pulse voltage signal, which is characterized in that the described method includes:
Obtain n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, the integer that the value of i is 0 to n-1；
N kind pulse voltage increment △ V is generated according to the n kind pulse voltagei, wherein △ Vi=(Vi-V0)÷2；
According to the value m of amplitude selection signal in the pulse voltage increment △ ViMiddle selection coded pulse voltage increment △ V,
In, △ V=△ Vm, the value of m is one in 0 to n-1 integer；
Pulse voltage, which is generated, according to the coded pulse voltage increment △ V encodes Cj, wherein the integer that the value of j is 0 to n-1；
The pulse voltage, which is exported, according to clock signal circulation encodes CjTo pulse voltage signal generative circuit to generate pulse voltage
Signal.
2. the method according to claim 1, wherein the value m of the amplitude selection signal is remained unchanged, or
Person, variation is primary at random after the period of every n clock signal by the value m of the amplitude selection signal.
3. according to the method described in claim 2, it is characterized in that, when the value m of the amplitude selection signal is in every n clock
When changing at random after the period of signal one time, one in integer that the value of m is 0 to n-1, alternatively, the value of m is 1 to n-1
Integer in one.
4. the method according to claim 1, wherein described generate according to the coded pulse voltage increment △ V
Pulse voltage encodes Cj, wherein the integer that the value of j is 0 to n-1, comprising:
It is generated according to the value of coded pulse voltage increment △ V, the value of first function f (x) and second function f (y)
Pulse voltage encodes Cj, wherein Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) are 1 or -1, the
The integer that the value that the value of two function f (y) is 1 or -1, j is 0 to n-1.
5. method as claimed in any of claims 1 to 4, which is characterized in that the pulse voltage signal generates electricity
Road includes high-speed A/D converter and high-speed power amplifying circuit；Alternatively, the pulse voltage signal generative circuit includes more
Road low speed digital analog converter, multi-path low speed amplifier, multi-channel analog switch circuit and single channel high-speed power amplifying circuit.
6. a kind of device for generating pulse voltage signal, which is characterized in that described device includes:
Acquiring unit, for obtaining n kind pulse voltage Vi, wherein n is the integer more than or equal to 1, and the value of i is 0 to n-1's
Integer；
First generation unit, for generating n kind pulse voltage increment △ V according to the n kind pulse voltagei, wherein △ Vi=
(Vi-V0)÷2；
Selecting unit, for the value m according to amplitude selection signal in the pulse voltage increment △ ViMiddle selection coded pulse electricity
Press increment △ V, wherein △ V=△ Vm, the value of m is one in 0 to n-1 integer；
Second generation unit encodes C for generating pulse voltage according to the coded pulse voltage increment △ Vj, wherein j's takes
The integer that value is 0 to n-1；
Output unit encodes C for exporting the pulse voltage according to clock signal circulationjGive pulse voltage signal generative circuit
To generate pulse voltage signal.
7. device according to claim 6, which is characterized in that the value m of the amplitude selection signal is remained unchanged, or
Person, variation is primary at random after the period of every n clock signal by the value m of the amplitude selection signal.
8. device according to claim 7, which is characterized in that when the value m of the amplitude selection signal is in every n clock
When changing at random after the period of signal one time, one in integer that the value of m is 0 to n-1, alternatively, the value of m is 1 to n-1
Integer in one.
9. according to device described in claim 6 to 8 any one, which is characterized in that second generation unit is specifically used for:
It is generated according to the value of coded pulse voltage increment △ V, the value of first function f (x) and second function f (y)
Pulse voltage encodes Cj, wherein Cj=V0The value of+f (x) * (1+f (y)) ÷ 2* △ V, first function f (x) are 1 or -1, the
The integer that the value that the value of two function f (y) is 1 or -1, j is 0 to n-1.
10. a kind of system for generating pulse voltage signal, which is characterized in that the system comprises:
Programmable logic device and pulse voltage signal generative circuit；
The programmable logic device is the device that pulse voltage signal is generated described in claim 6 to 9 any one；
The pulse voltage signal generative circuit includes high-speed A/D converter and high-speed power amplifying circuit；Alternatively, described
Pulse voltage signal generative circuit include multi-path low speed digital analog converter, multi-path low speed amplifier, multi-channel analog switch circuit with
And single channel high-speed power amplifying circuit.
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Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1038478A (en) * | 1975-04-28 | 1978-09-12 | Herbert N. Klingbeil | Control system having incremental "bang-bang" fine control |
| CN87106615A (en) * | 1986-09-29 | 1988-06-22 | 希格纳特罗恩公司 | Signal source distortion compensator |
| JP2000346924A (en) * | 1999-06-02 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Gps receiver |
| CN1593010A (en) * | 2001-10-31 | 2005-03-09 | 飞思卡尔半导体公司 | Incremental-delta analogue-to-digital conversion |
| JP2006080879A (en) * | 2004-09-09 | 2006-03-23 | Japan Science & Technology Agency | Composite noise generator |
| CN103606373A (en) * | 2013-11-28 | 2014-02-26 | 小米科技有限责任公司 | Method and device for audio restoration and terminal device |
| CN104349732A (en) * | 2012-04-09 | 2015-02-11 | 伊西康内外科公司 | Serial communication protocol for medical device |
-
2017
- 2017-06-12 CN CN201710438355.2A patent/CN109039303B/en active Active
Patent Citations (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA1038478A (en) * | 1975-04-28 | 1978-09-12 | Herbert N. Klingbeil | Control system having incremental "bang-bang" fine control |
| CN87106615A (en) * | 1986-09-29 | 1988-06-22 | 希格纳特罗恩公司 | Signal source distortion compensator |
| JP2000346924A (en) * | 1999-06-02 | 2000-12-15 | Matsushita Electric Ind Co Ltd | Gps receiver |
| CN1593010A (en) * | 2001-10-31 | 2005-03-09 | 飞思卡尔半导体公司 | Incremental-delta analogue-to-digital conversion |
| JP2006080879A (en) * | 2004-09-09 | 2006-03-23 | Japan Science & Technology Agency | Composite noise generator |
| CN104349732A (en) * | 2012-04-09 | 2015-02-11 | 伊西康内外科公司 | Serial communication protocol for medical device |
| CN103606373A (en) * | 2013-11-28 | 2014-02-26 | 小米科技有限责任公司 | Method and device for audio restoration and terminal device |
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