CN109038752B - Active equalization method for battery pack - Google Patents
Active equalization method for battery pack Download PDFInfo
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- CN109038752B CN109038752B CN201810965014.5A CN201810965014A CN109038752B CN 109038752 B CN109038752 B CN 109038752B CN 201810965014 A CN201810965014 A CN 201810965014A CN 109038752 B CN109038752 B CN 109038752B
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02J—CIRCUIT ARRANGEMENTS OR SYSTEMS FOR SUPPLYING OR DISTRIBUTING ELECTRIC POWER; SYSTEMS FOR STORING ELECTRIC ENERGY
- H02J7/00—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries
- H02J7/0013—Circuit arrangements for charging or depolarising batteries or for supplying loads from batteries acting upon several batteries simultaneously or sequentially
- H02J7/0014—Circuits for equalisation of charge between batteries
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01M—PROCESSES OR MEANS, e.g. BATTERIES, FOR THE DIRECT CONVERSION OF CHEMICAL ENERGY INTO ELECTRICAL ENERGY
- H01M10/00—Secondary cells; Manufacture thereof
- H01M10/42—Methods or arrangements for servicing or maintenance of secondary cells or secondary half-cells
- H01M10/44—Methods for charging or discharging
- H01M10/441—Methods for charging or discharging for several batteries or cells simultaneously or sequentially
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
- Y02E60/00—Enabling technologies; Technologies with a potential or indirect contribution to GHG emissions mitigation
- Y02E60/10—Energy storage using batteries
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- Chemical & Material Sciences (AREA)
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- General Chemical & Material Sciences (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The embodiment of the invention provides an active equalization method for a battery pack, and belongs to the technical field of equalization of batteries. The active equalization method comprises the following steps: obtaining a relation curve of voltage and residual capacity of the single battery of the battery pack at different temperatures through experiments; respectively detecting the temperature and the voltage of each single battery; performing compensation calculation according to the temperature and the voltage, and determining the equivalent voltage of each single battery; judging whether the battery pack needs to be balanced or not according to each equivalent voltage; balancing the single battery with the lowest equivalent voltage under the condition that the battery pack needs to be started for balancing; after balancing for a period of time, detecting the voltage of each single battery again, judging the balancing condition, and stopping the active balancing method under the condition of not starting balancing.
Description
Technical Field
The invention relates to the technical field of battery equalization, in particular to an active equalization method for a battery pack.
Background
The battery pack is one of indispensable components of modern various electrical appliances. In the production process of the single batteries, the conditions such as equipment are limited, so that various parameters of each single battery are kept completely consistent. Therefore, after the battery pack is used for many times, the voltages of the individual cells often deviate from each other. Therefore, in order to improve the efficiency of energy utilization and ensure the safety of the battery pack, the battery pack is often balanced during the use of the battery pack.
The prior art includes two methods for balancing the battery pack: one is passive equalization, also called lossy equalization, the equalization mode is simple to realize and low in cost, but the discharge current is small, the equalization time is long, and the problems of energy loss, heat dissipation and the like can be caused; the other mode is active equalization and lossless equalization, and the equalization mode has high energy utilization rate and short equalization time, but has higher cost and is relatively difficult to realize.
Disclosure of Invention
An object of an embodiment of the present invention is to provide an active equalization method for a battery pack, which performs compensation operation on voltages of single batteries by addressing a problem of non-uniform temperature of the battery pack, thereby improving equalization efficiency of the battery pack.
In order to achieve the above object, an embodiment of the present invention provides an active equalization method for a battery pack, including:
obtaining a relation curve of voltage and residual capacity of the single battery of the battery pack at different temperatures through experiments;
respectively detecting the temperature and the voltage of each single battery;
performing compensation calculation according to the temperature and the voltage, and determining the equivalent voltage of each single battery;
judging whether the battery pack needs to be balanced or not according to each equivalent voltage;
balancing the single battery with the lowest equivalent voltage under the condition that the battery pack needs to be started for balancing;
after balancing for a period of time, detecting the voltage of each single battery again, judging the balancing condition, and stopping the active balancing method under the condition of not starting balancing.
Optionally, the active balancing method further comprises:
presetting an active equalization circuit for a battery pack, the active equalization circuit comprising:
the temperature acquisition unit is used for acquiring the temperature of each single battery of the battery pack;
the voltage acquisition unit is used for acquiring the voltage of the single battery of the battery pack;
the balancing unit is used for carrying out balancing operation on the battery pack;
a first end of the channel selection unit is connected with the voltage acquisition unit, a second end of the channel selection unit is connected with the equalization unit, and a third end of the channel selection unit is connected with the battery pack;
the processing unit is respectively connected with the temperature acquisition unit, the voltage acquisition unit, the equalization unit and the channel selection unit and is used for:
respectively acquiring the temperature of each single battery of the battery pack through the temperature acquisition unit;
controlling the channel selection unit to connect the voltage acquisition unit to two ends of each single battery respectively so as to acquire the voltage of each single battery;
performing compensation calculation according to the temperature and the voltage, and determining the equivalent voltage of each single battery;
judging whether the battery pack needs to be balanced or not according to each equivalent voltage;
under the condition that the battery pack needs to be balanced, controlling the channel selection unit to disconnect the voltage acquisition unit from the battery pack, and controlling the channel selection unit to connect the balancing unit to the single battery with the lowest equivalent voltage in the battery pack so as to balance the single batteries;
after balancing for a period of time, detecting each single voltage again and judging the balancing condition, and stopping active balancing when balancing does not need to be started.
Optionally, the voltage acquisition unit includes:
one end of the voltage acquisition module is connected with the processing unit;
the device comprises a collecting switch, wherein one end of the collecting switch is connected with the other end of a voltage collecting module, the other end of the collecting switch is connected with the first end of a channel selecting unit, and the control end of the collecting switch is connected with a processing unit.
The voltage acquisition module includes:
one end of the first resistor and the other end of the first resistor are respectively connected with the anode and the cathode of the single battery;
one end of the second resistor is connected with one end of the first resistor;
one end of the third resistor is connected with the other end of the first resistor;
the negative electrode of the power supply end of the first operational amplifier is grounded;
the anode of the first diode is connected with the inverting input end of the first operational amplifier, and the cathode of the first diode is connected with the non-inverting input end of the first operational amplifier;
the anode of the second diode is connected with the positive-phase input end of the first operational amplifier, and the cathode of the second diode is connected with the negative-phase input end of the first operational amplifier;
the fourth resistor is connected between the inverting input end of the first operational amplifier and the output end of the first operational amplifier;
the fifth resistor is connected between the positive-phase input end of the first operational amplifier and the negative electrode of the power supply end of the first operational amplifier;
one end of the first inductor is used for being externally connected with a +5V direct-current power supply, and the other end of the first inductor is connected with the anode of the power supply end of the first operational amplifier;
the other end of the first inductor is grounded through the first capacitor and the second capacitor respectively;
and the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier, the non-inverting input end of the second operational amplifier is connected with the output end of the first operational amplifier, and the output end of the second operational amplifier is connected with the processing unit.
Optionally, the equalizing unit includes:
a boost module;
the voltage boosting module is connected with the transformer voltage reduction module;
and one end of the equalizing switch is connected with the other end of the transformer voltage reduction module, and the other end of the equalizing switch is connected with the second end of the channel selection unit.
Optionally, the boost module comprises:
one end of the sixth resistor is externally connected with a +12V direct-current power supply;
one end of the seventh resistor is connected with the other end of the sixth resistor, and the other end of the seventh resistor is grounded;
one end of the second inductor is connected with one end of the sixth resistor;
the anode of the third diode is connected with the other end of the second inductor, and the cathode of the third diode is connected with the transformer step-down module;
the first pin and the sixth pin of the boost chip are grounded, and the seventh pin of the boost chip is connected with a node between the sixth resistor and the seventh resistor;
one end of the eighth resistor is connected with a ninth pin of the boost chip;
one end of the third capacitor is connected with the other end of the eighth resistor, and the other end of the third capacitor is connected with a tenth pin of the boost chip;
one end of the ninth resistor is connected with the eighth pin of the boost chip;
one end of the fourth capacitor is connected with the other end of the ninth resistor, and the other end of the fourth capacitor is connected with a sixth pin of the boost chip;
one end of the tenth resistor is connected with a sixth pin of the boost chip;
one end of the eleventh resistor is connected with the other end of the ninth resistor, and the other end of the eleventh resistor is connected with the other end of the tenth resistor;
a gate of the first field effect transistor is connected with a fifth pin of the boost chip, a source of the first field effect transistor is connected with the other end of the tenth resistor, and a drain of the first field effect transistor is connected with a node between the second inductor and the third diode;
one end of the fifth capacitor is connected with the fourth pin of the boost chip, and the other end of the fifth capacitor is grounded;
the sixth capacitor is connected between the second pin and the third pin of the boost chip;
one end of the twelfth resistor is connected with the first pin of the boost chip, and the other end of the twelfth resistor is connected with one end of the second inductor;
one end of the thirteenth resistor is connected with a third pin of the boosting chip;
one end of the seventh capacitor is connected with the other end of the thirteenth resistor, and the other end of the seventh capacitor is connected with the second pin of the boost chip;
one end of the fourteenth resistor is connected with the cathode of the third diode, and the other end of the fourteenth resistor is connected with the second pin of the boost chip;
a fifteenth resistor, one end of which is connected with the other end of the fourteenth resistor, and the other end of which is grounded;
optionally, the transformer step-down unit includes:
a first pin of the transformer is connected with the boosting module, a fifth pin of the transformer is grounded, and a tenth pin of the transformer is used for being connected with the negative electrode of the single battery;
the drain electrode of the second field effect transistor is connected with the third pin of the transformer;
one end of the sixteenth resistor is connected with the source electrode of the second field effect transistor, and the other end of the sixteenth resistor is grounded;
the first pin of the high-frequency switch chip is suspended, and the fifth pin of the high-frequency switch chip is grounded;
one end of the seventeenth resistor is connected with a sixth pin of the high-frequency switch chip, and the other end of the seventeenth resistor is connected with one end of the sixteenth resistor;
one end of the eighteenth resistor is connected with the seventh pin of the high-frequency switch chip, and the other end of the eighteenth resistor is connected with the grid electrode of the second field-effect tube;
a nineteenth resistor connected between the fourth pin of the high-frequency switch chip and a ground terminal;
one end of the twentieth resistor is connected with the first pin of the transformer, and the other end of the twentieth resistor is connected with the third pin of the high-frequency switch chip;
one end of the twenty-first resistor is connected with the first pin of the transformer, and the other end of the twenty-first resistor is connected with the eighth pin of the high-frequency switch chip;
one end of the twenty-second resistor is connected with the fourth pin of the transformer, and the other end of the twenty-second resistor is connected with the second pin of the high-frequency switch chip;
one end of the twenty-third resistor is connected with the other end of the twenty-second resistor, and the other end of the twenty-third resistor is grounded;
a fourth pin of the first optical coupler is connected with a fourth pin of the high-frequency switch chip, a second pin of the first optical coupler is connected with the processing unit, and a third pin of the first optical coupler is grounded;
one end of the twenty-fourth resistor is connected with the first pin of the first optocoupler, and the other end of the twenty-fourth resistor is externally connected with a +5V direct-current power supply;
one end of the twenty-fifth resistor is connected with the second pin of the first optocoupler;
one end of the fourth diode is connected with a third pin of the transformer;
the anode of the fifth diode is connected with the other end of the fourth diode, and the cathode of the fifth diode is connected with the first pin of the transformer;
the anode of the sixth diode is connected with the fourth pin of the transformer, and the cathode of the sixth diode is connected with the eighth pin of the high-frequency switch chip;
the anode of the seventh diode is connected with the eighth pin of the transformer;
the anode of the eighth diode is grounded, and the cathode of the eighth diode is connected with the eighth pin of the high-frequency switch chip;
a ninth diode, an anode of which is connected to the other end of the twenty-fifth resistor, and a cathode of which is grounded;
one end of the eighth capacitor is connected with the sixth pin of the high-frequency switch chip, and the other end of the eighth capacitor is grounded;
one end of the ninth capacitor is connected with the third pin of the high-frequency switch chip, and the other end of the ninth capacitor is grounded;
one end of the tenth capacitor is connected with the eighth pin of the high-frequency switch chip, and the other end of the tenth capacitor is grounded;
one end of the eleventh capacitor is connected with the second pin of the high-frequency switch chip, and the other end of the eleventh capacitor is grounded;
a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor, wherein a cathode of the seventh diode is connected to a tenth pin of the transformer through the twelfth capacitor, the thirteenth capacitor and the fourteenth capacitor, respectively;
a first pin of the current sensor chip is connected with a negative electrode of the seventh diode, a second pin of the current sensor chip is connected with the first pin of the current sensor chip, a third pin of the current sensor chip is connected with a fourth pin of the current sensor chip, the third pin of the current sensor chip is used for being connected with a positive electrode of the single battery, a fifth pin of the current sensor chip is grounded, and an eighth pin of the current sensor chip is used for being externally connected with a +5V direct current power supply;
one end of the fifteenth capacitor is connected with a sixth pin of the current sensor chip, and the other end of the fifteenth capacitor is connected with a fifth pin of the current sensor chip;
one end of the sixteenth capacitor is connected with the processing unit, and the other end of the sixteenth capacitor is grounded;
one end of the twenty-sixth resistor is connected with the processing unit, and the other end of the twenty-sixth resistor is connected with a seventh pin of the current sensor chip.
Optionally, the channel selection unit includes:
a first end of the channel selection module is connected with the other end of the balancing unit, and a second end of the channel selection module is connected with the other end of the voltage acquisition unit;
and one end of the relay switch is connected with the third end of the channel selection module, and the other end of the relay switch is connected with the battery pack.
Optionally, the processing unit includes a microprocessor, and the channel selection module includes:
a plurality of logic shift registers, wherein an eighth pin of each logic shift register is grounded, a tenth pin of each logic shift register is connected with an MR port of the microprocessor, an eleventh pin of each logic shift register is connected with an SHCP port of the microprocessor, a twelfth pin of each logic shift register is connected with an STCP port of the microprocessor, a thirteenth pin of each logic shift register is connected with an OE port of the microprocessor, the logic shift register connected with the microprocessor is connected with a DS port of the microprocessor through a fourteenth pin of the logic shift register, and a fourteenth pin of the logic shift register connected between two logic shift registers is connected with a ninth pin of the previous logic shift register;
the relay switch includes:
a plurality of second opto-couplers, every the first pin of second opto-coupler passes through the external + 5V's of twenty-seventh resistance DC power supply, the second pin of second opto-coupler is used for passing through the control command that processing unit was received to the passageway selection module, the third pin of second opto-coupler with the single battery's of group battery one end is connected, the fourth pin of second opto-coupler is used for selecting the module through the passageway and is connected with the other end of gathering switch and balanced switch.
Optionally, the processing unit includes a microprocessor, and the channel selection module includes:
a plurality of logic shift registers, wherein an eighth pin of each logic shift register is grounded, a tenth pin of each logic shift register is connected with an MR port of the microprocessor, an eleventh pin of each logic shift register is connected with an SHCP port of the microprocessor, a twelfth pin of each logic shift register is connected with an STCP port of the microprocessor, a thirteenth pin of each logic shift register is connected with an OE port of the microprocessor, the logic shift register connected between the microprocessor and the logic shift register is connected with a DS port of the microprocessor through a fourteenth pin of the logic shift register, and a fourteenth pin of the logic shift register connected between two logic shift registers is connected with a ninth pin of the last logic shift register;
the relay switch includes: the optical coupler comprises at least one third optical coupler and at least one fourth optical coupler, wherein the third optical coupler corresponds to the fourth optical coupler one by one;
a second pin of each third optocoupler is used for receiving a control instruction of the processing unit through the channel selection module, a third pin of each third optocoupler is connected with one end of one single battery, and a fourth pin of each third optocoupler is used for being connected with the other ends of the acquisition switch and the balance switch through the channel selection module;
every the external + 5V's of first pin of fourth opto-coupler through the eighteen resistance of second direct current power supply, every the second pin of fourth opto-coupler with correspond the first pin of third opto-coupler is connected, every the third pin of fourth opto-coupler is connected with this a battery cell's the other end, every the fourth pin of fourth opto-coupler is used for passing through the passageway select module with gather the switch with the other end of equalizing switch is connected.
Optionally, the temperature acquisition unit comprises:
the plurality of thermistors are respectively arranged on the single batteries, and one end of each thermistor is grounded;
one end of each twenty-ninth resistor is externally connected with a +4.096V reference voltage, and the other end of each twenty-ninth resistor is connected with the other end of the thermistor;
a plurality of input ends of the analog channel multiplexer are respectively connected to a node between each twenty-ninth resistor and the thermistor, the positive electrode of a power supply pin of the analog channel multiplexer is used for being externally connected with a +5V direct-current power supply, the negative electrode of the power supply pin of the analog channel multiplexer is grounded, a VEE pin of the analog channel multiplexer is connected with the negative electrode of the power supply pin of the analog channel multiplexer, and an enable pin, a ninth pin, a tenth pin and an eleventh pin of the analog channel multiplexer are connected with the processing unit;
a positive-phase input end of the third operational amplifier is connected with an output pin of the analog channel multiplexer, and a negative-phase input end of the third operational amplifier is connected with an output end of the third operational amplifier;
and the output end of the third operational amplifier is connected with the processing unit through the thirtieth resistor.
Through the technical scheme, the active equalization method for the battery pack provided by the invention can perform temperature compensation calculation on the detection value when detecting the monomer voltage of the battery pack by aiming at the characteristic that the temperature of the battery pack is not uneven, so that the accurate detection on the monomer voltage of the battery pack is realized, and the battery pack is actively equalized according to the calculated equivalent voltage, so that the reasonability of selection of the equalized battery pack is improved, and the equalization efficiency of the battery pack is improved.
Additional features and advantages of embodiments of the invention will be set forth in the detailed description which follows.
Drawings
The accompanying drawings, which are included to provide a further understanding of the embodiments of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the embodiments of the invention without limiting the embodiments of the invention. In the drawings:
fig. 1 is a flowchart of an active balancing method for a battery pack according to an embodiment of the present invention;
FIG. 2 is a graph of voltage versus SOC of a unit cell under different temperature conditions, according to an embodiment of the present invention;
fig. 3 is a block diagram of an active equalization circuit for a battery pack according to an embodiment of the present invention;
fig. 4 is a block diagram of an active equalization circuit for a battery pack according to an embodiment of the present invention;
FIG. 5 is a schematic structural diagram of a voltage acquisition module according to one embodiment of the present invention;
FIG. 6 is a block diagram of a boost module according to an embodiment of the present invention;
FIG. 7 is a schematic diagram of a transformer step-down module according to an embodiment of the present invention;
FIG. 8 is a schematic structural diagram of a channel selection module according to one embodiment of the present invention;
FIG. 9 is a schematic diagram of a relay switch according to an embodiment of the present invention;
FIG. 10 is a schematic diagram of a relay switch according to an embodiment of the present invention;
fig. 11 is a schematic structural view of a temperature collection unit according to an embodiment of the present invention.
Detailed Description
The following detailed description of embodiments of the invention refers to the accompanying drawings. It should be understood that the detailed description and specific examples, while indicating embodiments of the invention, are given by way of illustration and explanation only, not limitation.
Fig. 1 is a flowchart illustrating an active balancing method for a battery pack according to an embodiment of the present invention. In fig. 1, the active equalization method may include:
in step S10, the relationship between the voltage and the remaining capacity (SOC) of the battery pack at different temperatures is obtained through experiments. In an example of the present invention, taking a single battery as an example, the voltage of the single battery is plotted against the remaining capacity at different temperatures (0 ℃, 10 ℃, 20 ℃, 30 ℃, 40 ℃ and 50 ℃) as shown in fig. 2. In fig. 2, the voltages of the unit cells of the same SOC value are different at different temperatures, and thus it can be determined that the voltages of the unit cells vary with the temperature.
In step S11, the temperature and voltage of each unit cell of the battery pack are detected, respectively.
In step S12, compensation calculation is performed based on the temperature and voltage of the cell, and the equivalent voltage of each cell is determined. In one example of the present invention, the compensation calculation according to the temperature and the voltage of the single battery may be performed by determining the equivalent voltage of the single battery at 20 ℃ according to the relation curve in fig. 2; preferably, the equivalent voltage may be calculated according to equation (1):
wherein, U20℃Is the equivalent voltage, U, of a single cell at 20 DEG CTIs the voltage of the unit cell at the temperature T,
is the compensation quantity required for the battery voltage equivalent to 20 ℃ voltage at T temperature, and the compensation quantity is related to the battery type and can be determined according to the battery type.
In step S13, it is determined from each equivalent voltage whether the battery pack needs to be start-equalized. In an example of the present invention, a threshold value for indicating whether active equalization needs to be started may be preset, for example, and the active equalization is started when it is determined that a difference between a maximum value and a minimum value of an equivalent voltage of the battery pack is greater than the threshold value; and not starting the active equalization under the condition that the difference value is judged to be less than or equal to the threshold value. In one example of the present invention, the maximum value and the minimum value may be determined by, for example, calculating a difference between the maximum value and the minimum value by arranging the equivalent voltages of the unit cells from small to large using a bubble sorting method.
In step S14, when it is determined that the battery pack needs to be equalized by starting, the cells having the lowest equivalent voltage are equalized.
After the equalization for a while, step S11 is executed again.
In one embodiment of the present invention, the active equalization method may further include presetting an active equalization circuit for the battery pack. As shown in fig. 3, the active equalization circuit may include a processing unit 10, a channel selection unit 20, an equalization unit 30, a voltage acquisition unit 40, and a temperature acquisition unit 50.
The temperature collecting unit 50 may be used to collect the temperature of each unit cell of the battery B.
The voltage collecting unit 40 may be used to collect the voltages of the unit cells of the battery B.
The equalizing unit 30 may be used to perform an equalizing operation on the battery B.
The first end of the channel selection unit 20 is connected with the voltage acquisition unit 40, the second end of the channel selection unit 20 is connected with the equalization unit 30, and the third end of the channel selection unit 20 is connected with the battery B.
The processing unit 10 may be connected to the temperature acquisition unit 50, the voltage acquisition unit 40, the equalization unit 30, and the channel selection unit 20, respectively, and configured to:
respectively acquiring the temperature of each single battery of the battery pack B through a temperature acquisition unit 50;
the control channel selection unit 20 connects the voltage acquisition units 40 to both ends of each unit cell respectively to acquire the voltage of each unit cell;
performing compensation calculation according to the temperature and the voltage, and determining the equivalent voltage of each single battery;
judging whether the battery pack B needs to be started for balancing or not according to the voltage of each single body;
under the condition that the battery pack B needs to be started for balancing, the control channel selection unit 20 disconnects the voltage acquisition unit 40 from the battery pack B, and the control channel selection unit 20 connects the balancing unit 30 to the single battery with the lowest equivalent voltage in the battery pack B so as to balance the single batteries;
and after the single battery with the lowest equivalent voltage is balanced for a period of time, detecting the single voltage of the battery pack B again and judging the balancing condition, and stopping active balancing when balancing does not need to be started. In this embodiment, the determination of the length of the period of time may be determined according to a standard voltage of the battery B, a material. In the present embodiment, the period of time may be 100ms, taking the battery B as a lithium battery and the standard voltage as 3.6V as an example.
In one embodiment of the present invention, as shown in fig. 4, the voltage collecting unit 40 may include a voltage collecting module 41 and a collecting switch 42.
One end of the voltage acquisition module 41 may be connected with the processing unit 10. One end of the collecting switch 42 may be connected to the other end of the voltage collecting module 41, the other end of the collecting switch 42 is connected to the first end of the channel selecting unit 20, and the control end of the collecting switch 42 is connected to the processing unit 10.
Preferably, the voltage acquisition module 41 may include a circuit as shown in fig. 5. In fig. 5, the voltage acquisition module 41 may include:
one end and the other end of the first resistor R1 are respectively connected with the anode and the cathode of the single battery;
one end of a second resistor R2 is connected with one end of a first resistor R1;
one end of a third resistor R3 is connected with the other end of the first resistor R1;
a first operational amplifier U1, wherein the inverting input terminal of the first operational amplifier U1 is connected with the other end of the second resistor R2, the non-inverting input terminal of the first operational amplifier U1 is connected with the other end of the third resistor R3, and the negative electrode of the power supply terminal of the first operational amplifier U1 is grounded (+5V GND);
a first diode D1, wherein the anode of the first diode D1 is connected with the inverting input end of the first operational amplifier U1, and the cathode of the first diode D1 is connected with the non-inverting input end of the first operational amplifier U1;
the anode of the second diode D2 is connected with the non-inverting input end of the first operational amplifier U1, and the cathode of the second diode D2 is connected with the inverting input end of the first operational amplifier U1;
the fourth resistor R4 is connected between the inverting input end of the first operational amplifier U1 and the output end of the first operational amplifier U1;
the fifth resistor R5 is connected between the non-inverting input end of the first operational amplifier U1 and the negative electrode of the power supply end of the first operational amplifier U1;
one end of a first inductor L1, one end of a first inductor L1 is used for being externally connected with a +5V direct-current power supply, and the other end of the first inductor L1 is connected with the anode of the power supply end of the first operational amplifier U1;
the other end of the first inductor L1 is grounded (+5V GND) through a first capacitor C1 and a second capacitor C2 respectively by a first capacitor C1 and a second capacitor C2, wherein the second capacitor C2 is a polar capacitor, the anode of the second capacitor C2 is connected to the other end of the first inductor L1, the cathode of the second capacitor C2 is grounded, and the first capacitor C1 is a non-polar capacitor;
and an inverting input end of the second operational amplifier U2 is connected with an output end of the second operational amplifier U2, a non-inverting input end of the second operational amplifier U2 is connected with an output end of the first operational amplifier U1, and an output end of the second operational amplifier U2 is connected with the processing unit 10. In the case of a microcontroller as processing unit 10, the output of the second op-amp U2 may be connected to the AD VBat pin of the microprocessor.
In one embodiment of the present invention, as shown in fig. 4, the equalizing unit 30 may include: a boost module 31, a transformer buck module 32 and an equalization switch 33. One end of the transformer step-down module 32 may be connected to the step-up module 31; one end of the equalization switch 33 is connected to the other end of the transformer step-down module 32, and the other end of the equalization switch 33 is connected to the second end of the channel selection unit 20.
In one embodiment of the present invention, as shown in fig. 6, the boosting module 31 may include:
one end of a sixth resistor R6 and one end of a sixth resistor R6 are externally connected with a +12V direct-current power supply;
one end of the seventh resistor R7 is connected with the other end of the sixth resistor R6, and the other end of the seventh resistor R7 is grounded;
one end of a second inductor L2 is connected with one end of a sixth resistor R6;
a third diode D3, wherein the anode of the third diode D3 is connected to the other end of the second inductor L2, and the cathode of the third diode D3 is connected to the transformer step-down module 32 (e.g., PBL + port in the figure);
the boost chip U3 is characterized in that a first pin (VIN) and a sixth pin (GND) of the boost chip U3 are grounded, and a seventh pin (UVLO) of the boost chip U3 is connected with a node between a sixth resistor R6 and a seventh resistor R7;
one end of an eighth resistor R8, one end of the eighth resistor R8 is connected with a ninth pin (RT) of the boosting chip U3;
one end of a third capacitor C3, one end of a third capacitor C3 is connected with the other end of the eighth resistor R8, and the other end of the third capacitor C3 is connected with a tenth pin (SS) of the boost chip U3;
one end of a ninth resistor R9, wherein the ninth resistor R9 is connected with an eighth pin (CS) of the boosting chip U3;
one end of a fourth capacitor C4, one end of a fourth capacitor C4 is connected with the other end of the ninth resistor R9, and the other end of the fourth capacitor C4 is connected with a sixth pin (GND) of the boost chip U3;
a tenth resistor R10, one end of the tenth resistor R10 being connected to the sixth pin (GND) of the boost chip U3;
an eleventh resistor R11, one end of the eleventh resistor R11 being connected to the other end of the ninth resistor R9, the other end of the eleventh resistor R11 being connected to the other end of the tenth resistor R10;
a gate of the first field effect transistor Q1 is connected with a fifth pin (OUT) of the boost chip U3, a source of the first field effect transistor Q1 is connected with the other end of the tenth resistor R10, and a drain of the first field effect transistor Q1 is connected with a node between the second inductor L2 and the third diode D3;
one end of a fifth capacitor C5, one end of a fifth capacitor C5 is connected with a fourth pin (VCC) of the boost chip U3, and the other end of the fifth capacitor C5 is grounded;
a sixth capacitor C6, the sixth capacitor C6 is connected between the second pin (FB) and the third pin (COMP) of the boost chip U3;
one end of a twelfth resistor R12, one end of the twelfth resistor R12 is connected with a first pin (VIN) of the boosting chip U3, and the other end of the twelfth resistor R12 is connected with one end of a second inductor L2;
one end of a thirteenth resistor R13, wherein one end of the thirteenth resistor R13 is connected with a third pin (COMP) of the boosting chip U3;
one end of a seventh capacitor C7, one end of a seventh capacitor C7 is connected with the other end of the thirteenth resistor R13, and the other end of the seventh capacitor C7 is connected with a second pin (FB) of the boost chip U3;
one end of a fourteenth resistor R14, one end of the fourteenth resistor R14 is connected with the cathode of the third diode D3, and the other end of the fourteenth resistor R14 is connected with the second pin (FB) of the boost chip U3;
one end of a fifteenth resistor R15, one end of a fifteenth resistor R15 and the other end of a fourteenth resistor R14 are connected, and the other end of the fifteenth resistor R15 is grounded.
In one embodiment of the present invention, as shown in fig. 7, the transformer step-down module 32 may include:
a transformer T1, wherein a first pin of the transformer T1 is connected with the boost module 31(PBL +), a fifth pin of the transformer T1 is grounded, and a tenth pin of the transformer T1 is used for being connected with the cathode (BIJ-) of the single battery;
the drain electrode of the second field effect transistor Q2 and the drain electrode of the second field effect transistor Q2 are connected with the third pin of the transformer T1;
one end of a sixteenth resistor R16, one end of a sixteenth resistor R16 is connected with the source electrode of the second field effect transistor Q2, and the other end of the sixteenth resistor R16 is grounded;
the high-frequency switch chip U4 is characterized in that a first pin (NC) of the high-frequency switch chip U4 is suspended, and a fifth pin (GND) of the high-frequency switch chip U4 is grounded;
one end of a seventeenth resistor R17, wherein one end of the seventeenth resistor R17 is connected with a sixth pin (Isense) of the high-frequency switch chip U4, and the other end of the seventeenth resistor R17 is connected with one end of a sixteenth resistor R16;
one end of an eighteenth resistor R18, one end of an eighteenth resistor R18 is connected with a seventh pin (OUTPUT) of the high-frequency switch chip U4, and the other end of the eighteenth resistor R18 is connected with the gate of the second field-effect transistor Q2;
a nineteenth resistor R19 and a nineteenth resistor R19 are connected between the fourth pin (SD) of the high-frequency switch chip U4 and the ground terminal;
one end of a twentieth resistor R20 and one end of a twentieth resistor R20 are connected with a first pin (Vin) of the transformer T1, and the other end of the twentieth resistor R20 is connected with a third pin (Vin) of the high-frequency switch chip U4;
one end of a twenty-first resistor R21, one end of a twenty-first resistor R21 is connected with a first pin of the transformer T1, and the other end of the twenty-first resistor R21 is connected with an eighth pin (Vcc) of the high-frequency switch chip U4;
one end of a twenty-second resistor R22, one end of a twenty-second resistor R22 is connected with the fourth pin of the transformer T1, and the other end of the twenty-second resistor R22 is connected with the second pin (Vsense) of the high-frequency switch chip U4;
one end of a twenty-third resistor R23, one end of a twenty-third resistor R23 is connected with the other end of the twenty-second resistor R22, and the other end of the twenty-third resistor R23 is grounded;
a fourth pin of the first optocoupler RL1, a fourth pin of the first optocoupler RL1 is connected with a fourth pin (SD) of the high-frequency switch chip U4, a second pin of the first optocoupler RL1 is connected with the processing unit 10(BL _ CTRL), and a third pin of the first optocoupler RL1 is grounded;
one end of a twenty-fourth resistor R24, one end of a twenty-fourth resistor R24 is connected with a first pin of a first optocoupler RL1, and the other end of the twenty-fourth resistor R24 is externally connected with a +5V direct-current power supply;
one end of a twenty-fifth resistor R25, one end of the twenty-fifth resistor R25 is connected with a second pin of the first optocoupler RL 1;
a fourth diode D4, the fourth diode D4 may be a transient suppression diode, and one end of the fourth diode D4 is connected to the third pin of the transformer T1;
a fifth diode D5, wherein the anode of the fifth diode D5 is connected to the other end of the fourth diode D4, and the cathode of the fifth diode D5 is connected to the first pin of the transformer T1;
a sixth diode D6, wherein the anode of the sixth diode D6 is connected to the fourth pin of the transformer T1, and the cathode of the sixth diode D6 is connected to the eighth pin (Vcc) of the high-frequency switch chip U4;
a seventh diode D7, wherein the anode of the seventh diode D7 is connected to the eighth pin of the transformer T1;
an eighth diode D8, wherein the eighth diode D8 may be a schottky diode, an anode of the eighth diode D8 is grounded, and a cathode of the eighth diode D8 is connected to an eighth pin (Vcc) of the high frequency switch chip U4;
a ninth diode D9, wherein the anode of the ninth diode D9 is connected to the other end of the twenty-fifth resistor R25, and the cathode of the ninth diode D9 is grounded;
one end of an eighth capacitor C8, one end of an eighth capacitor C8 is connected with a sixth pin (Isense) of the high-frequency switch chip U4, and the other end of the eighth capacitor C8 is grounded;
one end of a ninth capacitor C9, one end of the ninth capacitor C9 is connected with the third pin (Vin) of the high-frequency switch chip U4, and the other end of the ninth capacitor C9 is grounded;
a tenth capacitor C10, wherein one end of the tenth capacitor C10 is connected to the eighth pin (Vcc) of the high-frequency switch chip U4, and the other end of the tenth capacitor C10 is grounded;
one end of an eleventh capacitor C11, one end of the eleventh capacitor C11 is connected with the second pin (Vsense) of the high-frequency switch chip U4, and the other end of the eleventh capacitor C11 is grounded;
a twelfth capacitor C12, a thirteenth capacitor C13 and a fourteenth capacitor C14, where the twelfth capacitor C12, the thirteenth capacitor C13 and the fourteenth capacitor C14 may all be polar capacitors, anodes of the twelfth capacitor C12, the thirteenth capacitor C13 and the fourteenth capacitor C14 are connected to a cathode of a seventh diode D7, and cathodes of the twelfth capacitor C12, the thirteenth capacitor C13 and the fourteenth capacitor C14 are connected to a tenth pin of the transformer T1;
a first pin (IP +) of the current sensor chip U5 is connected with a negative electrode of a seventh diode D7, a second pin (IP +) of the current sensor chip U5 is connected with a first pin (IP +) of the current sensor chip U5, a third pin (IP-) of the current sensor chip U5 is connected with a fourth pin (IP-) of the current sensor chip U5, the third pin of the current sensor chip is used for being connected with a positive electrode (BIJ +) of a single battery, a fifth pin (GND) of the current sensor chip U5 is grounded (+5V GND), and an eighth pin (VCC) of the current sensor chip U5 is used for being externally connected with a +5V direct-current power supply;
a fifteenth capacitor C15, wherein one end of the fifteenth capacitor C15 is connected to the sixth pin (FILTER) of the current sensor chip U5, and the other end of the fifteenth capacitor C15 is connected to the fifth pin (GND) of the current sensor chip U5;
a sixteenth capacitor C16, one end of which is connected to the processing unit 10(BL _ Current), and the other end of the sixteenth capacitor C16 is grounded;
one end of a twenty-sixth resistor R26, one end of a twenty-sixth resistor R26 is connected to the processing unit 10(BL _ Current), and the other end of the twenty-sixth resistor R26 is connected to a seventh pin (VIOUT) of the Current sensor chip U5.
In one embodiment of the present invention, as shown in fig. 4, the channel selection unit 20 may include:
a first end of the channel selection module 21 is connected with the other end of the balancing unit 30, and a second end of the channel selection module 21 is connected with the other end of the voltage acquisition unit 40;
and one end of the relay switch 22 is connected with the third end of the channel selection module 21, and the other end of the relay switch 22 is connected with the battery pack B.
In one embodiment of the present invention, as shown in fig. 8, the processing unit 10 may include a microprocessor, and the channel selection module 21 may include:
a plurality of logic shift registers U6, the eighth pin (GND) of each logic shift register U6 is grounded, the tenth pin of each logic shift register U6
Connected to the MR port of the microprocessor, the eleventh pin (SHCP) of each logic shift register U6 is connected to the SHCP port of the microprocessor, the twelfth pin (STCP) of each logic shift register U6 is connected to the STCP port of the microprocessor, and the thirteenth pin of each logic shift register U6
The logic shift register U6 connected between the microprocessor and the logic shift register U6 is connected with the DS port of the microprocessor through the fourteenth pin (DS) of the logic shift register U6, and the fourteenth pin (DS) of the logic shift register U6 connected between the two logic shift registers U6 is connected with the ninth pin (Q7S) of the previous logic shift register U6;
as for the relay switch 22, in one example of the present invention, as shown in fig. 9, the relay switch 22 may include:
a plurality of second optical couplers RL2, the first pin of every second optical coupler RL2 is external through twenty-seventh resistance R27 + 5V's direct current power supply, the second pin of this second optical coupler RL2 is used for receiving the control command of processing unit 10 through passageway selection module 21, the third pin of second optical coupler RL2 is connected with the one end of the battery cell of group battery, the fourth pin of second optical coupler RL2 is used for selecting the module 21 and is connected with the other end of acquisition switch 42 and equalizing switch 33 through the passageway. When the cell voltages of the cells are detected or balanced, the processing unit 10 may output a low level to the second pin of the second optocoupler RL2 to enable the light emitting diode of the second optocoupler RL2 to emit light, and turn on the connection between the third pin and the fourth pin of the second optocoupler RL2, so that the collecting switch 42 and the balancing switch 33 are connected with one end of the cell connected with the second optocoupler RL 2. The processing unit 10 further controls the on/off of the collecting switch 42 and the equalizing switch 33 to realize the voltage collecting and equalizing operations of the voltage collecting unit 40 and the equalizing unit 30 on the single batteries.
In another example of the present invention, as shown in fig. 10, each relay switch 22 may include: the optical coupler comprises at least one third optical coupler RL3 and at least one fourth optical coupler RL4, wherein the third optical coupler RL3 corresponds to the fourth optical coupler RL4 in a one-to-one mode;
a second pin of each third optocoupler RL3 is used for receiving a control instruction of the processing unit 10 through the channel selection module 21, a third pin of each third optocoupler RL3 is connected with one end of one single battery, and a fourth pin of each third optocoupler RL3 is used for being connected with the other ends of the acquisition switch 42 and the equalization switch 33 through the channel selection module 21;
a first pin of each fourth optical coupler RL4 is externally connected with a +5V direct-current power supply through a twenty-eighth resistor R28, a second pin of each fourth optical coupler RL4 is connected with a first pin of a corresponding third optical coupler RL3, a third pin of each fourth optical coupler RL4 is connected with the other end of the single battery, and a fourth pin of each fourth optical coupler RL4 is used for being connected with the other ends of the acquisition switch 42 and the equalization switch 33 through the channel selection module 21. When the single battery needs to be detected and balanced, the processing unit 10 may output a low level to the second pin of the third optocoupler RL3, so that the light emitting diodes of the third optocoupler RL3 and the fourth optocoupler RL4 emit light, and further the connection between the third pin and the fourth pin of the third optocoupler and the fourth pin is conducted, and further the collecting switch 42 and the balancing switch 33 are connected with two ends of the single battery. The processing unit 10 may implement the voltage collection and equalization operations of the voltage collection unit 40 and the equalization unit 30 on the single batteries by controlling the collection switch 42 and the equalization switch 33.
In one embodiment of the present invention, as shown in fig. 11, the temperature collection unit 50 may include:
a plurality of thermistors NTC1 respectively arranged on the single batteries, one end of each thermistor NTC1 is grounded;
a plurality of twenty-ninth resistors R29, wherein one end of each twenty-ninth resistor R29 is externally connected with a +4.096V direct-current power supply, and the other end of each twenty-ninth resistor R29 is connected with the other end of the thermistor NTC;
an analog channel multiplexer U7, wherein multiple input terminals (Y0-Y7) of the analog channel multiplexer U7 are respectively connected to the node between each twenty-ninth resistor R29 and the thermistor NTC1, the positive electrode (VCC) of the power supply pin of the analog channel multiplexer U7 is used for externally connecting a +5V direct current power supply, the negative electrode (GND) of the power supply pin of the analog channel multiplexer U7 is grounded, the VEE pin of the analog channel multiplexer U7 is connected with the negative electrode of the power supply pin of the analog channel multiplexer U7, and the enable pin of the analog channel multiplexer U7
The ninth pin (S2), the tenth pin (S1), and the eleventh pin (S0) are connected to the processing unit 10. The processing unit 10 may implement the one-by-one detection of the temperature of each unit cell by outputting high and low levels to the ninth pin (S2), the tenth pin (S1), and the eleventh pin (S0) of the analog channel multiplexer U7, respectively, according to the encoding principle of a three-bit binary number.
A positive phase input end of a third operational amplifier U8 of the third operational amplifier U8 is connected with an output pin of the analog channel multiplexer U7, and a negative phase input end of the third operational amplifier U8 is connected with an output end of the third operational amplifier U8;
and the thirty-third resistor R30 is connected with the processing unit 10 through the thirty-third resistor R30 at the output end of the third operational amplifier U8.
Another aspect of the present invention also provides an active equalization circuit for a battery pack, which may include an active equalization circuit as illustrated in fig. 3 to 11, the active equalization circuit being controlled by an active equalization method as illustrated in fig. 1 to achieve equalization of unit cells of the battery pack.
In this embodiment of the invention, each capacitor is balanced by a non-polar capacitor, except for the noted polar capacitor. In addition, the specific structure of the circuit as shown in fig. 4 to 10 is only limited to supplement and explain the present invention, and does not limit the scope of protection of the present invention. Under the same technical idea of the present invention, simple modifications (such as changes to the connection way of the resistors) to the specific structure of the circuit shown in fig. 4 and 10 belong to the protection scope of the present invention.
Through the technical scheme, the active equalization method and the active equalization circuit for the battery pack provided by the invention can perform temperature compensation calculation on the detection value when detecting the monomer voltage of the battery pack by aiming at the characteristic that the temperature of the battery pack is not uneven, so that the accurate detection of the monomer voltage of the battery pack is realized, and the battery pack is actively equalized according to the calculated equivalent voltage, so that the reasonability of selection of the equalized battery pack is improved, and the equalization efficiency of the battery pack is improved.
Although the embodiments of the present invention have been described in detail with reference to the accompanying drawings, the embodiments of the present invention are not limited to the details of the above embodiments, and various simple modifications can be made to the technical solution of the embodiments of the present invention within the technical idea of the embodiments of the present invention, and the simple modifications all belong to the protection scope of the embodiments of the present invention.
It should be noted that the various features described in the above embodiments may be combined in any suitable manner without departing from the scope of the invention. In order to avoid unnecessary repetition, the embodiments of the present invention will not be described separately for the various possible combinations.
Those skilled in the art can understand that all or part of the steps in the method for implementing the above embodiments may be implemented by a program to instruct related hardware, where the program is stored in a storage medium and includes several instructions to enable a (may be a single chip, a chip, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a Random Access Memory (RAM), a magnetic disk or an optical disk, and other various media capable of storing program codes.
In addition, various different embodiments of the present invention may be arbitrarily combined with each other, and the embodiments of the present invention should be considered as disclosed in the disclosure of the embodiments of the present invention as long as the embodiments do not depart from the spirit of the embodiments of the present invention.
Claims (9)
1. An active equalization method for a battery pack, the active equalization method comprising:
obtaining a relation curve of voltage and residual capacity of the single battery of the battery pack at different temperatures through experiments;
respectively detecting the temperature and the voltage of each single battery;
performing compensation calculation according to the temperature and the voltage, and determining the equivalent voltage of each single battery;
judging whether the battery pack needs to be balanced or not according to each equivalent voltage;
balancing the single battery with the lowest equivalent voltage under the condition that the battery pack needs to be started for balancing;
after balancing for a period of time, detecting the voltage of each single battery again, judging the balancing condition, and stopping the active balancing method under the condition of not starting balancing;
the active equalization method further comprises:
employing an active equalization circuit for a battery pack to perform the active equalization method, the active equalization circuit comprising:
the temperature acquisition unit is used for acquiring the temperature of each single battery of the battery pack;
the voltage acquisition unit is used for acquiring the voltage of the single battery of the battery pack;
the balancing unit is used for carrying out balancing operation on the battery pack;
a first end of the channel selection unit is connected with the voltage acquisition unit, a second end of the channel selection unit is connected with the equalization unit, and a third end of the channel selection unit is connected with the battery pack;
and the processing unit is respectively connected with the temperature acquisition unit, the voltage acquisition unit, the equalization unit and the channel selection unit.
2. The active equalization method of claim 1 wherein the voltage acquisition unit comprises:
one end of the voltage acquisition module is connected with the processing unit;
one end of the acquisition switch is connected with the other end of the voltage acquisition module, the other end of the acquisition switch is connected with the first end of the channel selection unit, and the control end of the acquisition switch is connected with the processing unit;
the voltage acquisition module includes:
one end of the first resistor and the other end of the first resistor are respectively connected with the anode and the cathode of the single battery;
one end of the second resistor is connected with one end of the first resistor;
one end of the third resistor is connected with the other end of the first resistor;
the negative electrode of the power supply end of the first operational amplifier is grounded;
the anode of the first diode is connected with the inverting input end of the first operational amplifier, and the cathode of the first diode is connected with the non-inverting input end of the first operational amplifier;
the anode of the second diode is connected with the positive-phase input end of the first operational amplifier, and the cathode of the second diode is connected with the negative-phase input end of the first operational amplifier;
the fourth resistor is connected between the inverting input end of the first operational amplifier and the output end of the first operational amplifier;
the fifth resistor is connected between the positive-phase input end of the first operational amplifier and the negative electrode of the power supply end of the first operational amplifier;
one end of the first inductor is used for being externally connected with a +5V direct-current power supply, and the other end of the first inductor is connected with the anode of the power supply end of the first operational amplifier;
the other end of the first inductor is grounded through the first capacitor and the second capacitor respectively;
and the inverting input end of the second operational amplifier is connected with the output end of the second operational amplifier, the non-inverting input end of the second operational amplifier is connected with the output end of the first operational amplifier, and the output end of the second operational amplifier is connected with the processing unit.
3. The active equalization method of claim 2 wherein the equalization unit comprises:
a boost module;
the voltage boosting module is connected with the transformer voltage reduction module;
and one end of the equalizing switch is connected with the other end of the transformer voltage reduction module, and the other end of the equalizing switch is connected with the second end of the channel selection unit.
4. The active equalization method of claim 3 wherein the boost module comprises:
one end of the sixth resistor is externally connected with a +12V direct-current power supply;
one end of the seventh resistor is connected with the other end of the sixth resistor, and the other end of the seventh resistor is grounded;
one end of the second inductor is connected with one end of the sixth resistor;
the anode of the third diode is connected with the other end of the second inductor, and the cathode of the third diode is connected with the transformer step-down module;
the first pin and the sixth pin of the boost chip are grounded, and the seventh pin of the boost chip is connected with a node between the sixth resistor and the seventh resistor;
one end of the eighth resistor is connected with a ninth pin of the boost chip;
one end of the third capacitor is connected with the other end of the eighth resistor, and the other end of the third capacitor is connected with a tenth pin of the boost chip;
one end of the ninth resistor is connected with the eighth pin of the boost chip;
one end of the fourth capacitor is connected with the other end of the ninth resistor, and the other end of the fourth capacitor is connected with a sixth pin of the boost chip;
one end of the tenth resistor is connected with a sixth pin of the boost chip;
one end of the eleventh resistor is connected with the other end of the ninth resistor, and the other end of the eleventh resistor is connected with the other end of the tenth resistor;
a gate of the first field effect transistor is connected with a fifth pin of the boost chip, a source of the first field effect transistor is connected with the other end of the tenth resistor, and a drain of the first field effect transistor is connected with a node between the second inductor and the third diode;
one end of the fifth capacitor is connected with the fourth pin of the boost chip, and the other end of the fifth capacitor is grounded;
the sixth capacitor is connected between the second pin and the third pin of the boost chip;
one end of the twelfth resistor is connected with the first pin of the boost chip, and the other end of the twelfth resistor is connected with one end of the second inductor;
one end of the thirteenth resistor is connected with a third pin of the boosting chip;
one end of the seventh capacitor is connected with the other end of the thirteenth resistor, and the other end of the seventh capacitor is connected with the second pin of the boost chip;
one end of the fourteenth resistor is connected with the cathode of the third diode, and the other end of the fourteenth resistor is connected with the second pin of the boost chip;
and one end of the fifteenth resistor is connected with the other end of the fourteenth resistor, and the other end of the fifteenth resistor is grounded.
5. The active equalization method of claim 4 wherein the transformer buck unit comprises:
a first pin of the transformer is connected with the boosting module, a fifth pin of the transformer is grounded, and a tenth pin of the transformer is used for being connected with the negative electrode of the single battery;
the drain electrode of the second field effect transistor is connected with the third pin of the transformer;
one end of the sixteenth resistor is connected with the source electrode of the second field effect transistor, and the other end of the sixteenth resistor is grounded;
the first pin of the high-frequency switch chip is suspended, and the fifth pin of the high-frequency switch chip is grounded;
one end of the seventeenth resistor is connected with a sixth pin of the high-frequency switch chip, and the other end of the seventeenth resistor is connected with one end of the sixteenth resistor;
one end of the eighteenth resistor is connected with the seventh pin of the high-frequency switch chip, and the other end of the eighteenth resistor is connected with the grid electrode of the second field-effect tube;
a nineteenth resistor connected between the fourth pin of the high-frequency switch chip and a ground terminal;
one end of the twentieth resistor is connected with the first pin of the transformer, and the other end of the twentieth resistor is connected with the third pin of the high-frequency switch chip;
one end of the twenty-first resistor is connected with the first pin of the transformer, and the other end of the twenty-first resistor is connected with the eighth pin of the high-frequency switch chip;
one end of the twenty-second resistor is connected with the fourth pin of the transformer, and the other end of the twenty-second resistor is connected with the second pin of the high-frequency switch chip;
one end of the twenty-third resistor is connected with the other end of the twenty-second resistor, and the other end of the twenty-third resistor is grounded;
a fourth pin of the first optical coupler is connected with a fourth pin of the high-frequency switch chip, a second pin of the first optical coupler is connected with the processing unit, and a third pin of the first optical coupler is grounded;
one end of the twenty-fourth resistor is connected with the first pin of the first optocoupler, and the other end of the twenty-fourth resistor is externally connected with a +5V direct-current power supply;
one end of the twenty-fifth resistor is connected with the second pin of the first optocoupler;
one end of the fourth diode is connected with a third pin of the transformer;
the anode of the fifth diode is connected with the other end of the fourth diode, and the cathode of the fifth diode is connected with the first pin of the transformer;
the anode of the sixth diode is connected with the fourth pin of the transformer, and the cathode of the sixth diode is connected with the eighth pin of the high-frequency switch chip;
the anode of the seventh diode is connected with the eighth pin of the transformer;
the anode of the eighth diode is grounded, and the cathode of the eighth diode is connected with the eighth pin of the high-frequency switch chip;
a ninth diode, an anode of which is connected to the other end of the twenty-fifth resistor, and a cathode of which is grounded;
one end of the eighth capacitor is connected with the sixth pin of the high-frequency switch chip, and the other end of the eighth capacitor is grounded;
one end of the ninth capacitor is connected with the third pin of the high-frequency switch chip, and the other end of the ninth capacitor is grounded;
one end of the tenth capacitor is connected with the eighth pin of the high-frequency switch chip, and the other end of the tenth capacitor is grounded;
one end of the eleventh capacitor is connected with the second pin of the high-frequency switch chip, and the other end of the eleventh capacitor is grounded;
a twelfth capacitor, a thirteenth capacitor and a fourteenth capacitor, wherein a cathode of the seventh diode is connected to a tenth pin of the transformer through the twelfth capacitor, the thirteenth capacitor and the fourteenth capacitor, respectively;
a first pin of the current sensor chip is connected with a negative electrode of the seventh diode, a second pin of the current sensor chip is connected with the first pin of the current sensor chip, a third pin of the current sensor chip is connected with a fourth pin of the current sensor chip, the third pin of the current sensor chip is used for being connected with a positive electrode of the single battery, a fifth pin of the current sensor chip is grounded, and an eighth pin of the current sensor chip is used for being externally connected with a +5V direct current power supply;
one end of the fifteenth capacitor is connected with a sixth pin of the current sensor chip, and the other end of the fifteenth capacitor is connected with a fifth pin of the current sensor chip;
one end of the sixteenth capacitor is connected with the processing unit, and the other end of the sixteenth capacitor is grounded;
one end of the twenty-sixth resistor is connected with the processing unit, and the other end of the twenty-sixth resistor is connected with a seventh pin of the current sensor chip.
6. The active equalization method of claim 5 wherein the channel selection unit comprises:
a first end of the channel selection module is connected with the other end of the balancing unit, and a second end of the channel selection module is connected with the other end of the voltage acquisition unit;
and one end of the relay switch is connected with the third end of the channel selection module, and the other end of the relay switch is connected with the battery pack.
7. The active equalization method of claim 6 wherein the processing unit comprises a microprocessor, and wherein the channel selection module comprises:
a plurality of logic shift registers, wherein an eighth pin of each logic shift register is grounded, a tenth pin of each logic shift register is connected with an MR port of the microprocessor, an eleventh pin of each logic shift register is connected with an SHCP port of the microprocessor, a twelfth pin of each logic shift register is connected with an STCP port of the microprocessor, a thirteenth pin of each logic shift register is connected with an OE port of the microprocessor, the logic shift register connected with the microprocessor is connected with a DS port of the microprocessor through a fourteenth pin of the logic shift register, and a fourteenth pin of the logic shift register connected between two logic shift registers is connected with a ninth pin of the previous logic shift register;
the relay switch includes:
a plurality of second opto-couplers, every the external + 5V's of first pin of second opto-coupler passes through twenty-seventh resistance DC power supply, the second pin of second opto-coupler is used for passing through the control command that processing unit was received to the passageway selection module, the third pin of second opto-coupler with the one end of the battery cell of group battery is connected, the fourth pin of second opto-coupler is used for selecting the module through the passageway and is connected with the other end of gathering switch and equalizing switch.
8. The active equalization method of claim 7 wherein the processing unit comprises a microprocessor, and wherein the channel selection module comprises:
a plurality of logic shift registers, wherein an eighth pin of each logic shift register is grounded, a tenth pin of each logic shift register is connected with an MR port of the microprocessor, an eleventh pin of each logic shift register is connected with an SHCP port of the microprocessor, a twelfth pin of each logic shift register is connected with an STCP port of the microprocessor, a thirteenth pin of each logic shift register is connected with an OE port of the microprocessor, the logic shift register connected between the microprocessor and the logic shift register is connected with a DS port of the microprocessor through a fourteenth pin of the logic shift register, and a fourteenth pin of the logic shift register connected between two logic shift registers is connected with a ninth pin of the last logic shift register;
the relay switch includes: the optical coupler comprises at least one third optical coupler and at least one fourth optical coupler, wherein the third optical coupler corresponds to the fourth optical coupler one by one;
a second pin of each third optocoupler is used for receiving a control instruction of the processing unit through the channel selection module, a third pin of each third optocoupler is connected with one end of one single battery, and a fourth pin of each third optocoupler is used for being connected with the other ends of the acquisition switch and the balance switch through the channel selection module;
every the external + 5V's of first pin of fourth opto-coupler through the eighteen resistance of second direct current power supply, every the second pin of fourth opto-coupler with correspond the first pin of third opto-coupler is connected, every the third pin of fourth opto-coupler is connected with this a battery cell's the other end, every the fourth pin of fourth opto-coupler is used for passing through the passageway select module with gather the switch with the other end of equalizing switch is connected.
9. The active equalization method of claim 1 wherein the temperature acquisition unit comprises:
the plurality of thermistors are respectively arranged on the single batteries, and one end of each thermistor is grounded;
one end of each twenty-ninth resistor is externally connected with a +4.096V reference voltage, and the other end of each twenty-ninth resistor is connected with the other end of the thermistor;
a plurality of input ends of the analog channel multiplexer are respectively connected to a node between each twenty-ninth resistor and the thermistor, the positive electrode of a power supply pin of the analog channel multiplexer is used for being externally connected with a +5V direct-current power supply, the negative electrode of the power supply pin of the analog channel multiplexer is grounded, a VEE pin of the analog channel multiplexer is connected with the negative electrode of the power supply pin of the analog channel multiplexer, and an enable pin, a ninth pin, a tenth pin and an eleventh pin of the analog channel multiplexer are connected with the processing unit;
a positive-phase input end of the third operational amplifier is connected with an output pin of the analog channel multiplexer, and a negative-phase input end of the third operational amplifier is connected with an output end of the third operational amplifier;
and the output end of the third operational amplifier is connected with the processing unit through the thirtieth resistor.
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| CN114421567A (en) * | 2022-01-20 | 2022-04-29 | 重庆唐古拉科技有限公司 | Active equalization system and method for battery pack |
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| CN1601296A (en) * | 2003-07-29 | 2005-03-30 | 索尼株式会社 | Secondary cell residual capacity calculation method and battery pack |
| CN104348234A (en) * | 2014-11-21 | 2015-02-11 | 南京国臣信息自动化技术有限公司 | Battery management system with active equalization system |
| CN108879817A (en) * | 2018-06-06 | 2018-11-23 | 安徽锐能科技有限公司 | Active equalization method and system for battery pack |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN1601296A (en) * | 2003-07-29 | 2005-03-30 | 索尼株式会社 | Secondary cell residual capacity calculation method and battery pack |
| CN104348234A (en) * | 2014-11-21 | 2015-02-11 | 南京国臣信息自动化技术有限公司 | Battery management system with active equalization system |
| CN108879817A (en) * | 2018-06-06 | 2018-11-23 | 安徽锐能科技有限公司 | Active equalization method and system for battery pack |
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