CN109037145A - A kind of TSV through hole and its sputtering technology - Google Patents
A kind of TSV through hole and its sputtering technology Download PDFInfo
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- CN109037145A CN109037145A CN201810759488.4A CN201810759488A CN109037145A CN 109037145 A CN109037145 A CN 109037145A CN 201810759488 A CN201810759488 A CN 201810759488A CN 109037145 A CN109037145 A CN 109037145A
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/02—Pretreatment of the material to be coated
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- C—CHEMISTRY; METALLURGY
- C23—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; CHEMICAL SURFACE TREATMENT; DIFFUSION TREATMENT OF METALLIC MATERIAL; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL; INHIBITING CORROSION OF METALLIC MATERIAL OR INCRUSTATION IN GENERAL
- C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
- C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
- C23C14/22—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the process of coating
- C23C14/34—Sputtering
- C23C14/35—Sputtering by application of a magnetic field, e.g. magnetron sputtering
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76841—Barrier, adhesion or liner layers
- H01L21/76871—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers
- H01L21/76873—Layers specifically deposited to enhance or enable the nucleation of further layers, i.e. seed layers for electroplating
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
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- Condensed Matter Physics & Semiconductors (AREA)
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- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Abstract
The invention discloses a kind of TSV through hole and its sputtering technology, the sputtering technology includes seed layer sputtering, and the seed layer sputtering uses substep sputtering method.The present invention can make the barrier layer of sputtering and seed layer more continuous, fine and close by adjusting, optimization sputtering power and deposition rate；Pass through the through-hole filling effect after plating, it is determined that barrier layer and seed layer most preferably sputter thickness；Seed layer substep sputtering method is developed simultaneously, prevents the continuous sputtering process medium temperature of seed layer from spending the high damage caused by chip, also avoids the film layer for continuously sputtering generation abnormal.
Description
Technical field
The present invention relates to semiconductors manufactures and encapsulation field, and in particular to a kind of TSV through hole and its sputtering technology.
Background technique
With the fast development of semicon industry and the continuous renewal of consumer electronics demand, in the traditional 2D in certain fields
Encapsulation has been unable to satisfy the demand of product, and 3D encapsulation is come into being.
The encapsulation of TSV (through silicon via) through silicon via is that stacked chips realize interconnection in three dimensional integrated circuits
A kind of new 3D packing forms.With connection apart from it is short, signal delay can be reduced, reduce capacitive/inductive, realize chip chamber
The advantages that low energy consumption, high speed communication, enhancing broadband and realization miniaturization.Usual TSV through silicon via encapsulation is considered as after lead key
It closes, carry from the forth generation encapsulation technology after bonding and flip-chip.
TSV (through silicon via) through silicon via is encapsulated in while having the advantages that above that there is also following works
Skill difficult point: (1) etching of through-hole；(2) filling of through-hole；(3) stacking form；(4) bonding pattern；(5) processing of ultra-thin wafers.
Wherein the filling of through-hole is the key that 3D integrates work step, and TSV filling effect is directly related to the reliability and yield of integrated technology,
High reliability and yield is the key that can 3D TSV encapsulation mass production again.And through-hole sputtering is the key that through-hole filling, only
There is a continuous metal layer on through-hole side wall and bottom deposit, when plating just can be carried out conducting, to realize to the intact of deep hole
Fall into filling.
Magnetron sputtering realization is generallyd use to the continuity uniform fold of deep hole side wall and bottom seed layer, using fast electric
Plating, which is realized, fills the zero defect of deep hole.But conventional magnetron sputtering technique is difficult to the company of deposition on the through-hole side wall of high-aspect-ratio
Continuous metal layer can make chip since temperature is excessively high in continuous sputtering process additionally due to the seed layer thickness of sputtering is thicker
It is abnormal at damage and film layer.Therefore, it is necessary to be improved to the prior art.
Summary of the invention
The technical problem to be solved by the present invention is to overcome the technological deficiency of background technique, provide a kind of TSV through hole and its
Sputtering technology.The present invention is by adjusting, optimization sputtering power and deposition rate, and the barrier layer that can make sputtering and seed layer are more
It is continuous, fine and close；Pass through the through-hole filling effect after plating, it is determined that barrier layer and seed layer most preferably sputter thickness；It opens simultaneously
Seed layer substep sputtering method has been sent out, has prevented the continuous sputtering process medium temperature of seed layer from spending the high damage caused by chip, also avoids
The film layer that continuous sputtering generates is abnormal.
The present invention solves technological means used by above-mentioned technical problem are as follows:
A kind of TSV through hole sputtering technology, the sputtering technology include seed layer sputtering, and the seed layer sputtering is using substep
Sputtering method.
Preferably, depth-to-width ratio≤20 of the TSV through hole: 1.
Preferably, the substep sputtering method includes the following steps: that the sputtering for setting the seed layer with a thickness of X, first sputters X/2
± Y suspends 60s ± Z, then sputters X- (X/2 ± Y)；The sputtering thickness unit of the seed layer is
It is highly preferred that the X isThe Y isThe Z is 0~20s.
Most preferably, the X isThe Y isThe Z is 0s.
Preferably, the sputtering technology includes the following steps: (1) ultrasonic wave and IPA cleaning；(2) baking oven toasts；(3) it hinders
Barrier and seed layer sputtering；The effect of the ultrasonic wave and IPA cleaning is to remove the surface wafer and foreign matter in through-hole and dirty
Dirt guarantees the barrier layer of sputtering and the adhesion strength of seed layer and the surface wafer and side wall；The effect of baking oven baking be for
Still remain in the moisture in the surface wafer and through-hole after removal drying；The barrier layer and seed layer sputtering refer to utilization
Magnetron sputtering deposits one layer of barrier layer and seed layer in the surface wafer and TSV through hole, and when plating carries out conductive.
Preferably, in the step (1), the time of the ultrasonic wave and IPA cleaning is 15~20min；Conventional products
Ultrasonic wave and IPA scavenging period are 5~10min, to guarantee the cleaning effect in TSV through hole, the ultrasonic wave of TSV through hole product and
IPA scavenging period is 15~20min.
Preferably, in the step (1), further include the following steps: that QDR is washed after the ultrasonic wave and IPA cleaning
It is dried with SRD.
Preferably, the time of the SRD drying is 12~15min；The SRD drying time of conventional products is 8~10min；
For the moisture in removal through-hole, the drying time of TSV through hole product is 12~15min.
Preferably, in the step (2), in the baking oven baking, to prevent Pad in baking process from aoxidizing, nitrogen flow
Control is in 30 ± 10L.
Preferably, in the step (2), the time of the baking is 80~100min；The baking time of conventional products is
30~60min, to guarantee that remaining moisture removal is clean in through-hole, the baking time of TSV through hole product is 80~100min.
Preferably, in the step (3), the barrier layer is titanium atom, and the seed layer is copper atom.
Preferably, in the step (3), the power of the sputtering is 3~3.5kw, and deposition pressure is 4.5~5mtorr；
The sputtering power of conventional products is 2~2.5kw, and deposition pressure is 3.5~4mtorr, to guarantee through-hole internal barrier and seed layer
With the bond strength of through-hole side wall, the sputtering power of TSV through hole product is 3~3.5kw, and deposition pressure is 4.5~5mtorr.
Preferably, in the step (3), the sputtering on the barrier layer with a thickness of The seed layer
Sputtering with a thickness ofConventional products barrier layer sputtering with a thickness ofThe sputtering of seed layer
With a thickness ofTo guarantee uniformly, continuously cover one layer of barrier layer and seed layer in through-hole, to keep away
Exempt to cause route to lack when plating filling, the sputtering on the barrier layer of TSV through hole product with a thickness ofSeed layer
Sputtering with a thickness ofConventional products are using a step sputtering method, i.e., disposable sputteringBarrier layer andSeed layer, TSV through hole product due to sputtering seed thickness degree compared with
Thickness, to prevent continuous sputtering process medium temperature from spending the high film layer exception for damaging and avoiding caused by chip continuously to sputter generation,
Substep sputtering method is used when TSV through hole product sputtering seed layer, i.e., first sputters
Seed layer, be then spaced 40~80s, sputter the seed layer of remaining thickness again after temperature is cooling.
A kind of TSV through hole is prepared using above-mentioned technique.
Basic principle of the invention:
The present invention can effectively remove foreign matter and dirty, guarantee in the surface wafer and through-hole by ultrasonic wave and IPA cleaning
The adhesion strength of the barrier layer of sputtering and seed layer and the surface wafer and side wall；Baking oven baking remains in when can remove cleaning
The moisture on the surface wafer guarantees sputtering effect；Seed layer substep sputtering can prevent continuous sputtering process medium temperature from spending height to chip
Caused by damage and avoid continuously to sputter the film layer generated it is abnormal.
Compared with prior art, technical solution of the present invention has the advantages that
The present invention is by adjusting, optimization sputtering power and deposition rate, and the barrier layer that can make sputtering and seed layer are more
It is continuous, fine and close；Pass through the through-hole filling effect after plating, it is determined that barrier layer and seed layer most preferably sputter thickness；It opens simultaneously
Seed layer substep sputtering method has been sent out, has prevented the continuous sputtering process medium temperature of seed layer from spending the high damage caused by chip, also avoids
The film layer that continuous sputtering generates is abnormal.
Detailed description of the invention
Fig. 1 is the finally filled product SEM effect picture (250 times of amplification) of TSV through hole made from the embodiment of the present invention 1；
Fig. 2 is the finally filled product SEM effect picture (800 times of amplification) of TSV through hole made from the embodiment of the present invention 1.
Specific embodiment
In order to better understand the content of the present invention, it is described further combined with specific embodiments below with attached drawing.Ying Li
Solution, these embodiments are only used for that the present invention is further described, rather than limit the scope of the invention.In addition, it should also be understood that,
After having read the contents of the present invention, person skilled in art makes some nonessential changes or adjustment to the present invention, still belongs to
In protection scope of the present invention.
Examples 1 to 3 and 1~5 device therefor of comparative example respectively from:
Ultrasonic cleaning and drying: the rotation that the supersonic wave cleaning machine (model HWCJ4090B) of Jiangsu production, Beijing produce
Turn to rinse dryer (model CXS-2200C)；
Baking oven baking: the computermatic four cavitys cleaning oven (model CB5010) of Anhui production；
Magnetron sputtering: Sputtering System (model M2i8) produced in USA.
Magnetron sputtering thickness monitoring: four probe machines (CDE Resmap) produced in USA, model Resmap178 pass through
Piece is aoxidized to carry out；
A kind of TSV through hole sputtering technology, includes the following steps:
(1) ultrasonic wave and IPA cleaning；(2) baking oven toasts；(3) barrier layer and seed layer sputtering.
In the step (1), the time of the ultrasonic wave and IPA cleaning is 15~20min.
In the step (1), further include the following steps: that QDR washing and SRD are got rid of after the ultrasonic wave and IPA cleaning
It is dry；The time of the SRD drying is 12~15min.
In the step (2), in the baking oven baking, to prevent Pad in baking process from aoxidizing, nitrogen flow is controlled 30
±10L。
In the step (2), the time of the baking is 80~100min
In the step (3), the barrier layer is titanium atom, and the seed layer is copper atom.
In the step (3), the power of the sputtering is 3~3.5kw, and deposition pressure is 4.5~5mtorr.
In the step (3), the sputtering on the barrier layer with a thickness ofThe sputtering of the seed layer is thick
Degree is
A kind of design parameter of TSV through hole sputtering technology described in Examples 1 to 3 and comparative example 1~5 is as shown in table 1.Its
Middle 1~2 seed layer of comparative example sputtering uses a step sputtering method, and the sputtering of 3~5 seed layer of comparative example uses substep sputtering method.
1 Examples 1 to 3 of table and comparative example 1~5TSV through-hole sputtering technology design parameter
Effect example
Electroplating effect and final product test after the technology of the present invention effect is electroplated by SEM observation in TSV through hole is good
Rate is fed back, and the equipment used is the scanning electron microscope (SEM) of Japan, model JSM-6510.
Using the seed layer substep sputtering technology as described in the embodiment of the present invention 1~3, the barrier layer of sputtering and seed layer connect
It is continuous, fine and close, it is good with TSV through hole side wall caking property, one layer of barrier layer and seed can uniformly, be continuously covered in TSV through hole
Layer, finally fills that obtained TSV through hole pattern is good, meets the requirement of TSV through hole (see Fig. 1 and Fig. 2).
The sputtering of 1~2 seed layer of comparative example uses a step sputtering method.Using the technique as described in comparative example 1, conventional sputter is usedTi+U, in TSV through hole can not successive sedimentation plating seed layer, when plating in through-hole metal can it is imperfect go out
It now interrupts, when electric performance test shows as short circuit；It is continuous to sputter using the technique as described in comparative example 2Ti+
U, segment chip is impaired, and electric performance test non-defective unit reduces, while film layer can be abnormal.
The sputtering of 3~5 seed layer of comparative example uses substep sputtering method.Using the technique as described in comparative example 3~5, although using
Substep sputtering method sputtering seed layer, but since parameter selection is inappropriate, it is unable to get the good TSV through hole of pattern.
Above description is not the limitation to invention, and the present invention is also not limited to the example above.The common skill of the art
For art personnel in the essential scope of invention, the variations, modifications, additions or substitutions made also should belong to protection scope of the present invention.
Claims (10)
1. a kind of TSV through hole sputtering technology, which is characterized in that the sputtering technology includes seed layer sputtering, and the seed layer is splashed
It penetrates using substep sputtering method.
2. a kind of TSV through hole sputtering technology as described in claim 1, which is characterized in that depth-to-width ratio≤20 of the TSV through hole
∶1。
3. a kind of TSV through hole sputtering technology as described in claim 1, which is characterized in that the substep sputtering method includes as follows
Step: the sputtering of the seed layer is set with a thickness of X, first sputters X/2 ± Y, suspends 60s ± Z, then sputter X- (X/2 ± Y).
4. a kind of TSV through hole sputtering technology as claimed in claim 3, which is characterized in that the X is
The Y isThe Z is 0~20s.
5. a kind of TSV through hole sputtering technology as claimed in claim 4, which is characterized in that the X isInstitute
Stating Y isThe Z is 0s.
6. a kind of TSV through hole sputtering technology as claimed in any one of claims 1 to 5, wherein, which is characterized in that the sputtering technology
Include the following steps: (1) ultrasonic wave and IPA cleaning；(2) baking oven toasts；(3) barrier layer and seed layer sputtering.
7. a kind of TSV through hole sputtering technology as claimed in claim 6, which is characterized in that the ultrasonic wave and IPA cleaning are laggard
One step includes the following steps: QDR washing and SRD drying；The time of the SRD drying is 12~15min.
8. a kind of TSV through hole sputtering technology as claimed in claim 6, which is characterized in that in the step (2), the baking oven
In baking, nitrogen flow is controlled in 30 ± 10L；The time of the baking is 80~100min.
9. a kind of TSV through hole sputtering technology as claimed in claim 6, which is characterized in that in the step (3), the blocking
Layer is titanium atom, and the seed layer is copper atom；The power of the sputtering is 3~3.5kw, and deposition pressure is 4.5~5mtorr；
The sputtering on the barrier layer with a thickness ofThe sputtering of the seed layer with a thickness of
10. a kind of TSV through hole is prepared using the technique as described in claim 1~9 any one.
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810759488.4A CN109037145A (en) | 2018-07-11 | 2018-07-11 | A kind of TSV through hole and its sputtering technology |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201810759488.4A CN109037145A (en) | 2018-07-11 | 2018-07-11 | A kind of TSV through hole and its sputtering technology |
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|---|---|
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110791746A (en) * | 2019-11-08 | 2020-02-14 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
-
2018
- 2018-07-11 CN CN201810759488.4A patent/CN109037145A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110791746A (en) * | 2019-11-08 | 2020-02-14 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN110791746B (en) * | 2019-11-08 | 2021-10-15 | 北京工业大学 | Method and device for rapidly filling vertical silicon through hole with liquid alloy |
| CN114959606A (en) * | 2022-05-13 | 2022-08-30 | 赛莱克斯微系统科技（北京）有限公司 | Preparation method of silicon through hole seed layer and preparation method of chip |
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