CN109036272B - Multi-line addressing driving system and method - Google Patents
Multi-line addressing driving system and method Download PDFInfo
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- CN109036272B CN109036272B CN201810997803.7A CN201810997803A CN109036272B CN 109036272 B CN109036272 B CN 109036272B CN 201810997803 A CN201810997803 A CN 201810997803A CN 109036272 B CN109036272 B CN 109036272B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
Abstract
The disclosure relates to the technical field of display, in particular to a multi-line addressing driving system and method. The system comprises: the device comprises a memory, a processor, a time schedule controller, a row driver and a column driver; the processor is used for reading one frame of image data from the memory, obtaining a corresponding driving time sequence waveform generation instruction based on a set scanning driving mode, and performing operation and block cutting on t rows of data in the read image data to obtain first matrix data and second matrix data, wherein t is more than or equal to 2; the time sequence controller is used for generating a corresponding driving time sequence waveform according to the driving time sequence waveform generating instruction; the row driver is used for controlling row driving of the display array module based on the driving time sequence waveform; the column driver is used for controlling the column driving of the display array module according to the first matrix data and the second matrix data. Thereby realizing the reliable drive to the display array module.
Description
Technical Field
The disclosure relates to the technical field of display, in particular to a multi-line addressing driving system and method.
Background
Nowadays, Display array modules are widely used in various industries, wherein Organic light Emitting diodes (Organic L light Emitting diodes, O L ED) are used as a novel light Emitting technology, which has incomparable advantages with other flat panel displays, and its main technical features are self-luminescence, full-color Display, high brightness, high contrast, low voltage, low power consumption, light and thin, the volume and weight of which are only 1/3 of liquid Crystal displays (L iquid Crystal Display, L CD), high light Emitting efficiency, fast response, wide viewing angle, etc. O L ED is considered by industry as a third generation Display technology following L CD, but the reliability is still to be improved.
Disclosure of Invention
Accordingly, the present disclosure provides a multi-line addressing driving system and method.
In a first aspect, the present disclosure provides a multi-line addressing driving system for driving a display array module, the multi-line addressing driving system comprising: the device comprises a memory, a processor, a time schedule controller, a row driver and a column driver;
the memory is used for storing at least one frame of image data;
the processor is used for reading one frame of image data from the memory, obtaining a corresponding driving time sequence waveform generating instruction based on a set scanning driving mode, sending the driving time sequence waveform generating instruction to the time sequence controller, carrying out first operation and block cutting on t rows of data in the read image data to obtain first matrix data, carrying out second operation and block cutting on t rows of data in the read image data to obtain second matrix data, wherein t is more than or equal to 2;
the time sequence controller is used for generating a corresponding driving time sequence waveform according to the driving time sequence waveform generating instruction;
the row driver is used for controlling row driving of the display array module based on the driving time sequence waveform;
and the column driver is used for controlling the column driving of the display array module according to the first matrix data and the second matrix data.
Optionally, the processor is configured to perform a first operation and block cutting on t rows of data in the read image data to obtain first matrix data:
dicing t-line data in the read image data according to a block of t × 1;
the minimum value of the color in each tile of t × 1 is calculated, and the first matrix data is formed from all the calculated minimum values.
Optionally, the processor is configured to perform a second operation and block cutting on t rows of data in the read image data to obtain second matrix data by:
performing gamma positive transformation on t rows of data in the read image data;
slicing the t-row data subjected to gamma forward transformation according to the blocks of t × 1, and calculating the minimum value of colors in each block of t × 1;
subtracting the minimum value of each color from each block of t × 1 to obtain transition matrix data;
and performing gamma inverse transformation on the transition matrix data to obtain second matrix data.
Optionally, the multi-line addressing driving system further comprises a corrector, wherein the corrector is used for performing gamma correction on the first matrix data and the second matrix data respectively;
and the column driver is used for controlling the column driving of the display array module according to the first matrix data and the second matrix data after gamma correction.
Optionally, the processor is further configured to determine whether all the read image data are completely read, and if not, continue to read another t rows of data in the image data, generate a corresponding driving timing waveform generation instruction and send the driving timing waveform generation instruction to the timing controller, and perform operation and block cutting on the another t rows of data to obtain new first matrix data and second matrix data.
Optionally, the driving display array module is an organic light emitting diode pixel array.
In a second aspect, the present disclosure further provides a multi-line addressing driving method, applied to a processor in a multi-line addressing driving system to drive a display array module, where the multi-line addressing driving system includes a memory, a timing controller, a row driver, a column driver, and the processor; the method comprises the following steps:
reading a frame of image data from the memory;
obtaining a corresponding driving time sequence waveform generating instruction based on a set scanning driving mode and sending the corresponding driving time sequence waveform to the time sequence controller so as to generate a corresponding driving time sequence waveform, so that the row driver controls the row driving of the display array module based on the driving time sequence waveform, wherein t is more than or equal to 2;
and performing first operation and block cutting on t rows of data in the read image data to obtain first matrix data, performing second operation and block cutting on t rows of data in the read image data to obtain second matrix data, so that the column driver controls column driving of the display array module according to the first matrix data and the second matrix data.
Optionally, the step of performing a first operation and dicing on t rows of data in the read image data to obtain first matrix data includes:
dicing t-line data in the read image data according to a block of t × 1;
the minimum value of the colors in each tile of t × 1 is calculated, resulting in first matrix data.
Optionally, the step of performing a second operation and dicing on t rows of data in the read image data to obtain second matrix data includes:
performing gamma positive transformation on t rows of data in the read image data;
slicing the t-row data subjected to gamma forward transformation according to the blocks of t × 1, and calculating the minimum value of colors in each block of t × 1;
subtracting the minimum value of each color from each block of t × 1 to obtain transition matrix data;
and performing gamma inverse transformation on the transition matrix data to obtain second matrix data.
Optionally, the method further comprises:
and judging whether all the read image data are read or not, if not, continuing to read other t rows of data in the image data, generating a corresponding driving time sequence waveform generating instruction and sending the instruction to the time sequence controller, and operating and cutting the other t rows of data to obtain new first matrix data and second matrix data.
The multi-line addressing driving system and the multi-line addressing driving method have the advantages that the multi-line addressing driving system is ingeniously designed and integrated, the row driving of the display array module is controlled based on the driving time sequence waveform, the column driving of the display array module is controlled according to the first matrix data and the second matrix data, the multi-line driving mode effectively overcomes the defects of the traditional line-by-line single line scanning driving mode, the reliable driving of the display array module is achieved, the service life of the display array module can be effectively prolonged, the power consumption is reduced, and the resolution ratio is improved.
Drawings
In order to more clearly illustrate the technical solution of the present disclosure, the drawings needed to be used in the embodiments will be briefly described below. It is appreciated that the following drawings depict only certain embodiments of the disclosure and are therefore not to be considered limiting of its scope, for those skilled in the art will be able to derive additional related drawings therefrom without the benefit of the inventive faculty.
Fig. 1 is a block schematic diagram of a multi-line addressing driving system provided by the present disclosure.
Fig. 2 is another block diagram of the multi-line addressing driving system provided by the present disclosure.
Fig. 3 is a schematic block diagram of a multi-line addressing driving system provided by the present disclosure.
Fig. 4 is a flowchart illustrating a multi-line addressing driving method according to the present disclosure.
Fig. 5 is another flow chart of the multi-line addressing driving method provided by the present disclosure.
Fig. 6 is a schematic flow chart of a multi-line addressing driving method provided by the present disclosure.
Fig. 7 is a schematic diagram of a scanning driving scheme using a conventional scanning method.
Fig. 8 is a schematic diagram of a scan driving method provided in the present disclosure.
Fig. 9 is another schematic diagram of a scan driving method provided in the present disclosure.
Fig. 10 is a further schematic diagram of a scan driving method provided in the present disclosure.
Icon: 110-a memory; 120-a processor; 130-a time schedule controller; 140-row driver; 150-column driver; 160-an appliance; 200-display array module.
Detailed Description
Because of the superiority of O L ED performance, it is considered as the third generation display technology after L CD by the industry, however, it is found through investigation that the service life of O L ED is not long enough and the resolution of Passive Matrix organic electroluminescent diodes (Passive Matrix O L ED, PMO L ED) is low, which affects the popularization and application of O L ED.
In order to improve the applicability of the O L ED, the inventor finds that the main reasons of the O L ED with short service life and the low resolution of the PMO L ED include that the display array module is mainly driven by a line-by-line single-line scanning driving method in the prior art, and in the period of displaying a frame of image, the time for lighting each line of pixels in the display array module is short, so that the peak current required by each line of pixels is large to achieve the target brightness, thereby greatly reducing the service life of an O L ED element.
In view of the above, the present disclosure provides a multi-line addressing driving system and method, which are used for skillfully designing and integrating a multi-line addressing driving system, controlling row driving of a display array module based on a driving timing waveform, and controlling column driving of the display array module according to first matrix data and second matrix data.
The technical solutions in the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the present disclosure. It is to be understood that the described embodiments are merely a subset of the disclosed embodiments and not all embodiments. The components of the present disclosure, as generally described and illustrated in the figures herein, may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the present disclosure, presented in the figures, is not intended to limit the scope of the claimed disclosure, but is merely representative of selected embodiments of the disclosure. All other embodiments, which can be derived by a person skilled in the art from the embodiments of the disclosure without making creative efforts, shall fall within the protection scope of the disclosure.
It should be noted that: like reference numbers and letters refer to like items in the following figures, and thus, once an item is defined in one figure, it need not be further defined and explained in subsequent figures.
Referring to fig. 1, the present disclosure provides a multi-line addressing driving system for driving a display array module. The display array module can be an organic light emitting diode pixel array. The multi-line addressing driving system comprises: memory 110, processor 120, timing controller 130, row driver 140, and column driver 150.
The memory 110 is used for storing at least one frame of image data. The image data is original image data to be displayed.
The processor 120 is configured to read one frame of image data from the memory 110, obtain a corresponding driving timing waveform generating instruction based on a set scanning driving manner, send the driving timing waveform generating instruction to the timing controller 130, perform a first operation and block cutting on t rows of data in the read image data to obtain first matrix data, and perform a second operation and block cutting on t rows of data in the read image data to obtain second matrix data. Wherein t is 2 or more.
For example, assuming that the preset scan driving method is a 4-line M L a + S L a scan driving method, the processor 120 reads data of 4 × 1a at a time and calculates to obtain M L a and S L a matrices, and if the preset scan driving method is a 3-line M L a + S L a scan driving method, the processor 120 reads data of 3 × 1a at a time and calculates to obtain M L a and S L a matrices, and so on.
In the present disclosure, the first matrix data may be Multi-line Addressing (M L a) matrix data, and the second matrix data may be Single-line Addressing (S L a) matrix data.
Optionally, the processor 120 is configured to perform a first operation and block the t rows of data in the read image data to obtain first matrix data by blocking the t rows of data in the read image data according to the blocks of t × 1, calculating minimum values of colors in each block of t × 1, and forming the first matrix data by all the calculated minimum values.
Optionally, the processor 120 is configured to perform a second operation and block cutting on t rows of data in the read image data to obtain second matrix data, where the t rows of data in the read image data are subjected to gamma forward transformation, the t rows of data subjected to gamma forward transformation are subjected to block cutting according to t × 1 blocks, a minimum value of a color in each t × 1 block is calculated, the minimum value of each color is subtracted from each t × 1 block to obtain transition matrix data, and the transition matrix data are subjected to gamma inverse transformation to obtain second matrix data.
Accordingly, when the image data is gray scale image data, the minimum value of the gray scale values in the block of t × 1 is calculated, and when the image data is color image data, the minimum values of the R (red) component, the G (green) component, and the B (blue) in the block of t × 1 are calculated.
The timing controller 130 is configured to generate a corresponding driving timing waveform according to the driving timing waveform generating instruction. The row driver 140 is used for controlling the row driving of the display array module based on the driving timing waveform.
The column driver 150 is configured to control column driving of the display array module according to the first matrix data and the second matrix data.
Referring to fig. 2, in order to ensure the display effect, the multi-line addressing driving system optionally further includes a corrector 160, where the corrector 160 is configured to perform gamma correction on the first matrix data and the second matrix data, respectively. Correspondingly, the column driver 150 is configured to control column driving of the display array module according to the first matrix data and the second matrix data after gamma correction.
Taking the first matrix data as M L A matrix data and the second matrix data as S L A matrix data as an example, the scanning driving mode is M L A + S L A, if the current scanning driving mode is M L A, the gamma-corrected M L A matrix data of the corresponding column is correspondingly sent to each column, and if the current scanning driving mode is S L A, the gamma-corrected S L A matrix data of the corresponding column is correspondingly sent to each column.
The Multi-line Addressing (Multi L ine Addressing) driving system provided by the present disclosure is used for driving a display array module, such as a matrix display array, and is suitable for storing image data into a memory 110 by a PMO L ED., obtaining a corresponding driving timing waveform generating instruction by a processor 120 according to a preset scanning driving mode, and sending the instruction to a timing controller 130. the image data is decomposed into an M L a matrix and an S L a matrix by an algorithm, then the M L a matrix and the S L a matrix are gamma corrected, and then the gamma corrected M L a matrix data and the S L a matrix data are used for driving the display array module in a combined scanning mode.
The image data of one frame read by the processor 120 may include data of more than t lines, and in this case, in order to realize the full display of the image data of one frame, the image data of the frame needs to be read and processed multiple times. Correspondingly, the processor 120 is further configured to determine whether all the read image data are completely read, and if all the read image data are not completely read, continue to read another t rows of data in the image data, generate a corresponding driving timing waveform generation instruction and send the driving timing waveform generation instruction to the timing controller 130, and perform operation and block cutting on the another t rows of data to obtain new first matrix data and second matrix data. Until the whole reading and displaying of one frame of image data is realized.
Through the arrangement, the display array module is driven by the row driver 140 and the column driver 150, so that final image content is displayed, the defects of the traditional line-by-line single-line scanning are overcome, the service life of O L ED is prolonged, the power consumption is reduced, and the resolution is improved.
Referring to fig. 3, in order to more clearly illustrate the multi-line addressing system of the present disclosure, the multi-line addressing system of the present disclosure is illustrated by the structure shown in fig. 3.
In the present disclosure, a multi-line addressing driving system may include a memory 110, a processor 120, a timing controller 130, a row driver 140, and a column driver 150, the processor 120 is coupled to the timing controller 130 and the column driver 150, respectively, the timing controller 130 is coupled to the row driver 140, and the elements are electrically connected, directly or indirectly, to enable data transmission or interaction, for example, the elements may be electrically connected via one or more communication or signal buses, the column driver 150 and the row driver 140 are further coupled to a display array module 200 including an O L ED pixel array to drive each pixel of the display array module 200 to be illuminated, the display array module 200 includes N and M columns of O L ED pixel arrangements.
The memory 110 is used to store one frame of image data.
The Memory 110 may include, but is not limited to, a Random Access Memory (RAM), a Read Only Memory (ROM), a Programmable Read Only Memory (PROM), an Erasable Read Only Memory (EPROM), an electrically Erasable Read Only Memory (EEPROM), and the like.
The processor 120 is configured to read image data from the memory 110, block t-line data in the read image data according to blocks (blocks) of t × 1, and calculate a minimum value of a color in each block of t × 1, so as to obtain an M L a matrix.
The processor 120 performs gamma forward transformation on t line data in the read image data, converts original image data into a linear space, blocks the gamma forward transformed image data according to t × 1, calculates the minimum value of colors in each t × 1 block, correspondingly subtracts the minimum value of the colors in each t × block from each t × 1 block which is subjected to gamma forward transformation to obtain an S L A transition matrix, and performs gamma inverse transformation on the S L A transition matrix to obtain an S L A matrix.
The processor 120 respectively performs gamma correction on the obtained M L A matrix and the S L A matrix to obtain final M L A matrix data and S L A matrix data, performs scanning driving on the obtained M L A matrix data and S L A matrix data in a combined scanning mode, judges whether scanning of one frame of image is finished, if the scanning is not finished, continues to read other t rows of data, and if the scanning is finished, displays the one frame of image.
The processor 120 may be an integrated circuit chip having signal processing capabilities. The processor 120 may be a general-purpose processor, and includes a Central Processing Unit (CPU), a Network Processor (NP), and the like; but may also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), an off-the-shelf programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components. Which may implement or perform the methods, steps, and logic blocks disclosed in the embodiments of the present application. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like.
The timing controller 130 is configured to generate a driving timing waveform corresponding to a scanning driving manner after receiving the driving timing waveform generation instruction, and control the row driver 140 to perform driving scanning based on the driving timing waveform, so that the row driver 140 controls the row driving of the display array module 200.
The column driver 150 is used for controlling the column driving of the display array module 200 according to the gamma corrected M L A matrix data and S L A matrix data.
The display array module 200 is driven by the row driver 140 and the column driver 150 to display image content.
It will be appreciated that the configuration shown in figure 3 is merely illustrative and that the multi-line addressing driving system may also include more or fewer components than shown in figure 3 or have a different configuration than that shown in figure 3 the components shown in figure 3 may be implemented in hardware, software or a combination thereof for example the multi-line addressing driving system may further comprise an M L a matrix data memory and an S L a matrix data memory, the M L a matrix data memory being arranged to store M L a matrix data calculated by the processor 120 and the S L a matrix data memory being arranged to store S L a matrix data calculated by the processor 120.
Referring to fig. 4, the present disclosure provides a multi-line addressing driving method applied to the processor 120 in the multi-line addressing driving system shown in fig. 1 to 3 to drive the display array module 200. The multi-line addressing driving system includes a memory 110, a timing controller 130, a row driver 140, a column driver 150, and the processor 120. The method comprises the following steps.
In step S11, one frame of image data is read from the memory 110.
In step S12, a corresponding driving timing waveform generation command is obtained based on the set scanning driving manner and sent to the timing controller 130 to generate a corresponding driving timing waveform, so that the row driver 140 controls the row driving of the display array module 200 based on the driving timing waveform, where t is greater than or equal to 2.
Step S13, performing a first operation and a block cutting on t rows of data in the read image data to obtain first matrix data, and performing a second operation and a block cutting on t rows of data in the read image data to obtain second matrix data, so that the column driver 150 controls the column driving of the display array module 200 according to the first matrix data and the second matrix data.
Referring to fig. 5, the step of performing a first operation and dicing on t rows of data in the read image data to obtain a first matrix data includes the following steps.
In step S131, the t line data in the read image data is diced into blocks of t × 1.
Step S132, calculate the minimum value of the color in each block of t × 1, and obtain the first matrix data.
Referring to fig. 6, the step of performing a second operation and dicing on t rows of data in the read image data to obtain second matrix data includes the following steps.
In step S133, gamma forward conversion is performed on t line data in the read image data.
In step S134, the t line data subjected to gamma forward conversion is diced into t × 1 blocks, and the minimum value of the color in each t × 1 block is calculated.
In step S135, the minimum color value is subtracted from each block of t × 1 to obtain transition matrix data.
And step S136, performing gamma inverse transformation on the transition matrix data to obtain second matrix data.
Optionally, the method further comprises: and judging whether all the read image data are read or not, if not, continuing to read other t rows of data in the image data, generating a corresponding driving time sequence waveform generating instruction and sending the instruction to the time sequence controller 130, and operating and cutting the other t rows of data to obtain new first matrix data and second matrix data.
The implementation principle of the multi-line addressing driving method provided in the present disclosure is similar to that of the multi-line addressing driving system, and the related contents can be referred to the description in the multi-line addressing driving system, and therefore, the details are not described herein.
Please refer to fig. 7, which is a diagram illustrating a conventional scanning method. The traditional scanning mode is as follows: scanning a line, sending corresponding image data by all columns, scanning in sequence, and sending corresponding data by the columns each time one line is scanned until all the lines are scanned.
L T is the time for scanning a line in the conventional scanning mode, and is calculated as follows:
where FR is the frame rate and M is the total number of rows in the display array.
FIG. 8 is a schematic diagram of a first M L A scan mode, which is a scan mode in which M L A and S L A are scanned separately, and the scan mode of FIG. 8 is that each time 4 rows of M L A are scanned, M L A is scanned for 4 rows until all rows are scanned, and then S L A single-row scanning is performed until all rows are scanned for S L A.
FIG. 9 shows an interlaced scan of two lines M L A + S L A, three lines M L A + S L A, and four lines M L A + S L A. the scan of FIG. 9 is performed by scanning 4 lines M L A, then 4 lines S L A, then 4 lines M L A, and then 4 lines S L A until all lines have been interlaced.
It should be understood that the above description is by way of example only, and the scope of the disclosure is not limited to two, three, and four wires, and that any split scan pattern of the wires M L a + S L a is within the scope of the disclosure.
Taking the four-line M L a + S L a split scan as an example, the details are as follows:
and simultaneously scanning four rows, sending M L A data in columns, continuing to scan the four rows, sending M L A data in columns, continuing to scan the four rows until all rows are scanned by M L A, then scanning one row, sending S L A data in columns, continuing to scan one row, sending S L A data in columns, continuing to scan one row until all rows are scanned by S L A, and finishing the scanning of the image.
Fig. 9 is a diagram of a second scanning mode M L a, which is a scanning mode of M L a and S L a interlaced scanning mode.
The schematic diagram of fig. 9 illustrates an interleaved scanning pattern of two lines M L a + S L a, three lines M L a + S L a, and four lines M L a + S L a, respectively.
Taking the four-line M L A + S L A interlaced scanning manner as an example, the details are as follows:
and simultaneously scanning four rows, carrying out column feeding on M L A data, scanning the first row in the four rows, carrying out column feeding on S L A data, scanning the second row in the four rows, carrying out column feeding on S L A data, scanning the third row in the four rows, carrying out column feeding on S L A data, scanning the fourth row in the four rows, carrying out column feeding on S L A data, completing the staggered scanning of M L A and S L A of the four rows, continuing to scan the next four rows, and sequentially circulating until all the rows are scanned, and completing the scanning of the original image.
FIG. 10 is a schematic diagram of time-proportional gears of four lines M L A and S L A. different O L0 ED display array modules have different luminous efficiencies and display characteristics, and in order to make full use of the advantages of M L1A, the present disclosure designs the time ratios of the shiftable gears for M L A and S L A. in addition, the gears related to the present disclosure do not only include the gears shown in FIG. 10, and any gear of the time ratios of M L A and S L A falls within the scope of the present disclosure, and in addition, FIG. 10 is a schematic diagram of time gears of four lines M L A + S L A, and any other time gears of M L A + S L A fall within the scope of the present disclosure.
The multi-line addressing driving system and the multi-line addressing driving method have the advantages that the multi-line addressing driving system is ingeniously designed and integrated, the row driving of the display array module is controlled based on the driving time sequence waveform, the column driving of the display array module is controlled according to the first matrix data and the second matrix data, the multi-line driving mode effectively overcomes the defects of the traditional line-by-line single line scanning driving mode, the reliable driving of the display array module is achieved, the service life of the display array module can be effectively prolonged, the power consumption is reduced, and the resolution ratio is improved.
In the description of the present disclosure, it is to be noted that the terms "disposed," "connected," and "connected" are to be construed broadly and may be, for example, fixedly connected, detachably connected, or integrally connected unless otherwise explicitly stated or limited. Either mechanically or electrically. They may be connected directly or indirectly through intervening media, or they may be interconnected between two elements. The specific meaning of the above terms in the present disclosure can be understood in specific instances by those of ordinary skill in the art.
In the description of the present disclosure, it should be further noted that the terms "upper", "lower", "inner", "outer", and the like indicate orientations or positional relationships based on orientations or positional relationships shown in the drawings or orientations or positional relationships conventionally found to be used with the products of the present disclosure, and are used for convenience in describing and simplifying the present disclosure, but do not indicate or imply that the devices or elements referred to must have a specific orientation, be constructed in a specific orientation, and be operated, and thus should not be construed as limiting the present disclosure. Furthermore, the terms "first," "second," and the like are used merely to distinguish one description from another, and are not to be construed as indicating or implying relative importance.
The above description is only a preferred embodiment of the present disclosure and is not intended to limit the present disclosure, and various modifications and changes may be made to the present disclosure by those skilled in the art. Any modification, equivalent replacement, improvement and the like made within the spirit and principle of the present disclosure should be included in the protection scope of the present disclosure.
Claims (8)
1. A multi-line addressing driving system for driving a display array module, the multi-line addressing driving system comprising: the device comprises a memory, a processor, a time schedule controller, a row driver and a column driver;
the memory is used for storing at least one frame of image data;
the processor is used for reading one frame of image data from the memory, obtaining a corresponding driving time sequence waveform generating instruction based on a set scanning driving mode, sending the driving time sequence waveform generating instruction to the time sequence controller, carrying out first operation and block cutting on t rows of data in the read image data to obtain first matrix data, carrying out second operation and block cutting on t rows of data in the read image data to obtain second matrix data, wherein t is more than or equal to 2;
the time sequence controller is used for generating a corresponding driving time sequence waveform according to the driving time sequence waveform generating instruction;
the row driver is used for controlling row driving of the display array module based on the driving time sequence waveform;
the column driver is used for controlling the column driving of the display array module according to the first matrix data and the second matrix data; the processor is used for performing first operation and block cutting on t-row data in the read image data in the following mode to obtain first matrix data:
dicing t-line data in the read image data according to a block of t × 1;
the minimum value of the color in each tile of t × 1 is calculated, and the first matrix data is formed from all the calculated minimum values.
2. The system of claim 1, wherein the processor is configured to perform a second operation and block t rows of data in the read image data to obtain second matrix data by:
performing gamma positive transformation on t rows of data in the read image data;
slicing the t-row data subjected to gamma forward transformation according to the blocks of t × 1, and calculating the minimum value of colors in each block of t × 1;
subtracting the minimum value of each color from each block of t × 1 to obtain transition matrix data;
and performing gamma inverse transformation on the transition matrix data to obtain second matrix data.
3. The multi-line addressing driving system according to any of claims 1-2, further comprising a corrector for gamma correction of the first and second matrix data, respectively;
and the column driver is used for controlling the column driving of the display array module according to the first matrix data and the second matrix data after gamma correction.
4. The system of claim 1, wherein the processor is further configured to determine whether all of the read image data has been completely read, and if not, continue to read t additional rows of data in the image data, generate a corresponding driving timing waveform generating instruction and send the driving timing waveform generating instruction to the timing controller, and perform operation and block cutting on the t additional rows of data to obtain new first matrix data and second matrix data.
5. The multi-line addressing driving system of claim 1, wherein the driving display array module is an organic light emitting diode pixel array.
6. A multi-line addressing driving method is characterized in that the method is applied to a processor in a multi-line addressing driving system to drive a display array module, wherein the multi-line addressing driving system comprises a memory, a time schedule controller, a row driver, a column driver and the processor; the method comprises the following steps:
reading a frame of image data from the memory;
obtaining a corresponding driving time sequence waveform generating instruction based on a set scanning driving mode and sending the corresponding driving time sequence waveform to the time sequence controller so as to generate a corresponding driving time sequence waveform, so that the row driver controls the row driving of the display array module based on the driving time sequence waveform, wherein t is more than or equal to 2;
performing first operation and block cutting on t rows of data in the read image data to obtain first matrix data, performing second operation and block cutting on t rows of data in the read image data to obtain second matrix data, and enabling the column driver to control column driving of the display array module according to the first matrix data and the second matrix data; performing first operation and dicing on t-line data in the read image data to obtain first matrix data, including:
dicing t-line data in the read image data according to a block of t × 1;
the minimum value of the colors in each tile of t × 1 is calculated, resulting in first matrix data.
7. The multiline addressing method of claim 6, wherein the step of performing a second operation and dicing on t lines of data in the read image data to obtain second matrix data includes:
performing gamma positive transformation on t rows of data in the read image data;
slicing the t-row data subjected to gamma forward transformation according to the blocks of t × 1, and calculating the minimum value of colors in each block of t × 1;
subtracting the minimum value of each color from each block of t × 1 to obtain transition matrix data;
and performing gamma inverse transformation on the transition matrix data to obtain second matrix data.
8. The multi-line address driving method of claim 6, further comprising:
and judging whether all the read image data are read or not, if not, continuing to read other t rows of data in the image data, generating a corresponding driving time sequence waveform generating instruction and sending the instruction to the time sequence controller, and operating and cutting the other t rows of data to obtain new first matrix data and second matrix data.
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