CN109005561B - Signal compression method and device - Google Patents
Signal compression method and device Download PDFInfo
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- CN109005561B CN109005561B CN201710423939.2A CN201710423939A CN109005561B CN 109005561 B CN109005561 B CN 109005561B CN 201710423939 A CN201710423939 A CN 201710423939A CN 109005561 B CN109005561 B CN 109005561B
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Abstract
The invention relates to the field of mobile communication, in particular to a signal compression method and a device, aiming at solving the problems of high processing time delay and large compression loss in the existing signal compression method, the method comprises the steps of determining the whole shift length based on the respective leading symbol bits of a first I signal and a first Q signal contained in an initial IQ signal, respectively carrying out shift processing on the first I signal and the first Q signal based on the whole shift length to obtain a second I signal and a second Q signal, respectively carrying out bit truncation processing on the second I signal and the second Q signal according to the preset bit width to obtain a third I signal and a third Q signal, and generating a target IQ signal based on the third I signal and the third Q signal, thus, additional AGC processing is not needed to be added, the time delay is greatly reduced, and the signal fidelity is higher because part of IQ signals of bit segments are completely reserved, the compression loss is greatly reduced.
Description
Technical Field
The present invention relates to the field of mobile communications, and in particular, to a signal compression method and apparatus.
Background
Time Division long Term Evolution (Time Division L ong Term Evolution, TD-L TE) systems and 5G systems pursue high-speed and high-capacity data transmission, and in L TE systems and 5G systems, data transmission is usually realized by a base station, wherein a Baseband Unit (BBU) and a Radio Remote Unit (RRU) in an indoor environment respectively undertake Baseband processing and Radio frequency processing functions of the base station, an optical fiber is used between the BBU and the RRU for data transmission, and the optical fiber is mainly used for transmitting operation maintenance data and IQ signals, and interfaces at two ends are called IR interfaces.
In order to achieve reliable and efficient transmission of large data volume with limited bandwidth, compression method is usually adopted to compress the IQ signal transmitted between the IR interface of the RRU and the IR interface of the BBU.
Specifically, in a conventional IQ signal compression method, at a sending end, first, an Automatic Gain Control (AGC) process is performed on an IQ signal transmitted between an IR interface of a BBU and an IR interface of an RRU, where the AGC process refers to amplitude modulation of an amplitude of an IQ signal to be compressed, and adjusting the amplitude to an expected target value for subsequent compression; and then, compressing the IQ signal after the AGC processing by adopting an A-law compression algorithm or a similar A-law compression algorithm. For the receiving end, decompression processing operation and de-AGC processing operation corresponding to the transmitting end are performed on the received IQ signal.
However, the conventional IQ signal compression method is complex in implementation steps, and needs AGC processing before IQ signal compression, which increases processing delay, and further, an a-law compression algorithm is used to compress the IQ signal after AGC processing, so that Error Vector Magnitude (EVM) is about 2%, and obviously, compression loss is relatively large.
In view of the above, a signal compression method needs to be redesigned to overcome the above-mentioned drawbacks.
Disclosure of Invention
The embodiment of the invention provides a signal compression method and a signal compression device, which are used for solving the problems of high processing time delay and large compression loss in the conventional signal compression method.
The embodiment of the invention provides the following specific technical scheme:
a method of signal compression, comprising:
acquiring an initial IQ signal, and determining the whole shift length of the initial IQ signal based on the respective corresponding leading symbol bits of a first I signal and a first Q signal contained in the initial IQ signal;
respectively carrying out shift processing on the first I signal and the first Q signal based on the whole shift length to obtain a second I signal and a second Q signal;
according to a preset bit width, performing bit truncation processing on the second I signal and the second Q signal respectively to obtain a third I signal and a third Q signal;
generating a target IQ signal based on the third I signal and the third Q signal.
Optionally, determining an overall shift length of the initial IQ signal based on the number of pilot symbol bits corresponding to each of the first I signal and the first Q signal included in the initial IQ signal includes:
determining a first leading symbol bit number contained in the first I signal;
determining a second preamble symbol bit number contained in the first Q signal;
comparing the first preamble symbol bit number with the second preamble symbol bit number, determining the smaller one, and determining the overall shift length of the initial IQ signal based on the smaller one.
Optionally, based on the overall shift length, respectively performing shift processing on the first I signal and the first Q signal to obtain a second I signal and a second Q signal, including:
moving the first I signal to the left by a bit number according with the integral shift length to obtain a second I signal;
and moving the first Q signal to the left by a bit number consistent with the integral shift length to obtain a second Q signal.
Optionally, the truncating the second I signal and the second Q signal according to a preset bit width to obtain a third I signal and a third Q signal respectively includes:
determining the residual transmission bit width based on the current transmission bit width and a preset control bit width;
determining a bit width occupied by the second I signal and a bit width occupied by the second Q signal based on the remaining transmission bit width;
based on the bit width occupied by the second I signal, carrying out bit truncation processing on the second I signal to obtain a third I signal;
and performing bit truncation processing on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
Optionally, performing bit truncation processing on the second I signal based on the bit width occupied by the second I signal to obtain a third I signal, including:
intercepting the bit number corresponding to the bit width occupied by the second I signal by taking the highest bit of the second I signal as a starting point;
when the value of the highest bit of the non-intercepted part in the second I signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second I signal, and the obtained carry result is not overflowed, the carry result is used as a third I signal; otherwise, directly taking the intercepted part of the second I signal as a third I signal;
based on the bit width occupied by the second Q signal, performing bit truncation processing on the second Q signal to obtain a third Q signal, including:
intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point to obtain a third Q signal;
when the value of the highest bit of the non-intercepted part in the second Q signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second Q signal, and the obtained carry result is not overflowed, the carry result is used as a third Q signal; otherwise, directly taking the intercepted part of the second Q signal as a third Q signal.
Optionally, generating a target IQ signal based on the third I signal and the third Q signal includes:
determining a signal bit based on the third I signal and the third Q signal, wherein a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal;
determining a control bit based on the preset control bit width, wherein the control bit is used for transmitting control information carried by a target IQ signal;
and generating a target IQ signal based on the signal bit and the control bit.
A signal compression apparatus comprising:
a processing unit, configured to acquire an initial IQ signal, and determine an overall shift length of the initial IQ signal based on a preamble symbol bit number corresponding to each of a first I signal and a first Q signal included in the initial IQ signal;
a shifting unit, configured to perform shifting processing on the first I signal and the first Q signal respectively based on the entire shift length to obtain a second I signal and a second Q signal;
the bit cutting unit is used for respectively performing bit cutting processing on the second I signal and the second Q signal according to a preset bit width to obtain a third I signal and a third Q signal;
a generating unit for generating a target IQ signal based on the third I signal and the third Q signal.
Optionally, when determining the overall shift length of the initial IQ signal based on the preamble symbol bits corresponding to the first I signal and the first Q signal included in the initial IQ signal, the processing unit is configured to:
determining a first leading symbol bit number contained in the first I signal;
determining a second preamble symbol bit number contained in the first Q signal;
comparing the first preamble symbol bit number with the second preamble symbol bit number, determining the smaller one, and determining the overall shift length of the initial IQ signal based on the smaller one.
Optionally, when the first I signal and the first Q signal are respectively shifted based on the entire shift length to obtain a second I signal and a second Q signal, the shifting unit is configured to:
moving the first I signal to the left by a bit number according with the integral shift length to obtain a second I signal;
and moving the first Q signal to the left by a bit number consistent with the integral shift length to obtain a second Q signal.
Optionally, when the bit-cutting processing is performed on the second I signal and the second Q signal respectively according to a preset bit width to obtain a third I signal and a third Q signal, the bit-cutting unit is configured to:
determining the residual transmission bit width based on the current transmission bit width and a preset control bit width;
determining a bit width occupied by the second I signal and a bit width occupied by the second Q signal based on the remaining transmission bit width;
based on the bit width occupied by the second I signal, carrying out bit truncation processing on the second I signal to obtain a third I signal;
and performing bit truncation processing on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
Optionally, when performing bit truncation processing on the second I signal based on the bit width occupied by the second I signal to obtain a third I signal, the bit truncation unit is configured to:
intercepting the bit number corresponding to the bit width occupied by the second I signal by taking the highest bit of the second I signal as a starting point;
when the value of the highest bit of the non-intercepted part in the second I signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second I signal, and the obtained carry result is not overflowed, the carry result is used as a third I signal; otherwise, directly taking the intercepted part of the second I signal as a third I signal;
based on the bit width occupied by the second Q signal, performing bit truncation processing on the second Q signal to obtain a third Q signal, where the bit truncation unit is configured to:
intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point to obtain a third Q signal;
when the value of the highest bit of the non-intercepted part in the second Q signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second Q signal, and the obtained carry result is not overflowed, the carry result is used as a third Q signal; otherwise, directly taking the intercepted part of the second Q signal as a third Q signal.
Optionally, when generating the target IQ signal based on the third I signal and the third Q signal, the generating unit is configured to:
determining a signal bit based on the third I signal and the third Q signal, wherein a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal;
determining a control bit based on the preset control bit width, wherein the control bit is used for transmitting control information carried by a target IQ signal;
and generating a target IQ signal based on the signal bit and the control bit.
In the embodiment of the invention, the overall shift length is determined based on the respective leading symbol bits of the first I signal and the first Q signal contained in the initial IQ signal, the first I signal and the first Q signal are respectively shifted based on the overall shift length to obtain the second I signal and the second Q signal, the second I signal and the second Q signal are respectively truncated according to the preset bit width to obtain the third I signal and the third Q signal, and the target IQ signal is generated based on the third I signal and the third Q signal, so that additional AGC processing is not required to be added, the time delay is greatly reduced, in addition, because the IQ signals of partial bit segments are completely reserved, the signal fidelity is higher, the compression loss is greatly reduced, meanwhile, because only the IQ signal processing is involved, the hardware structure of the system is not required to be changed, and therefore, the method can be compatible with the existing transmission system, the user experience is greatly improved.
Drawings
FIG. 1 is a flow chart of a signal compression method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of an example second I signal and an example second Q signal in an embodiment of the present invention;
FIG. 3 is a schematic diagram of an exemplary target IQ signal in an embodiment of the present invention;
fig. 4 is a schematic structural diagram of a signal compression device according to an embodiment of the present invention.
Detailed Description
In order to solve the problems of high processing delay and large compression loss in the conventional signal compression method, in an embodiment of the present invention, a signal compression method is newly designed, where the method includes obtaining an initial IQ signal, determining an overall shift length of the initial IQ signal based on a preamble symbol bit number corresponding to each of a first I signal and a first Q signal included in the initial IQ signal, then performing shift processing on the first I signal and the first Q signal respectively based on the overall shift length to obtain a second I signal and a second Q signal, performing truncation processing on the second I signal and the second Q signal respectively according to a preset bit width to obtain a third I signal and a third Q signal, and finally generating a target IQ signal based on the third I signal and the third Q signal.
The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
The scheme of the present invention will be described in detail by way of specific examples, but the present invention is not limited to the following examples.
Before describing the signal compression method, in the embodiment of the present invention, the signal compression method is directed to an IQ signal transmitted between an IR interface of an indoor Baseband Unit (BBU) and an IR interface of a Remote Radio Unit (RRU), where the IQ signal includes two paths of signals, one path of the IQ signal is an I signal, the other path of the IQ signal is a Q signal, and the I signal and the Q signal are in-phase and orthogonal.
Referring to fig. 1, in the embodiment of the present invention, the signal compression method has the following flow:
step 100: acquiring an initial IQ signal, and determining the overall shift length of the initial IQ signal based on the respective corresponding preamble symbol bits of a first I signal and a first Q signal contained in the initial IQ signal.
Specifically, an initial IQ signal to be compressed is obtained first, then, a first preamble symbol bit number in a first I signal included in the initial IQ signal is determined, a second preamble symbol bit number in a first Q signal included in the initial IQ signal is determined, after the first preamble symbol bit number and the second preamble symbol bit number are determined, the first preamble symbol bit number and the second preamble symbol bit number are compared, a smaller-valued party is determined, and an overall shift length of the initial IQ signal is determined based on the smaller-valued party.
Further, as to how to determine the overall shift length of the initial IQ signal based on the smaller one, in the embodiment of the present invention, the value obtained by subtracting the bit width from the leading symbol bit with the smaller value is determined as the overall shift length, so that the sign bit of the IQ signal is usually all 1 or all 0, if the leading symbol bit with the smaller value is completely taken as the overall shift length, no sign bit exists in the I signal or the Q signal corresponding to the leading symbol bit with the smaller value during the subsequent shift, and thus, for the receiving end, the compressed IQ signal is received and the original sign bit thereof cannot be recovered, so that a sign bit needs to be reserved for the I signal or the Q signal corresponding to the leading symbol bit with the smaller value, so as to facilitate the subsequent decompression and correctly recover the original sign bit thereof.
For example, assuming that the first I signal and the first Q signal in the initial IQ signal both occupy a bit width of 16 bits, if the first I signal is "0001011110100110", and the first Q signal is "1111011101110110", it is determined that the first preamble symbol of the first I signal is "000", and the second preamble symbol of the first Q signal is "1111", and further, it is determined that the first preamble symbol bit number of the first I signal is "3", the second preamble symbol bit number of the first Q signal is "4", obviously, the first preamble symbol bit number is less than the second preamble symbol bit number, and the value "2" obtained by subtracting one bit width from the first preamble symbol bit number "3" is taken as the entire shift length of the initial IQ signal.
Step 110: and respectively carrying out shift processing on the first I signal and the first Q signal based on the determined overall shift length to obtain a second I signal and a second Q signal.
Specifically, after the overall shift length of the initial IQ signal is determined, the first I signal and the first Q signal are shifted based on the determined overall shift length, the first I signal is shifted to the left by a number of bits corresponding to the overall shift length to obtain a second I signal, and the first Q signal is shifted to the left by a number of bits corresponding to the overall shift length to obtain a second Q signal.
For example, continuing with the above example, the overall shift length is "2" bit, shifting the first I signal "0001011110100110" by two bits to the left results in the second I signal "01011110100110", and shifting the first Q signal "1111011101110110" by two bits to the left results in the second Q signal "11011101110110".
Step 120: and according to a preset bit width, performing bit truncation processing on the second I signal and the second Q signal respectively to obtain a third I signal and a third Q signal.
Specifically, before the bit-truncation processing is performed on the second I signal and the second Q signal according to the preset bit width, the remaining transmission bit width is determined based on the current transmission bit width and the preset control bit width, and then the bit width occupied by the second I signal and the bit width occupied by the second Q signal are determined based on the remaining transmission bit width.
In the embodiment of the present invention, the preset control bit width is used for transmitting control information of the IQ signal, and preferably, the preset control bit width preferentially adopted in the present embodiment is "3 bit", based on different configuration scenarios of the compressed IQ signal, the preset control bit width can also be set to "2 bit", and the specific bit occupation of the preset control bit width is set, which is not limited in the present invention, but can be adjusted based on an actual configuration scenario.
For example, assume that the current transmission bit width is 15 bits, and assume that the preset control bit width is "3 bits", because the I signal and the Q signal in the IQ signal are usually present in pairs, the bit widths occupied by the I signal and the Q signal are the same, and further, it can be determined that the bit width occupied by the second I signal is "6 bits", and the bit width occupied by the Q signal is also "6 bits".
Further, after the bit width occupied by the second I signal is determined, bit truncation processing is performed on the second I signal based on the bit width occupied by the second I signal to obtain a third I signal, and bit truncation processing is performed on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
Furthermore, the most significant bit of the second I signal is taken as the starting point, the bit number corresponding to the bit width occupied by the second I signal is intercepted, when the value of the most significant bit of the non-intercepted part in the second I signal is judged to reach the set threshold value, the carry operation is executed on the least significant bit of the intercepted part of the second I signal, and the obtained carry result is not overflowed, the carry result is determined as the third I signal, otherwise, the intercepted part of the second I signal is directly taken as the third I signal.
And intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point, determining the carry result as a third Q signal when the value of the highest bit of the non-intercepted part of the second Q signal reaches a set threshold value and carrying out carry operation on the lowest bit of the intercepted part of the second Q signal, and if the obtained carry result does not overflow, directly taking the intercepted part of the second Q signal as the third Q signal.
Preferably, in the embodiment of the present invention, the threshold is set to be 1.
For example, as can be seen from the above example, the second I signal occupies a bit width of "6 bits", and the second Q signal occupies a bit width of "6 bits".
For the second I signal "01011110100110":
specifically, as shown in fig. 2, with the highest bit "1" of the second I signal as a starting point, 6 bits are intercepted, the intercepted part of the second I signal is "010111", the non-intercepted part of the second I signal is "10100110", the highest bit of the non-intercepted part is known to be "1", a set threshold value "1" is reached, and the determination is continued, if the carry operation is performed on the lowest bit of the intercepted part of the second I signal, whether the carry result overflows or not is determined, it is known that the operation is performed on the lowest bit "1" of "010111", the obtained carry result is "011000", and no overflow exists, so the carry result "011000" is used as the third I signal.
For the second Q signal "11011101110110":
specifically, as shown in fig. 2, with the highest bit "1" of the second Q signal as a starting point, 6 bits are intercepted, the intercepted portion of the second Q signal is "110111", the non-intercepted portion of the second Q signal is "110111", it is known that the highest bit of the non-intercepted portion is "0", and the highest bit does not reach the set threshold "1", so that the intercepted portion "110111" of the second I signal is directly used as the third Q signal.
Taking the second Q signal as an example, in the embodiment of the present invention, it is determined not to directly determine the truncated part of the second Q signal as the third Q signal, but to determine whether the value of the highest bit of the non-truncated part is the set threshold, considering in the rounding method, so that the difference between the retained part and the actual value is the smallest as possible, that is, the retained part can be as close to the actual value as possible, and the error caused by the truncation is reduced.
Step 130: based on the obtained third I signal and third Q signal, a target IQ signal is generated.
Specifically, first, a signal bit is determined based on a third I signal and a third Q signal, where a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal, then, a control bit is determined based on a preset control bit width, and finally, a target IQ signal is generated based on the determined signal bit and control bit.
For example, as can be seen from the above description, the third I signal is "011000", the third Q signal is "110111", and the signal bits are "011000" and "110111", wherein the bit width occupied by the signal bits is 12 bits, and the preset control bit width is "3 bits" as can be seen from the foregoing examples, and after the signal bits and the control bits are determined, the target IQ signal can be determined, as shown in fig. 3.
Of course, the combination order of the signal bit, the sign bit and the control bit is not limited to the one shown in fig. 3, and may be determined according to a format specified in an actual transmission protocol.
The signal compression process is specific to a transmitting end, and after receiving a compressed target IQ signal, an equivalent receiving end firstly determines a third I signal and a third Q signal included in the target IQ signal, then performs zero padding on the third I signal and the third Q signal respectively based on bit widths missing through bit truncation processing, and then performs a right shift operation on the third I signal and the third Q signal respectively after the zero padding based on an overall shift length, wherein in the process of the right shift, an original sign bit can be restored based on a value on a respectively reserved sign bit, thereby obtaining a decompressed initial IQ signal.
For example, continuing with the description of the target IQ signal "011000110111 XXX" obtained in the above example, the third I signal "011000" is determined first, and the third Q signal "110111" is determined, and since the bit width occupied by the non-truncated portion is 7 bits when the truncation process operation is performed, 8 0's are complemented after the third I signal "011000", which is equivalent to amplifying the third I signal by 28Multiplying, obtaining "01100000000000", and complementing 8 0's after the third Q signal "110111", which is equivalent to amplifying the third Q signal by 28Doubling to obtain "11011100000000";
and because the overall displacement length is '2 bit', and the value on the sign bit of a reserved bit in the third I signal '01100000000000' after zero paddingTo "0", shift 2bit to the right and complement "0" in the bit width shifted to the right, resulting in "0001100000000000", which is equivalent to reducing the third I signal after zero padding by 22In the same way, the third Q signal "11011100000000" after zero padding is shifted to the right by 2 bits, and since the value of the reserved sign bit is "1", the bit width shifted to the right is padded by "1", so as to obtain "1111011100000000", which is equivalent to that the third Q signal after zero padding is reduced by 2 bits2Further, a decompressed initial IQ signal is obtained, wherein the I signal is "0001100000000000" and the Q signal is "1111011100000000".
It can be seen from the foregoing embodiments that the present invention can achieve 1/2 compression of signals, and further, in combination with the prior art, 1/3 compression of signals and 1/4 compression of signals can be achieved on the basis of the embodiments of the present invention, and the specific configuration method is shown in table 1.
TABLE 1
Based on the above embodiments, referring to fig. 4, in an embodiment of the present invention, the signal compression apparatus at least includes a processing unit 40, a shifting unit 41, a truncating unit 42 and a generating unit 43, wherein,
a processing unit 40, configured to acquire an initial IQ signal, and determine an overall shift length of the initial IQ signal based on a preamble symbol bit number corresponding to each of a first I signal and a first Q signal included in the initial IQ signal;
a shifting unit 41, configured to perform shifting processing on the first I signal and the first Q signal respectively based on the entire shift length to obtain a second I signal and a second Q signal;
the bit truncating unit 42 is configured to perform bit truncating processing on the second I signal and the second Q signal respectively according to a preset bit width to obtain a third I signal and a third Q signal;
a generating unit 43, configured to generate a target IQ signal based on the third I signal and the third Q signal.
Optionally, when determining the overall shift length of the initial IQ signal based on the preamble symbol bits corresponding to the first I signal and the first Q signal included in the initial IQ signal, the processing unit 40 is configured to:
determining a first leading symbol bit number contained in the first I signal;
determining a second preamble symbol bit number contained in the first Q signal;
comparing the first preamble symbol bit number with the second preamble symbol bit number, determining the smaller one, and determining the overall shift length of the initial IQ signal based on the smaller one.
Optionally, when performing shift processing on the first I signal and the first Q signal respectively based on the entire shift length to obtain a second I signal and a second Q signal, the shift unit 41 is configured to:
moving the first I signal to the left by a bit number according with the integral shift length to obtain a second I signal;
and moving the first Q signal to the left by a bit number consistent with the integral shift length to obtain a second Q signal.
Optionally, when the bit-cutting processing is performed on the second I signal and the second Q signal respectively according to a preset bit width to obtain a third I signal and a third Q signal, the bit-cutting unit 42 is configured to:
determining the residual transmission bit width based on the current transmission bit width and a preset control bit width;
determining a bit width occupied by the second I signal and a bit width occupied by the second Q signal based on the remaining transmission bit width;
based on the bit width occupied by the second I signal, carrying out bit truncation processing on the second I signal to obtain a third I signal;
and performing bit truncation processing on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
Optionally, when performing truncation processing on the second I signal based on the bit width occupied by the second I signal to obtain a third I signal, the truncation unit 42 is configured to:
intercepting the bit number corresponding to the bit width occupied by the second I signal by taking the highest bit of the second I signal as a starting point;
when the value of the highest bit of the non-intercepted part in the second I signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second I signal, and the obtained carry result is not overflowed, the carry result is used as a third I signal; otherwise, directly taking the intercepted part of the second I signal as a third I signal;
based on the bit width occupied by the second Q signal, when performing bit truncation on the second Q signal to obtain a third Q signal, the bit truncation unit 42 is configured to:
intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point to obtain a third Q signal;
when the value of the highest bit of the non-intercepted part in the second Q signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second Q signal, and the obtained carry result is not overflowed, the carry result is used as a third Q signal; otherwise, directly taking the intercepted part of the second Q signal as a third Q signal.
Optionally, when generating the target IQ signal based on the third I signal and the third Q signal, the generating unit 43 is configured to:
determining a signal bit based on the third I signal and the third Q signal, wherein a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal;
determining a control bit based on the preset control bit width, wherein the control bit is used for transmitting control information carried by a target IQ signal;
and generating a target IQ signal based on the signal bit and the control bit.
In summary, in the embodiment of the present invention, an overall shift length is determined based on the respective preamble symbol bits of the first I signal and the first Q signal included in the initial IQ signal, the first I signal and the first Q signal are respectively shifted based on the overall shift length to obtain the second I signal and the second Q signal, the second I signal and the second Q signal are respectively truncated according to a preset bit width to obtain the third I signal and the third Q signal, and the target IQ signal is generated based on the third I signal and the third Q signal, so that an additional AGC process is not required to be added, and the compression loss is greatly reduced, and furthermore, because the IQ signal of a partial bit segment is completely retained, the signal fidelity is higher, and meanwhile, because only the process related to the IQ signal is involved, the hardware structure of the system does not need to be changed, so that the present transmission system can be compatible, the user experience is greatly improved.
As will be appreciated by one skilled in the art, embodiments of the present invention may be provided as a method, system, or computer program product. Accordingly, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, and the like) having computer-usable program code embodied therein.
The present invention is described with reference to flowchart illustrations and/or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each flow and/or block of the flow diagrams and/or block diagrams, and combinations of flows and/or blocks in the flow diagrams and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present invention have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including preferred embodiments and all such alterations and modifications as fall within the scope of the invention.
It will be apparent to those skilled in the art that various modifications and variations can be made in the embodiments of the present invention without departing from the spirit or scope of the embodiments of the invention. Thus, if such modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to encompass such modifications and variations.
Claims (12)
1. A method of signal compression, comprising:
acquiring an initial IQ signal, and determining the whole shift length of the initial IQ signal based on the respective corresponding leading symbol bits of a first I signal and a first Q signal contained in the initial IQ signal;
respectively carrying out shift processing on the first I signal and the first Q signal based on the whole shift length to obtain a second I signal and a second Q signal;
according to a preset bit width, performing bit truncation processing on the second I signal and the second Q signal respectively to obtain a third I signal and a third Q signal;
generating a target IQ signal based on the third I signal and the third Q signal.
2. The method of claim 1, wherein determining the overall shift length of the initial IQ signal based on the number of pilot symbol bits corresponding to each of a first I signal and a first Q signal included in the initial IQ signal comprises:
determining a first leading symbol bit number contained in the first I signal;
determining a second preamble symbol bit number contained in the first Q signal;
comparing the first preamble symbol bit number with the second preamble symbol bit number, determining the smaller one, and determining the overall shift length of the initial IQ signal based on the smaller one.
3. The method of claim 1, wherein shifting the first I signal and the first Q signal based on the overall shift length to obtain a second I signal and a second Q signal, respectively, comprises:
moving the first I signal to the left by a bit number according with the integral shift length to obtain a second I signal;
and moving the first Q signal to the left by a bit number consistent with the integral shift length to obtain a second Q signal.
4. The method according to claim 1, 2 or 3, wherein the truncating the second I signal and the second Q signal according to a preset bit width to obtain a third I signal and a third Q signal respectively comprises:
determining the residual transmission bit width based on the current transmission bit width and a preset control bit width;
determining a bit width occupied by the second I signal and a bit width occupied by the second Q signal based on the remaining transmission bit width;
based on the bit width occupied by the second I signal, carrying out bit truncation processing on the second I signal to obtain a third I signal;
and performing bit truncation processing on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
5. The method of claim 4, wherein truncating the second I signal based on the bit width occupied by the second I signal to obtain a third I signal comprises:
intercepting the bit number corresponding to the bit width occupied by the second I signal by taking the highest bit of the second I signal as a starting point;
when the value of the highest bit of the non-intercepted part in the second I signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second I signal, and the obtained carry result is not overflowed, the carry result is used as a third I signal; otherwise, directly taking the intercepted part of the second I signal as a third I signal;
based on the bit width occupied by the second Q signal, performing bit truncation processing on the second Q signal to obtain a third Q signal, including:
intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point to obtain a third Q signal;
when the value of the highest bit of the non-intercepted part in the second Q signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second Q signal, and the obtained carry result is not overflowed, the carry result is used as a third Q signal; otherwise, directly taking the intercepted part of the second Q signal as a third Q signal.
6. The method of claim 5, wherein generating a target IQ signal based on the third I signal and the third Q signal comprises:
determining a signal bit based on the third I signal and the third Q signal, wherein a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal;
determining a control bit based on the preset control bit width, wherein the control bit is used for transmitting control information carried by a target IQ signal;
and generating a target IQ signal based on the signal bit and the control bit.
7. A signal compression apparatus, comprising:
a processing unit, configured to acquire an initial IQ signal, and determine an overall shift length of the initial IQ signal based on a preamble symbol bit number corresponding to each of a first I signal and a first Q signal included in the initial IQ signal;
a shifting unit, configured to perform shifting processing on the first I signal and the first Q signal respectively based on the entire shift length to obtain a second I signal and a second Q signal;
the bit cutting unit is used for respectively performing bit cutting processing on the second I signal and the second Q signal according to a preset bit width to obtain a third I signal and a third Q signal;
a generating unit for generating a target IQ signal based on the third I signal and the third Q signal.
8. The apparatus as claimed in claim 7, wherein when determining the overall shift length of the initial IQ signal based on the number of pilot symbol bits corresponding to each of the first I signal and the first Q signal included in the initial IQ signal, the processing unit is configured to:
determining a first leading symbol bit number contained in the first I signal;
determining a second preamble symbol bit number contained in the first Q signal;
comparing the first preamble symbol bit number with the second preamble symbol bit number, determining the smaller one, and determining the overall shift length of the initial IQ signal based on the smaller one.
9. The apparatus of claim 7, wherein when the first I signal and the first Q signal are respectively shifted based on the overall shift length to obtain a second I signal and a second Q signal, the shifting unit is configured to:
moving the first I signal to the left by a bit number according with the integral shift length to obtain a second I signal;
and moving the first Q signal to the left by a bit number consistent with the integral shift length to obtain a second Q signal.
10. The apparatus according to claim 7, 8 or 9, wherein when performing truncation processing on the second I signal and the second Q signal according to a preset bit width to obtain a third I signal and a third Q signal, the truncation unit is configured to:
determining the residual transmission bit width based on the current transmission bit width and a preset control bit width;
determining a bit width occupied by the second I signal and a bit width occupied by the second Q signal based on the remaining transmission bit width;
based on the bit width occupied by the second I signal, carrying out bit truncation processing on the second I signal to obtain a third I signal;
and performing bit truncation processing on the second Q signal based on the bit width occupied by the second Q signal to obtain a third Q signal.
11. The apparatus according to claim 10, wherein when performing truncation processing on the second I signal based on a bit width occupied by the second I signal to obtain a third I signal, the truncation unit is configured to:
intercepting the bit number corresponding to the bit width occupied by the second I signal by taking the highest bit of the second I signal as a starting point;
when the value of the highest bit of the non-intercepted part in the second I signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second I signal, and the obtained carry result is not overflowed, the carry result is used as a third I signal; otherwise, directly taking the intercepted part of the second I signal as a third I signal;
based on the bit width occupied by the second Q signal, performing bit truncation processing on the second Q signal to obtain a third Q signal, where the bit truncation unit is configured to:
intercepting the bit number corresponding to the bit width occupied by the second Q signal by taking the highest bit of the second Q signal as a starting point to obtain a third Q signal;
when the value of the highest bit of the non-intercepted part in the second Q signal is judged to reach a set threshold value, carry operation is carried out on the lowest bit of the intercepted part in the second Q signal, and the obtained carry result is not overflowed, the carry result is used as a third Q signal; otherwise, directly taking the intercepted part of the second Q signal as a third Q signal.
12. The apparatus of claim 11, wherein, in generating a target IQ signal based on the third I signal and the third Q signal, the generating unit is to:
determining a signal bit based on the third I signal and the third Q signal, wherein a bit width occupied by the signal bit is a sum of a bit width occupied by the third I signal and a bit width occupied by the third Q signal;
determining a control bit based on the preset control bit width, wherein the control bit is used for transmitting control information carried by a target IQ signal;
and generating a target IQ signal based on the signal bit and the control bit.
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