CN109005561A - A kind of compression method and device - Google Patents
A kind of compression method and device Download PDFInfo
- Publication number
- CN109005561A CN109005561A CN201710423939.2A CN201710423939A CN109005561A CN 109005561 A CN109005561 A CN 109005561A CN 201710423939 A CN201710423939 A CN 201710423939A CN 109005561 A CN109005561 A CN 109005561A
- Authority
- CN
- China
- Prior art keywords
- signal
- bit wide
- processing
- digit
- occupies
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04W—WIRELESS COMMUNICATION NETWORKS
- H04W28/00—Network traffic management; Network resource management
- H04W28/02—Traffic management, e.g. flow control or congestion control
- H04W28/06—Optimizing the usage of the radio link, e.g. header compression, information sizing, discarding information
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Compression, Expansion, Code Conversion, And Decoders (AREA)
Abstract
The present invention relates to mobile communication fields, more particularly to a kind of compression method and device, to solve the problems, such as that processing delay height and compression loss are big in existing compression method, this method is, the respective leading symbol digit of the first I signal and the first Q signal for including based on initial I/Q signal, determine integral shift length, and it is based on integral shift length, shifting processing is carried out to the first I signal and the first Q signal respectively, obtain the second I signal and the second Q signal, and according to preset bit wide, processing is truncated to the second I signal and the second Q signal respectively, obtain third I signal and third Q signal, and it is based on third I signal and third Q signal, generate target I/Q signal, in this way, without increasing additional AGC processing, greatly reduce time delay, and, due to completely remaining the I of part position section Q signal, signal fidelity is higher, greatly reduces compression loss.
Description
Technical field
The present invention relates to mobile communication field more particularly to a kind of compression methods and device.
Background technique
Timesharing long term evolution (Time Division Long Term Evolution, TD-LTE) system and 5G system chase after
It asks the data of high-speed high capacity to transmit, in LTE system and 5G system, data transmission is usually realized by base station, wherein indoor
Base Band Unit equipment (Building Baseband Unit, BBU) and RF remote equipment (Remote Radio Unit, RRU)
The Base-Band Processing and radio frequency processing function for undertaking base station respectively, are carried out data transmission between BBU and RRU using optical fiber, main to use
It is known as IR interface in transmission operation maintenance data and I/Q signal, the interface at both ends.
In order to complete reliable effective transmission of big data quantity with limited bandwidth, it will usually compression method is used, to BBU
IR interface and RRU IR interface between the I/Q signal transmitted compressed.
Specifically, traditional I/Q signal compression method, in transmitting terminal, firstly, the IR interface of IR interface and RRU to BBU
Between the I/Q signal transmitted carry out automatic growth control (Automatic Gain Control, AGC) processing, so-called AGC processing,
Refer to and amplitude modulation is carried out to the amplitude of I/Q signal to be compressed, the set goal value is adjusted to, so as to subsequent compression；Then,
Restraining compression algorithm or class A rule compression algorithm using A, I/Q signal is compressed to having carried out AGC treated.It is right for receiving end
The I/Q signal received executes decompression operation reconciliation AGC processing operation corresponding with transmitting terminal.
However, not only realizing that step is complicated using traditional I/Q signal compression method, moreover, needing before I/Q signal compression
AGC processing is carried out, processing delay is increased, further, AGC treated I/Q signal is carried out using A rule compression algorithm
Compression, error vector magnitude (Error Vector Magnitude, EVM) is 2% or so, it is clear that compression loss is bigger
's.
In view of this, a kind of compression method need to be redesigned to overcome drawbacks described above.
Summary of the invention
The embodiment of the present invention provides a kind of compression method and device, to solve in existing compression method
Manage time delay height and the big problem of compression loss.
Specific technical solution provided in an embodiment of the present invention is as follows:
A kind of compression method, comprising:
Initial I/Q signal is obtained, and the first I signal for including based on the initial I/Q signal and the first Q signal respectively correspond to
Leading symbol digit, determine the integral shift length of the initial I/Q signal；
Based on the integral shift length, shifting processing is carried out to first I signal and first Q signal respectively,
Obtain the second I signal and the second Q signal；
According to preset bit wide, processing is truncated to second I signal and second Q signal respectively, obtains the
Three I signals and third Q signal；
Based on the third I signal and the third Q signal, target I/Q signal is generated.
Optionally, the first I signal and the corresponding leading symbol of the first Q signal for including based on the initial I/Q signal
Digit determines the integral shift length of the initial I/Q signal, comprising:
Determine the first leading symbol digit that first I signal includes；
Determine the second leading symbol digit that first Q signal includes；
The first leading symbol digit and the second leading symbol digit are compared, determine value it is small one
Side, and a side small based on the value, determine the integral shift length of the initial I/Q signal.
Optionally, it is based on the integral shift length, first I signal and first Q signal are moved respectively
Position processing, obtains the second I signal and the second Q signal, comprising:
First I signal is moved to the left to the digit being consistent with the integral shift length, obtains the second I signal；
First Q signal is moved to the left to the digit being consistent with the integral shift length, obtains the second Q signal.
Optionally, according to preset bit wide, processing is truncated to second I signal and second Q signal respectively,
Obtain third I signal and third Q signal, comprising:
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined；
Based on the residue transmission bit wide, determine what the bit wide of the second I signal occupancy and second Q signal occupied
Bit wide；
Based on the bit wide that second I signal occupies, processing is truncated to second I signal, obtains the 3rd I letter
Number；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains the 3rd Q letter
Number.
Optionally, the bit wide occupied based on second I signal is truncated processing to second I signal, acquisition the
Three I signals, comprising:
Using the highest order of second I signal as starting point, the position being consistent with the bit wide that second I signal occupies is intercepted
Number；
When the value for determining the highest order for not intercepting part in second I signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two I signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third I signal；Otherwise, part will have directly been intercepted in second I signal as third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains the 3rd Q letter
Number, comprising:
Using the highest order of second Q signal as starting point, the position being consistent with the bit wide that second Q signal occupies is intercepted
Number obtains third Q signal；
When the value for determining the highest order for not intercepting part in second Q signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two Q signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third Q signal；Otherwise, part will have directly been intercepted in second Q signal as third Q signal.
Optionally, it is based on the third I signal and the third Q signal, generates target I/Q signal, comprising:
Based on the third I signal and the third Q signal, signal position is determined, wherein the bit wide of the signal bit occupancy
The sum of the bit wide that the bit wide occupied for the third I signal and the third Q signal occupy；
Based on the default control bit wide, control bit is determined, wherein the control bit is used for transmission the carrying of target I/Q signal
Control information；
Based on the signal position and the control bit, target I/Q signal is generated.
A kind of signal compression device, comprising:
Processing unit, for obtaining initial I/Q signal, and the first I signal and first for including based on the initial I/Q signal
The corresponding leading symbol digit of Q signal, determines the integral shift length of the initial I/Q signal；
Shift unit, for being based on the integral shift length, respectively to first I signal and first Q signal
Shifting processing is carried out, the second I signal and the second Q signal are obtained；
Cut position unit, for being cut to second I signal and second Q signal respectively according to preset bit wide
Position processing, obtains third I signal and third Q signal；
Generation unit generates target I/Q signal for being based on the third I signal and the third Q signal.
Optionally, the first I signal and the corresponding leading symbol of the first Q signal for including based on the initial I/Q signal
Digit, when determining the integral shift length of the initial I/Q signal, the processing unit is used for:
Determine the first leading symbol digit that first I signal includes；
Determine the second leading symbol digit that first Q signal includes；
The first leading symbol digit and the second leading symbol digit are compared, determine value it is small one
Side, and a side small based on the value, determine the integral shift length of the initial I/Q signal.
Optionally, it is based on the integral shift length, first I signal and first Q signal are moved respectively
Position processing, when obtaining the second I signal and the second Q signal, the shift unit is used for:
First I signal is moved to the left to the digit being consistent with the integral shift length, obtains the second I signal；
First Q signal is moved to the left to the digit being consistent with the integral shift length, obtains the second Q signal.
Optionally, according to preset bit wide, processing is truncated to second I signal and second Q signal respectively,
When obtaining third I signal and third Q signal, the cut position unit is used for:
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined；
Based on the residue transmission bit wide, determine what the bit wide of the second I signal occupancy and second Q signal occupied
Bit wide；
Based on the bit wide that second I signal occupies, processing is truncated to second I signal, obtains the 3rd I letter
Number；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains the 3rd Q letter
Number.
Optionally, the bit wide occupied based on second I signal is truncated processing to second I signal, acquisition the
When three I signals, the cut position unit is used for:
Using the highest order of second I signal as starting point, the position being consistent with the bit wide that second I signal occupies is intercepted
Number；
When the value for determining the highest order for not intercepting part in second I signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two I signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third I signal；Otherwise, part will have directly been intercepted in second I signal as third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains third Q signal
When, the cut position unit is used for:
Using the highest order of second Q signal as starting point, the position being consistent with the bit wide that second Q signal occupies is intercepted
Number obtains third Q signal；
When the value for determining the highest order for not intercepting part in second Q signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two Q signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third Q signal；Otherwise, part will have directly been intercepted in second Q signal as third Q signal.
Optionally, it is based on the third I signal and the third Q signal, when generating target I/Q signal, the generation unit
For:
Based on the third I signal and the third Q signal, signal position is determined, wherein the bit wide of the signal bit occupancy
The sum of the bit wide that the bit wide occupied for the third I signal and the third Q signal occupy；
Based on the default control bit wide, control bit is determined, wherein the control bit is used for transmission the carrying of target I/Q signal
Control information；
Based on the signal position and the control bit, target I/Q signal is generated.
It is respective leading by the first I signal and the first Q signal that include based on initial I/Q signal in the embodiment of the present invention
Symbol digit determines integral shift length, and is based on integral shift length, moves respectively to the first I signal and the first Q signal
Position processing, obtains the second I signal and the second Q signal, and according to preset bit wide, respectively to the second I signal and the second Q signal
It is truncated processing, obtains third I signal and third Q signal, and be based on third I signal and third Q signal, generates target IQ letter
Number, in this way, time delay is greatly reduced without increasing additional AGC processing, moreover, because completely remaining the IQ of part position section
Signal, signal fidelity is higher, greatly reduces compression loss, simultaneously as the processing of I/Q signal is pertained only to, without changing system
Uniting hardware configuration therefore can be compatible with the realization of existing Transmission system, substantially increases user experience.
Detailed description of the invention
Fig. 1 is compression method flow chart in the embodiment of the present invention；
Fig. 2 is the schematic diagram of the second Q signal of the second I signal of example and example in the embodiment of the present invention；
Fig. 3 is the schematic diagram of instance object I/Q signal in the embodiment of the present invention；
Fig. 4 is signal compression apparatus structure schematic diagram in the embodiment of the present invention.
Specific embodiment
To solve the problems, such as that processing delay height and compression loss are big in existing compression method, the embodiment of the present invention
In, a kind of compression method is redesigned, this method is to obtain initial I/Q signal, and include based on initial I/Q signal
First I signal and the corresponding leading symbol digit of the first Q signal, determine the integral shift length of initial I/Q signal, then,
Based on integral shift length, shifting processing is carried out to the first I signal and the first Q signal respectively, obtains the second I signal and the 2nd Q
Signal, and according to preset bit wide, processing is truncated to the second I signal and the second Q signal respectively, obtain third I signal
Target I/Q signal is generated finally, being based on third I signal and third Q signal with third Q signal.
Following will be combined with the drawings in the embodiments of the present invention, and technical solution in the embodiment of the present invention carries out clear, complete
Site preparation description, it is clear that described embodiments are only a part of the embodiments of the present invention, is not whole embodiments.It is based on
Embodiment in the present invention, it is obtained by those of ordinary skill in the art without making creative efforts every other
Embodiment shall fall within the protection scope of the present invention.
The solution of the present invention will be described in detail by specific embodiment below, certainly, the present invention is not limited to
Lower embodiment.
Before describing compression method, in the embodiment of the present invention, compression method is directed to indoor base band list
Element device (Building Baseband Unit, BBU) IR interface and RF remote equipment (Remote Radio Unit,
RRU the I/Q signal transmitted between IR interface), wherein I/Q signal includes two paths of signals, is I signal all the way, is Q signal all the way,
It is inphase quadrature between I signal and Q signal.
As shown in fig.1, compression method process is as follows in the embodiment of the present invention:
Step 100: obtaining initial I/Q signal, and the first I signal for including based on initial I/Q signal and the first Q signal are respectively
Corresponding leading symbol digit determines the integral shift length of initial I/Q signal.
Specifically, initial I/Q signal to be compressed is first obtained, then, it is determined that in the first I signal that initial I/Q signal includes
The first leading symbol digit, and determine the second leading symbol digit in the first Q signal that above-mentioned initial I/Q signal includes,
After determining the first leading symbol digit and the second leading symbol digit, to the first leading symbol digit and the second leading symbol position
Number is compared, and is determined the lesser side of value, and be based on the lesser side of value, is determined that the integral shift of initial I/Q signal is long
Degree.
Further, for how a side small based on value, determine the integral shift length of initial I/Q signal, the present invention
In embodiment, the small leading symbol digit of value is subtracted into the value that a bit wide obtains and is determined as integral shift length, in this way
It is because the sign bit of I/Q signal is usually all ones or all zeroes, if by completely moving the small leading symbol digit of value as a whole
Bit length will be not present sign bit in subsequent displacement in the value small corresponding I signal of leading symbol digit or Q signal, and
In this way, receiving the I/Q signal of compression for receiving end, its original symbol position can not be restored, therefore need to be before value is small
It leads the corresponding I signal of symbol digit or Q signal retains a bit sign position and can correctly restore its original symbol in order to subsequent decompression
Number position.
For example, it is assumed that the first I signal and the first Q signal in initial I/Q signal occupy the bit wide of 16bit, if the first I
Signal is " 0001011110100110 ", and the first Q signal is " 1111011101110110 ", then can determine above-mentioned first I signal
The first leading symbol be " 000 " and the second leading symbol of above-mentioned first Q signal is that " 1111 " determine the first I in turn
First leading symbol digit of signal is " 3 ", and the second leading symbol digit of the first Q signal is " 4 ", it is clear that the first leading character
Number digit is less than the second leading symbol digit, the first leading symbol digit " 3 " can be subtracted a bit wide, obtained value
The integral shift length of " 2 " as initial I/Q signal.
Step 110: based on determining integral shift length, the first I signal and the first Q signal being carried out at displacement respectively
Reason obtains the second I signal and the second Q signal.
Specifically, determining integral shift length is based respectively on, to the after determining the integral shift length of initial I/Q signal
One I signal and the first Q signal carry out shifting processing, and the first I signal is moved to the left to the position being consistent with above-mentioned integral shift length
Number obtains the second I signal, and the first Q signal is moved to the left to the digit being consistent with above-mentioned integral shift length, obtains second
Q signal.
For example, continuing to be illustrated with above-mentioned example, integral shift length is " 2 " bit, by the first I signal
" 0001011110100110 " is moved to the left two, obtains the second I signal " 01011110100110 ", and by the first Q signal
" 1111011101110110 " are moved to the left two, obtain the second Q signal " 11011101110110 ".
Step 120: according to preset bit wide, processing being truncated to the second I signal and the second Q signal respectively, obtains the
Three I signals and third Q signal.
Specifically, before being truncated processing to the second I signal and the second Q signal respectively according to preset bit wide, first
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined, then, be based on residue transmission bit wide, determine the
The bit wide that the bit wide and the second Q signal that two I signals occupy occupy.
In the embodiment of the present invention, default control bit wide is to be used for transmission the control information of I/Q signal, preferably, this implementation
The default control bit wide preferentially used is " 3bit ", the different configuration scenes based on compressed I/Q signal, moreover it is possible to by default control
Bit wide processed is set as " 2bit ", and default control bit wide specifically occupies how many bit, and the present invention does not limit, and can be based on reality
Configuration scene is adjusted.
For example, it is assumed that current transmission bit wide is 15bit, and assume that default control bit wide is " 3bit " due to usual I/Q signal
In I signal and Q signal occur in pairs, therefore, bit wide shared by I signal and Q signal be it is identical, in turn, it may be determined that
The bit wide that second I signal occupies is " 6bit ", and the bit wide that Q signal occupies also is " 6bit ".
Further, it is determined that, based on the bit wide that the second I signal occupies, believing the 2nd I after the bit wide that the second I signal occupies
It number is truncated processing, third I signal, and the bit wide occupied based on the second Q signal is obtained, the second Q signal is truncated
Processing obtains third Q signal.
Further, it using the highest order of the second I signal as starting point, intercepts the bit wide occupied with the second I signal and is consistent
Digit, when determining that the value of highest order for not intercepting part in the second I signal reaches given threshold, and to the second I signal
The lowest order for intercepting part executes carry operation, and when the carry result of acquisition is not spilt over, carry result is determined as the 3rd I letter
Number, otherwise, the second I signal is directly intercepted into part as third I signal.
And using the highest order of the second Q signal as starting point, the digit being consistent with the bit wide that the second Q signal occupies is intercepted,
When the value for determining the second Q signal highest order for not intercepting part reaches given threshold, and part is intercepted to the second Q signal
Lowest order executes carry operation, when the carry result of acquisition is not spilt over, carry result is determined as third Q signal, otherwise, directly
Part will have been intercepted in second Q signal as third Q signal.
Preferably, in the embodiment of the present invention, given threshold 1.
For example, the bit wide that the second Q signal occupies is by above-mentioned example it is found that the bit wide that the second I signal occupies is " 6bit "
“6bit”。
For the second I signal " 01011110100110 ":
Referring particularly to shown in Fig. 2, with the highest order " 1 " of the second I signal for starting point, 6bit is intercepted, obtains the second I signal
The part of interception be " 010111 ", obtain the second I signal do not intercept part be " 10100110 ", it is known that do not intercept part
The value of highest order is " 1 ", reaches given threshold " 1 ", continues to judge, if to the lowest order for having intercepted part of the second I signal
Execute carry operation, whether carry result overflow, it is known that, lowest order " 1 " execution of " 010111 " is operated, obtain into
Position result is " 011000 ", and there is no spillings, therefore, it regard above-mentioned carry result " 011000 " as third I signal.
For the second Q signal " 11011101110110 ":
Referring particularly to shown in Fig. 2, with the highest order " 1 " of the second Q signal for starting point, 6bit is intercepted, obtains the second Q signal
The part of interception be " 110111 ", obtain the second Q signal do not intercept part be " 110111 ", it is known that do not intercept part most
High-order value is " 0 ", not up to given threshold " 1 ", therefore directly by the part of interception " 110111 " of the second I signal as the
Three Q signals.
By taking the second Q signal as an example, in the embodiment of the present invention, why not by the interception part of the second Q signal, directly really
It is set to third Q signal, and is also to judgement and does not intercept whether the value of the highest order of part is given threshold, allows for four houses
Five enter in method, so that being retained the minimum as far as possible with the difference of actual value of part, that is, so that being retained part as far as possible can be close to reality
Actual value reduces bring error due to cut position processing.
Step 130: third I signal and third Q signal based on acquisition generate target I/Q signal.
Specifically, firstly, determining signal position, wherein the bit wide of signal bit occupancy based on third I signal and third Q signal
Then the sum of the bit wide that the bit wide and third Q signal occupied for third I signal occupies is based on default control bit wide, determine control
Position generates target I/Q signal finally, being based on fixed signal position and control bit.
For example, third Q signal is " 110111 " it can be seen from the above, third I signal is " 011000 ", it is known that, signal position is
" 011000 " and " 110111 ", wherein bit wide shared by signal position is 12bit, and the default control bit wide known to aforementioned exemplary is
" 3bit " after determining signal position and control bit, that is, can determine target I/Q signal, referring particularly to shown in Fig. 3.
Certainly, the built-up sequence of signal position, sign bit and control bit is not limited in one kind shown in Fig. 3, specifically can be according to
Factually depending on format specified in the transport protocol of border.
Above-mentioned signal compression process is for transmitting terminal, when the receiving end of equity, receives compressed target IQ letter
After number, firstly, determining third I signal and third Q signal that target I/Q signal includes, then, it is based respectively on to handle through cut position and grasps
Make the bit wide that lacks, in third I signal and third Q signal trailing zero, then, be based on integral shift length, respectively to zero padding after
Third I signal and third Q signal execute right shift operation, wherein, can be based on respectively retaining during right shift
Value on one bit sign position restores original symbol position, thus, the initial I/Q signal after being decompressed.
For example, continuing is that " 011000110111XXX " is illustrated with target I/Q signal obtained in above-mentioned example, first really
Determine third I signal " 011000 ", and determine third Q signal " 110111 ", due to not intercepting when executing cut position processing operation
The bit wide that part occupies is 7bit, therefore, in third I signal " 011000 " polishing 80 afterwards, it is equivalent to and is exaggerated third I signal
28Times, it obtains " 01100000000000 ", and mend 80 afterwards in third Q signal " 110111 ", is equivalent to third Q signal
It is exaggerated 28Times, obtain " 11011100000000 "；
Again because global displacement length is " 2bit ", and retain in the third I signal " 01100000000000 " after zero padding
Value on one bit sign position is " 0 ", right shift 2bit, and the benefit " 0 " in the bit wide to move right, is obtained
" 0001100000000000 " is equivalent to the third I signal after zero padding reducing 22Times, similarly, the 3rd Q after zero padding is believed
Number " 11011100000000 " right shift 2bit, the value on a bit sign position retained by it is " 1 ", therefore is being moved right
Bit wide on mend " 1 ", obtain " 1111011100000000 ", be equivalent to and the third Q signal after zero padding is reduced 22Times, into
And the initial I/Q signal after being decompressed, wherein I signal is " 0001100000000000 ", and Q signal is
“1111011100000000”。
As can be seen from the above embodiments, 1/2 compression of signal may be implemented in the present invention, and on the basis of the embodiment of the present invention
On, the prior art is further combined, 1/3 compression of signal and 1/4 compression of signal, concrete configuration method may be implemented
As shown in table 1.
Table 1
Based on the above embodiment, as shown in fig.4, in the embodiment of the present invention, it is single to include at least processing for signal compression device
Member 40, shift unit 41, cut position unit 42 and generation unit 43, wherein
Processing unit 40, for obtaining initial I/Q signal, and the first I signal and for including based on the initial I/Q signal
The corresponding leading symbol digit of one Q signal, determines the integral shift length of the initial I/Q signal；
Shift unit 41 respectively believes first I signal and the first Q for being based on the integral shift length
Number shifting processing is carried out, obtains the second I signal and the second Q signal；
Cut position unit 42, for being carried out to second I signal and second Q signal respectively according to preset bit wide
Cut position processing, obtains third I signal and third Q signal；
Generation unit 43 generates target I/Q signal for being based on the third I signal and the third Q signal.
Optionally, the first I signal and the corresponding leading symbol of the first Q signal for including based on the initial I/Q signal
Digit, when determining the integral shift length of the initial I/Q signal, the processing unit 40 is used for:
Determine the first leading symbol digit that first I signal includes；
Determine the second leading symbol digit that first Q signal includes；
The first leading symbol digit and the second leading symbol digit are compared, determine value it is small one
Side, and a side small based on the value, determine the integral shift length of the initial I/Q signal.
Optionally, it is based on the integral shift length, first I signal and first Q signal are moved respectively
Position processing, when obtaining the second I signal and the second Q signal, displacement Unit 41 are used for:
First I signal is moved to the left to the digit being consistent with the integral shift length, obtains the second I signal；
First Q signal is moved to the left to the digit being consistent with the integral shift length, obtains the second Q signal.
Optionally, according to preset bit wide, processing is truncated to second I signal and second Q signal respectively,
When obtaining third I signal and third Q signal, cut position Unit 42 is used for:
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined；
Based on the residue transmission bit wide, determine what the bit wide of the second I signal occupancy and second Q signal occupied
Bit wide；
Based on the bit wide that second I signal occupies, processing is truncated to second I signal, obtains the 3rd I letter
Number；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains the 3rd Q letter
Number.
Optionally, the bit wide occupied based on second I signal is truncated processing to second I signal, acquisition the
When three I signals, the cut position unit 42 is used for:
Using the highest order of second I signal as starting point, the position being consistent with the bit wide that second I signal occupies is intercepted
Number；
When the value for determining the highest order for not intercepting part in second I signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two I signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third I signal；Otherwise, part will have directly been intercepted in second I signal as third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains third Q signal
When, the cut position unit 42 is used for:
Using the highest order of second Q signal as starting point, the position being consistent with the bit wide that second Q signal occupies is intercepted
Number obtains third Q signal；
When the value for determining the highest order for not intercepting part in second Q signal reaches given threshold, and to described the
The lowest order that part has been intercepted in two Q signals executes carry operation, when the carry result of acquisition is not spilt over, by the carry result
As third Q signal；Otherwise, part will have directly been intercepted in second Q signal as third Q signal.
Optionally, it is based on the third I signal and the third Q signal, when generating target I/Q signal, the generation unit
43 are used for:
Based on the third I signal and the third Q signal, signal position is determined, wherein the bit wide of the signal bit occupancy
The sum of the bit wide that the bit wide occupied for the third I signal and the third Q signal occupy；
Based on the default control bit wide, control bit is determined, wherein the control bit is used for transmission the carrying of target I/Q signal
Control information；
Based on the signal position and the control bit, target I/Q signal is generated.
In conclusion passing through the first I signal and the first Q signal for including based on initial I/Q signal in the embodiment of the present invention
Respective leading symbol digit determines integral shift length, and is based on integral shift length, respectively to the first I signal and the first Q
Signal carries out shifting processing, the second I signal and the second Q signal is obtained, and according to preset bit wide, respectively to the second I signal
It is truncated processing with the second Q signal, obtains third I signal and third Q signal, and be based on third I signal and third Q signal,
Target I/Q signal is generated, in this way, time delay is greatly reduced, moreover, because completely remaining without increasing additional AGC processing
The I/Q signal of part position section, signal fidelity is higher, compression loss is greatly reduced, simultaneously as pertaining only to the place of I/Q signal
Reason, therefore, can be compatible with the realization of existing Transmission system without changing system hardware structure, substantially increases user experience.
It should be understood by those skilled in the art that, the embodiment of the present invention can provide as method, system or computer program
Product.Therefore, complete hardware embodiment, complete software embodiment or reality combining software and hardware aspects can be used in the present invention
Apply the form of example.Moreover, it wherein includes the computer of computer usable program code that the present invention, which can be used in one or more,
The computer program implemented in usable storage medium (including but not limited to magnetic disk storage, CD-ROM, optical memory etc.) produces
The form of product.
The present invention be referring to according to the method for the embodiment of the present invention, the process of equipment (system) and computer program product
Figure and/or block diagram describe.It should be understood that every one stream in flowchart and/or the block diagram can be realized by computer program instructions
The combination of process and/or box in journey and/or box and flowchart and/or the block diagram.It can provide these computer programs
Instruct the processor of general purpose computer, special purpose computer, Embedded Processor or other programmable data processing devices to produce
A raw machine, so that being generated by the instruction that computer or the processor of other programmable data processing devices execute for real
The device for the function of being specified in present one or more flows of the flowchart and/or one or more blocks of the block diagram.
These computer program instructions, which may also be stored in, is able to guide computer or other programmable data processing devices with spy
Determine in the computer-readable memory that mode works, so that it includes referring to that instruction stored in the computer readable memory, which generates,
Enable the manufacture of device, the command device realize in one box of one or more flows of the flowchart and/or block diagram or
The function of being specified in multiple boxes.
These computer program instructions also can be loaded onto a computer or other programmable data processing device, so that counting
Series of operation steps are executed on calculation machine or other programmable devices to generate computer implemented processing, thus in computer or
The instruction executed on other programmable devices is provided for realizing in one or more flows of the flowchart and/or block diagram one
The step of function of being specified in a box or multiple boxes.
Although preferred embodiments of the present invention have been described, it is created once a person skilled in the art knows basic
Property concept, then additional changes and modifications may be made to these embodiments.So it includes excellent that the following claims are intended to be interpreted as
It selects embodiment and falls into all change and modification of the scope of the invention.
Obviously, those skilled in the art can carry out various modification and variations without departing from this hair to the embodiment of the present invention
The spirit and scope of bright embodiment.In this way, if these modifications and variations of the embodiment of the present invention belong to the claims in the present invention
And its within the scope of equivalent technologies, then the present invention is also intended to include these modifications and variations.
Claims (12)
1. a kind of compression method characterized by comprising
Initial I/Q signal is obtained, and before the first I signal for including based on the initial I/Q signal and the first Q signal are corresponding
Symbol digit is led, determines the integral shift length of the initial I/Q signal；
Based on the integral shift length, shifting processing is carried out to first I signal and first Q signal respectively, is obtained
Second I signal and the second Q signal；
According to preset bit wide, processing is truncated to second I signal and second Q signal respectively, obtains the 3rd I letter
Number and third Q signal；
Based on the third I signal and the third Q signal, target I/Q signal is generated.
2. the method as described in claim 1, which is characterized in that the first I signal for including based on the initial I/Q signal and
The corresponding leading symbol digit of one Q signal, determines the integral shift length of the initial I/Q signal, comprising:
Determine the first leading symbol digit that first I signal includes；
Determine the second leading symbol digit that first Q signal includes；
The first leading symbol digit and the second leading symbol digit are compared, determine the small side of value, and
Based on the small side of the value, the integral shift length of the initial I/Q signal is determined.
3. the method as described in claim 1, which is characterized in that be based on the integral shift length, believe respectively the first I
Number and first Q signal carry out shifting processing, obtain the second I signal and the second Q signal, comprising:
First I signal is moved to the left to the digit being consistent with the integral shift length, obtains the second I signal；
First Q signal is moved to the left to the digit being consistent with the integral shift length, obtains the second Q signal.
4. method as claimed in claim 1,2 or 3, which is characterized in that according to preset bit wide, believe respectively the 2nd I
Number and second Q signal be truncated processing, acquisition third I signal and third Q signal, comprising:
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined；
Based on the residue transmission bit wide, the bit wide that second I signal occupies and the position that second Q signal occupies are determined
It is wide；
Based on the bit wide that second I signal occupies, processing is truncated to second I signal, obtains third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains third Q signal.
5. method as claimed in claim 4, which is characterized in that based on the bit wide that second I signal occupies, to described second
I signal is truncated processing, obtains third I signal, comprising:
Using the highest order of second I signal as starting point, the digit being consistent with the bit wide that second I signal occupies is intercepted；
When the value for determining the highest order for not intercepting part in second I signal reaches given threshold, and the 2nd I is believed
Intercepted in number part lowest order execute carry operation, when the carry result of acquisition is not spilt over, using the carry result as
Third I signal；Otherwise, part will have directly been intercepted in second I signal as third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains third Q signal, packet
It includes:
Using the highest order of second Q signal as starting point, the digit being consistent with the bit wide that second Q signal occupies is intercepted,
Obtain third Q signal；
When the value for determining the highest order for not intercepting part in second Q signal reaches given threshold, and the 2nd Q is believed
Intercepted in number part lowest order execute carry operation, when the carry result of acquisition is not spilt over, using the carry result as
Third Q signal；Otherwise, part will have directly been intercepted in second Q signal as third Q signal.
6. the method according to claim 1 to 5, which is characterized in that be based on the third I signal and the 3rd Q
Signal generates target I/Q signal, comprising:
Based on the third I signal and the third Q signal, signal position is determined, wherein the bit wide of the signal bit occupancy is institute
The sum of the bit wide that the bit wide and the third Q signal for stating third I signal occupancy occupy；
Based on the default control bit wide, control bit is determined, wherein the control bit is used for transmission the control of target I/Q signal carrying
Information processed；
Based on the signal position and the control bit, target I/Q signal is generated.
7. a kind of signal compression device characterized by comprising
Processing unit, for obtaining initial I/Q signal, and the first I signal and the first Q letter for including based on the initial I/Q signal
Number corresponding leading symbol digit, determines the integral shift length of the initial I/Q signal；
Shift unit respectively carries out first I signal and first Q signal for being based on the integral shift length
Shifting processing obtains the second I signal and the second Q signal；
Cut position unit, for being truncated place to second I signal and second Q signal respectively according to preset bit wide
Reason obtains third I signal and third Q signal；
Generation unit generates target I/Q signal for being based on the third I signal and the third Q signal.
8. device as claimed in claim 7, which is characterized in that the first I signal for including based on the initial I/Q signal and
The corresponding leading symbol digit of one Q signal, when determining the integral shift length of the initial I/Q signal, the processing unit
For:
Determine the first leading symbol digit that first I signal includes；
Determine the second leading symbol digit that first Q signal includes；
The first leading symbol digit and the second leading symbol digit are compared, determine the small side of value, and
Based on the small side of the value, the integral shift length of the initial I/Q signal is determined.
9. device as claimed in claim 7, which is characterized in that be based on the integral shift length, believe respectively the first I
Number and first Q signal carry out shifting processing, obtain the second I signal and when the second Q signal, the shift unit be used for:
First I signal is moved to the left to the digit being consistent with the integral shift length, obtains the second I signal；
First Q signal is moved to the left to the digit being consistent with the integral shift length, obtains the second Q signal.
10. the device as described in claim 7,8 or 9, which is characterized in that according to preset bit wide, believe respectively the 2nd I
Number and second Q signal be truncated processing, when acquisition third I signal and third Q signal, the cut position unit is used for:
Based on current transmission bit wide and default control bit wide, residue transmission bit wide is determined；
Based on the residue transmission bit wide, the bit wide that second I signal occupies and the position that second Q signal occupies are determined
It is wide；
Based on the bit wide that second I signal occupies, processing is truncated to second I signal, obtains third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, obtains third Q signal.
11. device as claimed in claim 10, which is characterized in that based on the bit wide that second I signal occupies, to described the
Two I signals are truncated processing, and when obtaining third I signal, the cut position unit is used for:
Using the highest order of second I signal as starting point, the digit being consistent with the bit wide that second I signal occupies is intercepted；
When the value for determining the highest order for not intercepting part in second I signal reaches given threshold, and the 2nd I is believed
Intercepted in number part lowest order execute carry operation, when the carry result of acquisition is not spilt over, using the carry result as
Third I signal；Otherwise, part will have directly been intercepted in second I signal as third I signal；
Based on the bit wide that second Q signal occupies, processing is truncated to second Q signal, when obtaining third Q signal,
The cut position unit is used for:
Using the highest order of second Q signal as starting point, the digit being consistent with the bit wide that second Q signal occupies is intercepted,
Obtain third Q signal；
When the value for determining the highest order for not intercepting part in second Q signal reaches given threshold, and the 2nd Q is believed
Intercepted in number part lowest order execute carry operation, when the carry result of acquisition is not spilt over, using the carry result as
Third Q signal；Otherwise, part will have directly been intercepted in second Q signal as third Q signal.
12. such as the described in any item devices of claim 7-11, which is characterized in that be based on the third I signal and the third
Q signal, when generating target I/Q signal, the generation unit is used for:
Based on the third I signal and the third Q signal, signal position is determined, wherein the bit wide of the signal bit occupancy is institute
The sum of the bit wide that the bit wide and the third Q signal for stating third I signal occupancy occupy；
Based on the default control bit wide, control bit is determined, wherein the control bit is used for transmission the control of target I/Q signal carrying
Information processed；
Based on the signal position and the control bit, target I/Q signal is generated.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710423939.2A CN109005561B (en) | 2017-06-07 | 2017-06-07 | Signal compression method and device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN201710423939.2A CN109005561B (en) | 2017-06-07 | 2017-06-07 | Signal compression method and device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN109005561A true CN109005561A (en) | 2018-12-14 |
| CN109005561B CN109005561B (en) | 2020-07-21 |
Family
ID=64573392
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201710423939.2A Active CN109005561B (en) | 2017-06-07 | 2017-06-07 | Signal compression method and device |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN109005561B (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400570A (en) * | 2019-06-24 | 2019-11-01 | 成都航天通信设备有限责任公司 | A kind of multi-path digital audio mixing implementation method |
| CN113114686A (en) * | 2021-04-14 | 2021-07-13 | 广州开信通讯系统有限公司 | Optical fiber transmission method for 5G and transmission system thereof |
| CN113381964A (en) * | 2020-03-09 | 2021-09-10 | 中国电信股份有限公司 | Method, system and storage medium for transmitting data in indoor distribution system |
| CN113450807A (en) * | 2020-03-25 | 2021-09-28 | 大唐移动通信设备有限公司 | Method and device for compressing voice digital signal |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN105471776A (en) * | 2015-11-26 | 2016-04-06 | 京信通信系统（广州）有限公司 | Signal transmission method and device |
| US20160373239A1 (en) * | 2015-06-18 | 2016-12-22 | Mediatek Singapore Pte. Ltd. | Synthesizer module, rf transceiver and method therefor |
| CN106713199A (en) * | 2015-08-14 | 2017-05-24 | 芯迪半导体科技（上海）有限公司 | OFDM receiver and frequency response equalization method thereof |
-
2017
- 2017-06-07 CN CN201710423939.2A patent/CN109005561B/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20160373239A1 (en) * | 2015-06-18 | 2016-12-22 | Mediatek Singapore Pte. Ltd. | Synthesizer module, rf transceiver and method therefor |
| CN106713199A (en) * | 2015-08-14 | 2017-05-24 | 芯迪半导体科技（上海）有限公司 | OFDM receiver and frequency response equalization method thereof |
| CN105471776A (en) * | 2015-11-26 | 2016-04-06 | 京信通信系统（广州）有限公司 | Signal transmission method and device |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110400570A (en) * | 2019-06-24 | 2019-11-01 | 成都航天通信设备有限责任公司 | A kind of multi-path digital audio mixing implementation method |
| CN110400570B (en) * | 2019-06-24 | 2021-08-31 | 成都航天通信设备有限责任公司 | Multi-channel digital audio mixing implementation method |
| CN113381964A (en) * | 2020-03-09 | 2021-09-10 | 中国电信股份有限公司 | Method, system and storage medium for transmitting data in indoor distribution system |
| CN113381964B (en) * | 2020-03-09 | 2022-08-02 | 中国电信股份有限公司 | Method, system and storage medium for transmitting data in indoor distribution system |
| CN113450807A (en) * | 2020-03-25 | 2021-09-28 | 大唐移动通信设备有限公司 | Method and device for compressing voice digital signal |
| CN113450807B (en) * | 2020-03-25 | 2023-03-17 | 大唐移动通信设备有限公司 | Method and device for compressing voice digital signal |
| CN113114686A (en) * | 2021-04-14 | 2021-07-13 | 广州开信通讯系统有限公司 | Optical fiber transmission method for 5G and transmission system thereof |
| CN113114686B (en) * | 2021-04-14 | 2023-03-21 | 广州开信通讯系统有限公司 | Optical fiber transmission method for 5G and transmission system thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| CN109005561B (en) | 2020-07-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN109005561A (en) | A kind of compression method and device | |
| Kaltenberger et al. | The OpenAirInterface 5G new radio implementation: Current status and roadmap | |
| CN105164956B (en) | Speed matching method and equipment, the wireless communication device of Polar code | |
| US20190288818A1 (en) | Coding scheme determining method and apparatus | |
| JP2022517750A (en) | Downstream data reception method, transmission method, device and storage medium | |
| CN105978611A (en) | Frequency domain signal compression method and device | |
| CN113395714B (en) | Frequency hopping method and system, terminal and base station | |
| CN108965333B (en) | Data compression method, data decompression method, data compression system, data decompression system and electronic equipment | |
| CN108429713A (en) | A kind of data compression method and apparatus | |
| EP4362544A1 (en) | Electronic device for controlling e2 termination on basis of traffic information of e2 termination, and method for operating electronic device | |
| CN109690987A (en) | Transmit method, receiving device and the sending ending equipment of data | |
| CN110099449A (en) | A kind of uplink information transmission and equipment | |
| CN107113790A (en) | A kind of carrier polymerizing method and device | |
| CN115336202A (en) | Encoding and decoding method and device for polarization code | |
| CN109392021A (en) | A kind of cell cooperating method and relevant device | |
| CN108365929A (en) | The method and apparatus of transmission data and the method and apparatus for transmitting information | |
| CN111245560B (en) | Data transmission method and device | |
| CN104812073A (en) | Terminal capability reporting method and device | |
| US20190174424A1 (en) | Data transmission method and network device thereof | |
| CN109995382B (en) | Polar code decoder | |
| CN107306424A (en) | Data transmission method and device | |
| CN110831167B (en) | Information indication method and device | |
| CN109428688A (en) | A kind of HARQ number of retransmissions Dynamic Configuration, device and medium | |
| KR20210015634A (en) | Method and apparatus for transmitting and receiving signal using polar code in communication system | |
| CN110622604B (en) | Service execution method and device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |