CN109004029A - With metal oxide/silica gatestack GaN base MOS-HEMT device and preparation method thereof - Google Patents
With metal oxide/silica gatestack GaN base MOS-HEMT device and preparation method thereof Download PDFInfo
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- 239000000377 silicon dioxide Substances 0.000 title claims abstract description 53
- 229910044991 metal oxide Inorganic materials 0.000 title claims abstract description 39
- 150000004706 metal oxides Chemical class 0.000 title claims abstract description 39
- 238000002360 preparation method Methods 0.000 title abstract description 28
- 229910002704 AlGaN Inorganic materials 0.000 claims abstract description 70
- 238000000407 epitaxy Methods 0.000 claims abstract description 29
- 238000001755 magnetron sputter deposition Methods 0.000 claims abstract description 28
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 26
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 26
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- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 26
- 238000000034 method Methods 0.000 claims description 55
- 229910052751 metal Inorganic materials 0.000 claims description 44
- 239000002184 metal Substances 0.000 claims description 44
- 238000005036 potential barrier Methods 0.000 claims description 32
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 claims description 30
- 150000004767 nitrides Chemical class 0.000 claims description 26
- 238000005229 chemical vapour deposition Methods 0.000 claims description 21
- 229920002120 photoresistant polymer Polymers 0.000 claims description 21
- 239000010931 gold Substances 0.000 claims description 20
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 19
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- 238000002955 isolation Methods 0.000 claims description 13
- 229910001845 yogo sapphire Inorganic materials 0.000 claims description 13
- 238000005566 electron beam evaporation Methods 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 10
- 229910052759 nickel Inorganic materials 0.000 claims description 10
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims description 8
- 239000000126 substance Substances 0.000 claims description 7
- 239000000463 material Substances 0.000 claims description 6
- 239000012299 nitrogen atmosphere Substances 0.000 claims description 5
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 claims description 4
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 4
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- 238000005859 coupling reaction Methods 0.000 claims description 4
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- 229910003087 TiOx Inorganic materials 0.000 claims description 3
- QZQVBEXLDFYHSR-UHFFFAOYSA-N gallium(III) oxide Inorganic materials O=[Ga]O[Ga]=O QZQVBEXLDFYHSR-UHFFFAOYSA-N 0.000 claims description 3
- CJNBYAVZURUTKZ-UHFFFAOYSA-N hafnium(IV) oxide Inorganic materials O=[Hf]=O CJNBYAVZURUTKZ-UHFFFAOYSA-N 0.000 claims description 3
- NRTOMJZYCJJWKI-UHFFFAOYSA-N Titanium nitride Chemical compound [Ti]#N NRTOMJZYCJJWKI-UHFFFAOYSA-N 0.000 claims description 2
- 229910000147 aluminium phosphate Inorganic materials 0.000 claims description 2
- 238000001020 plasma etching Methods 0.000 claims description 2
- HLLICFJUWSZHRJ-UHFFFAOYSA-N tioxidazole Chemical compound CCCOC1=CC=C2N=C(NC(=O)OC)SC2=C1 HLLICFJUWSZHRJ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052719 titanium Inorganic materials 0.000 claims description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 claims 1
- 239000002253 acid Substances 0.000 claims 1
- 229910052731 fluorine Inorganic materials 0.000 claims 1
- 239000011737 fluorine Substances 0.000 claims 1
- 239000001257 hydrogen Substances 0.000 claims 1
- 229910052739 hydrogen Inorganic materials 0.000 claims 1
- 125000004435 hydrogen atom Chemical class [H]* 0.000 claims 1
- 230000007547 defect Effects 0.000 abstract description 8
- 229910002601 GaN Inorganic materials 0.000 description 66
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- KFZMGEQAYNKOFK-UHFFFAOYSA-N Isopropanol Chemical compound CC(C)O KFZMGEQAYNKOFK-UHFFFAOYSA-N 0.000 description 6
- 238000001259 photo etching Methods 0.000 description 6
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- QAOWNCQODCNURD-UHFFFAOYSA-N Sulfuric acid Chemical compound OS(O)(=O)=O QAOWNCQODCNURD-UHFFFAOYSA-N 0.000 description 3
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- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
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- 238000004891 communication Methods 0.000 description 2
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 2
- 229910001195 gallium oxide Inorganic materials 0.000 description 2
- 230000015689 metaplastic ossification Effects 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 238000001552 radio frequency sputter deposition Methods 0.000 description 2
- JMASRVWKEDWRBT-UHFFFAOYSA-N Gallium nitride Chemical compound [Ga]#N JMASRVWKEDWRBT-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003139 buffering effect Effects 0.000 description 1
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- 229910000077 silane Inorganic materials 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66446—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET]
- H01L29/66462—Unipolar field-effect transistors with an active layer made of a group 13/15 material, e.g. group 13/15 velocity modulation transistor [VMT], group 13/15 negative resistance FET [NERFET] with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
Abstract
The invention discloses with metal oxide/silica gatestack GaN base MOS-HEMT device and preparation method thereof；The device includes AlGaN/GaN heterogenous junction epitaxy layer, the first gate dielectric layer, the second gate dielectric layer, gate electrode and source-drain electrode；First gate dielectric layer is the SiO being covered on AlGaN/GaN heterogenous junction epitaxy layer2Film, the first gate dielectric layer with a thickness of 5-15nm；Second gate dielectric layer is the metal-oxide film being covered on the first gate dielectric layer, the second gate dielectric layer with a thickness of 5-15nm；The present invention uses metal oxide/SiO2Laminated medium structure, reduce damage of the magnetron sputtering deposit high dielectric constant medium of oxides to extension, make that it is suitable for the preparations of GaN base HEMT device；SiO is compensated for simultaneously2The low defect of dielectric constant improves device entirety grid control ability and effectively reduces electric leakage of the grid.
Description
Technical field
The present invention relates to MOS-HEMT devices, have metal oxide/silica gatestack more specifically to one kind
GaN base MOS-HEMT device and preparation method thereof, GaN base MOS-HEMT device can be used for the neck such as power electronics and microwave communication
Domain, the invention belongs to technical field of semiconductors.
Background technique
With the development of modern weapons equipment and aerospace, nuclear energy, the communication technology, automotive electronics, Switching Power Supply, half-and-half
More stringent requirements are proposed for conductor performance.The representative of GaN and gaN series material as third generation semiconductor material with wide forbidden band, has
Forbidden bandwidth big (3.4eV), electron saturation velocities height (2 × 107Cm/s), disruptive field intensity is high, thermal conductivity height and corrosion-resistant etc. special
Point, it is considered to be the excellent materials of high voltagehigh frequency high-power electronic device.In addition, GaN can form modulation doping with AlGaN
AlGaN/GaN heterojunction structure, the structure can form the two-dimensional electron gas of high electron concentration and high electron mobility at room temperature,
This makes AlGaN/GaN high electron mobility transistor (HEMT) to become mostly important one of the type of device in gallium nitride field.
Due to AlGaN/GaN crystalline epitaxial surface defect, metal/semiconductor Schottky contacts quality etc., traditional Xiao
The disadvantages of that there are electric leakage of the grid is serious for the HEMT device of special base grid structure, and the gate operational voltages amplitude of oscillation is small, seriously limits GaN base
The performance of HEMT device performance advantage.For this problem, the method generallyd use at present is in gate electrode and AlGaN potential barrier
Between insertion medium of oxides layer formed MOS structure.
The method of gate dielectric layer preparation mainly includes PECVD (plasma enhanced chemical vapor deposition), LPCVD (low pressure
Chemical vapor deposition), the methods of ALD (atomic layer deposition) and PVD (physical deposition), several method respectively has superiority and inferiority.ALD deposition
Film quality is high, but is chiefly used in tentative experiment, and not compatible with conventional semiconductor processing, deposition velocity is slow, volume production is difficult；
The silicon nitride and silica of PECVD/LPCVD deposition cause grid-control ability not as good as Gao Jie since material dielectric constant itself is low
Permittivity media structure；Although PVD energy deposit high dielectric constant medium, externally postponing a meeting or conference has physical damnification, leads to epitaxial surface
Defect increases, and device current is degenerated.Based on the above circumstances, how under the premise of being compatible with traditional silicon MOS technique, Gao Jie is realized
Quick, the inexpensive preparation of electric constant gate medium is GaN base MOS-HEMT device urgent problem to be solved.
Summary of the invention
It is an object of the invention to overcome the defect of the gate medium technology of preparing of existing GaN base MOS-HEMT device, from
The angle of gate dielectric structure and preparation process propose a kind of with metal oxide/silica gatestack GaN base MOS-HEMT
Device and preparation method thereof can effectively reduce device grids leakage current and improve grid control ability, be suitable for simultaneously
Large-scale production.
To achieve the above object, the invention provides the following technical scheme:
With metal oxide/silica gatestack GaN base MOS-HEMT device, including outside AlGaN/GaN hetero-junctions
Prolong layer, the first gate dielectric layer, the second gate dielectric layer, gate electrode and source-drain electrode；The AlGaN/GaN heterogenous junction epitaxy layer is under
And upper includes substrate, nitride nucleating layer, nitride buffer layer, GaN channel layer and AlGaN potential barrier；
First gate dielectric layer is the SiO being covered on AlGaN/GaN heterogenous junction epitaxy layer2Film, the first gate medium
Layer with a thickness of 5-15nm；
Second gate dielectric layer is the metal-oxide film being covered on the first gate dielectric layer, the metal oxide
For Al2O3、Ga2O3、HfO2Or TiOx, the second gate dielectric layer with a thickness of 5-15nm；
First gate dielectric layer, the second gate dielectric layer and AlGaN/GaN heterogenous junction epitaxy layer form MOS structure；
The source-drain electrode is the spaced source electrode and drain electrode on AlGaN potential barrier face；In source electrode and leakage
Gate electrode is equipped between electrode, the gate electrode is arranged on the second gate dielectric layer.
To further realize the object of the invention, it is preferable that the thickness of the gate electrode and source-drain electrode is all 100-
300nm。
Preferably, the cross section of the gate electrode and source-drain electrode is all round.
Preferably, the gate electrode cross section is a length of rectangle of item, a length of 50-2000 μm, 2-10 μm wide.
Preferably, the substrate, nitride nucleating layer, nitride buffer layer, GaN channel layer and AlGaN potential barrier
Thickness is respectively 0.5-2mm, 0.2-1 μm, 500-2500nm, 100-500nm and 10-30nm.
Preferably, the cross section of the substrate is circle, diameter 4inch-10inch.
Preferably, the SiO2Film is heavy by plasma reinforced chemical vapour deposition (PECVD) or low pressure chemical phase
Product (LPCVD deposition) is formed.
Preferably, the metal-oxide film is deposited by magnetron sputtering forms.
Described has metal oxide/silica gatestack GaN base MOS-HEMT device method, including walks as follows
It is rapid:
1) epitaxial growth: by metal organic chemical vapor deposition, on substrate successively epitaxial growth nitride nucleating layer, nitridation
Object buffer layer, GaN channel layer, AlGaN potential barrier form AlGaN/GaN heterogenous junction epitaxy layer；
2) device isolation: defining active area, carries out covering protection to active area using photoresist；Using inductively it is equal from
Daughter etching ICP is removed the AlGaN/GaN heterogenous junction epitaxy layer other than active area, and etching depth is greater than AlGaN potential barrier
The thickness of layer and GaN channel layer；
3) prepared by source-drain electrode: being realized in step 2) by negative-working photoresist technique and defines source and drain electricity on the active area of isolation
Pole metal sites and figure deposit source-drain electrode film by electron beam evaporation or magnetron sputtering；In nitrogen atmosphere, 800 DEG C
It anneals in above temperature, source-drain electrode and AlGaN potential barrier is made to form Ohmic contact；
4) first grid cvd dielectric layer: SiO is deposited on AlGaN/GaN heterogenous junction epitaxy layer2Film forms the first grid and is situated between
Matter layer be covering, the first gate dielectric layer with a thickness of 5-15nm；
5) second gate cvd dielectric layer: by magnetron sputtering on the first gate dielectric layer depositing metal oxide film；
6) medium removes: source-drain electrode region first layer medium, second layer dielectric layer being removed, source-drain electrode gold is exposed
Belong to；Photoresist protection Region Medium in addition to source-drain electrode is first passed through, it is rear to carry out medium removal；
7) prepared by gate electrode: preparing gate electrode between source-drain electrode metal by electron beam evaporation or magnetron sputtering.
First layer metal chooses high work function material, and such as nickel metal, golden Au or titanium nitride TiN etc. is can be used in second layer metal
Good conductivity, the stable metal of chemical property.
Preferably, source-drain electrode film described in step 3) is made of Ti/Al metal system multiple layer metal, passes through removing
Technique forms source-drain electrode metal wire；The Ti/Al metal system is Ti/Al/Ni/Au or Ti/Al/Ni/TiN；
The method that the step 6) medium removes is wet etching or dry etching；The solution that wherein wet etching uses for
Hydrofluoric acid or phosphoric acid etc.；The dry etching is sense coupling or reactive ion etching；
Gate electrode described in step 7) is made of double layer of metal, and first layer metal selects nickel metal, and second layer metal is selected
Au or TiN.
The present invention is to form source-drain electrode in GaN epitaxy on-chip active area；Then heavy using Plasma Enhanced Chemical Vapor
Product forms the first gate dielectric layer SiO2, reuse the second gate dielectric layer that magnetron sputtering forms high dielectric constant；It is carved by dry method
Etching off is except the first medium layer and second layer medium above source-drain electrode metal；Gate electrode is formed between source-drain electrode.
First gate dielectric layer of the invention is by plasma reinforced chemical vapour deposition PECVD or low-pressure chemical vapor deposition
The SiO of LPCVD deposition2Film, this layer of SiO2It is required that film compactness is good, movable charge density is small in dielectric layer, leakage current
It is small, disruptive field intensity is high and has high quality interface with AlGaN；To reduce gate leakage currents and reduce active area by next step magnetic
Control the damage of sputtering technology.Second gate dielectric layer is the higher metal-oxide film of dielectric constant deposited by magnetron sputtering,
The higher metal oxide of dielectric constant can be Al2O3、Ga2O3、HfO2、TiOxOne of.The layer film requires compactness
Well, disruptive field intensity is high, relative dielectric constant is high and and SiO2There is high quality interface；Meanwhile the surface roughness of two layers of medium
It is smaller；To further decrease Leakage Current while keep grid-control ability.
Compared with the existing technology, the present invention have the advantage that and the utility model has the advantages that
1) first layer SiO of the present invention2Active area is formed and is protected, reduces subsequent magnetron sputtering technique to the damage of extension
Wound；Second layer high dielectric constant further improves the leakage current characteristic of dielectric layer, and compensates for first layer SiO2Opposite dielectric
The low defect of constant improves grid to the control ability of channel, and then improves the dynamic electrical characteristics of device.
2) plasma enhanced chemical vapor deposition PECVD, low-pressure chemical vapor deposition LPCVD and magnetron sputtering PVD are equal
Belong to the mature technology of semi-conductor industry metaplasia production, the MOS structure of above-mentioned laminated process preparation can be used in large-scale production, subtract
The grid leak electricity of gadget, the breakdown characteristics and dynamic electrical characteristics for improving device.
3) present invention uses metal oxide/SiO2Laminated medium structure, reducing magnetron sputtering, to deposit high dielectric normal
Damage of the number medium of oxides to extension, makes that it is suitable for the preparations of GaN base HEMT device；Make device entirety grid control ability
It improves and effectively reduces electric leakage of the grid.
4) technique used in the method for the present invention with SiMOS process compatible, simple process, strong operability.
Detailed description of the invention
Fig. 1 is that the present invention is a kind of with metal oxide/silica gatestack GaN base MOS-HEMT device preparation method
Flow chart.
Fig. 2-Fig. 8 is that the present invention is a kind of to be formed with metal oxide/silica gatestack GaN base MOS-HEMT device
Process schematic.
Fig. 9 is the grid with metal oxide/silica gatestack GaN base MOS-HEMT device of specific embodiment 1
Source IV curve；
Figure 10 is the pass with metal oxide/silica gatestack GaN base MOS-HEMT device of specific embodiment 1
State punctures curve；
Figure 11 is turning with metal oxide/silica gatestack GaN base MOS-HEMT device for specific embodiment 1
Move curve.
It is shown in figure: AlGaN/GaN heterogenous junction epitaxy layer 1, AlGaN potential barrier 01, GaN channel layer 02, nitride buffering
Layer 03, nitride nucleating layer 04, substrate 05, source-drain electrode 2, the first gate dielectric layer 3, the second gate dielectric layer 4, gate electrode 5.
Specific embodiment
Specific implementation of the invention is described further below in conjunction with drawings and examples, but the present invention implements and protection
It is without being limited thereto, it should be pointed out that if the following promising process being especially described in detail or technological parameter belong to those skilled in the art
Member can refer to prior art realization.
As shown in figure 8, having metal oxide/silica gatestack GaN base MOS-HEMT device, including AlGaN/
GaN heterogenous junction epitaxy layer 1, the first gate dielectric layer 3, the second gate dielectric layer 4, gate electrode 5, source-drain electrode 2.The AlGaN/GaN
Heterogenous junction epitaxy layer 1 from bottom to top include substrate 05, nitride nucleating layer 04, nitride buffer layer 03, GaN channel layer 02,
AlGaN potential barrier 01；The substrate 05 is preferably circular, and diameter is preferably 4inch-10inch；The substrate 05, nitride
Nucleating layer 04, nitride buffer layer 03, GaN channel layer 02, AlGaN potential barrier 01 thickness be respectively 0.5-2mm, 0.2-1 μm,
500-2500nm, 100-500nm and 10-30nm.
First gate dielectric layer 3 is on being covered on AlGaN/GaN heterogenous junction epitaxy layer 1, with a thickness of 5-15nm；Described
Two gate dielectric layers 4 are covered on the first gate dielectric layer 3；Second gate dielectric layer 4 with a thickness of 5-15nm, the first gate dielectric layer 3,
Two gate dielectric layers 4 form MOS structure with AlGaN/GaN heterogenous junction epitaxy layer 1；The source-drain electrode is included in AlGaN potential barrier
Spaced source electrode and drain electrode on 01 face；Gate electrode 5 is equipped between source electrode and drain electrode, the gate electrode 5 is set
It sets on the second gate dielectric layer 4.The thickness of gate electrode 5 and source-drain electrode 2 is preferably all 100-300nm.
Embodiment 1
As shown in Figure 1, corresponding each process description has metal oxide/silica gatestack GaN referring to Fig. 2-Fig. 8
The preparation method of base MOS-HEMT device includes the following steps:
It is prepared by step S1:AlGaN/GaN heterogenous junction epitaxy layer 1.By metal organic chemical vapor deposition (MOCVD), in Si or
Nitride nucleating layer 04, nitride buffer layer 03, the GaN channel layer 02, AlGaN potential barrier 01 successively grown in SiC substrate 05,
As shown in Figure 2.Then AlGaN/GaN heterogenous junction epitaxy layer 1 is soaked in H2SO4:H2O210 points in=6:1 (mass ratio) solution
Clock, to remove surface oxide layer, then using the organic matter on acetone and isopropanol removal AlGaN/GaN heterogenous junction epitaxy layer 1.
Step S2: device isolation is realized.Active area is defined by positive photoresist photoetching process, active area is wide 53 μm 100 μm long
Rectangle.Covering protection is carried out to active area using photoresist.Using sense coupling (ICP) to active area with
Outer GaN channel layer and AlGaN potential barrier hetero-junctions is removed, and etching depth is greater than or equal to AlGaN potential barrier and GaN ditch
The thickness summation of channel layer realizes the isolation between device as shown in Figure 3.
Step S3: prepared by source-drain electrode 2.It is realized by negative-working photoresist technique and is defined on the active area of isolation in step s 2
Source-drain electrode metal is long 100 μm wide 10 μm of rectangle, apart from 2 μm of active-surface.It is leaked electricity by electron beam evaporation sedimentary origin
Very thin films, used multiple layer metal are followed successively by Ti/Al/Ni/Au from top to bottom, and the thickness of Ti/Al/Ni/Au is respectively 20/100/
10/100nm forms source-drain electrode by stripping technology, as shown in Figure 4.Sample is placed under nitrogen atmosphere, is moved back in 850 DEG C
Fiery 1min makes source-drain electrode and AlGaN potential barrier form Ohmic contact.
The S4: the first gate dielectric layer of step 3 deposits.Lead on the face of nitride buffer layer, AlGaN potential barrier and source-drain electrode
Cross plasma reinforced chemical vapour deposition (PECVD deposition) SiO2The first gate dielectric layer 3 is formed, as shown in Figure 5.Its thickness
15nm, sedimentary condition are as follows: chamber pressure 850mTorr, high-purity N2O flow 1000sccm, high-purity N2Flow 400sccm, content are
The SiH of 5% (volume)4And N2Mixed gas flow 100sccm, 300 DEG C of reaction temperature, radio-frequency power 50W.Then print is turned
Move to magnetron sputtering cavity.
The S4: the second gate dielectric layer of step 4 deposits.The second layer is formed on the face of the first gate dielectric layer 3 by magnetron sputtering
Medium 4, as shown in Figure 6.This layer of Al2O3Preparation condition are as follows: using the aluminium oxide ceramics target of purity 99.99% as target, lining
300 DEG C of bottom temperature, sputter gas Ar, sputtering pressure 6mtorr, rf sputtering power 160W, deposition thickness 15nm.
Step S5: source-drain electrode 2 exposes.Photoresist is covered in non-source drain regions by photoetching process to be protected,
Use inductively coupled plasma etching ICP technique.With fluoroform CHF3And O2For process gas, actual conditions are as follows: CHF3Flow
For 50sccm, O2Flow is 10sccm, RF radio-frequency power 60W, ICP power 600W.By SiO2Dielectric layer 3 is with Al2O3Dielectric layer 4
Etching removal, realizes the exposing of source-drain electrode metal.As shown in Figure 7.
Step S6: prepared by gate electrode 5.As shown in figure 8, defining bargraphs and the position of gate electrode by negative-working photoresist technique
It sets, wherein 100 μm wide 3 μm of the rectangle of a length of length of gate electrode lines, between source-drain electrode.Using electron beam evaporation process according to
The deposit thickness of secondary deposition nickel and gold, nickel and gold is respectively 50nm and 150nm, realizes the second gate dielectric layer by stripping technology
The reservation of 4 top gate electrodes 5.
The device is the laminated gate medium MOS high electron mobility transistor based on AlGaN/GaN hetero-junctions, by using
Plasma reinforced chemical vapour deposition PEDCVD forms the first gate dielectric layer SiO2, after with magnetron sputtering formed the second gate dielectric layer
Al2O3Realize gatestack medium MOS structure.First gate dielectric layer SiO2Active area is formed and is protected, subsequent magnetic control can be effectively reduced and splash
Penetrate damage of the technique to extension；Second layer high K medium further improves the leakage current characteristic of dielectric layer, and compensates for the first gate medium
Layer SiO2The low defect of relative dielectric constant improves grid to the control ability of channel, and then improves the dynamic electric of device
Characteristic.Plasma enhanced chemical vapor deposition PECVD, low-pressure chemical vapor deposition LPCVD and magnetron sputtering PVD belong to half
The mature technology of conductor industrialized production, the MOS structure of above-mentioned laminated gate medium technique preparation subtract suitable for large-scale production
The grid leak electricity of gadget, the breakdown characteristics and dynamic electrical characteristics for improving device.
DC characteristic test is carried out using sample of the Agilent B1505 to embodiment 1, as a result such as Fig. 9, Figure 10, Tu11Suo
Show, in figure, SiO2/Al2O3It is the sample of embodiment 1, SiN is to use existing plasma reinforced chemical vapour deposition PECVD system
The sample of standby SiN medium.As shown in figure 9, in application -5V voltage, 1 sample grid leak electricity Ig < 10 of embodiment‐7A/mm, and it is existing
The SiN medium samples of some plasma reinforced chemical vapour deposition PECVD preparations, which is compared, reduces two orders of magnitude.Such as Figure 10 institute
Show, 1 sample breakdown voltage of embodiment reaches 530V, and nearly 330V is increased compared with the 200V of SiN medium samples.Such as Figure 11 institute
Show, 1 sample mutual conductance peak value of embodiment reaches 65mS/mm, the SiN medium sample with plasma reinforced chemical vapour deposition PECVD preparation
Condition ratio increases 12mS/mm.
Embodiment 2
As shown in Figure 1, corresponding each process description has metal oxide/silica gatestack GaN referring to Fig. 2-Fig. 8
The preparation method of base MOS-HEMT device includes the following steps:
It is prepared by step S1:AlGaN/GaN heterogenous junction epitaxy layer 1.By metal organic chemical vapor deposition (MOCVD), in Si or
Nitride nucleating layer 04, nitride buffer layer 03, the GaN channel layer 02, AlGaN potential barrier 01 successively grown in SiC substrate 05,
As shown in Figure 2.Then AlGaN/GaN heterogenous junction epitaxy layer 1 is soaked in H2SO4:H2O210 points in=6:1 (mass ratio) solution
Clock, to remove surface oxide layer, then using the organic matter on acetone and isopropanol removal AlGaN/GaN heterogenous junction epitaxy layer 1.
Step S2: device isolation is realized.Active area is defined by positive photoresist photoetching process, active area is wide 53 μm 100 μm long
Rectangle, apart from 2 μm of active area boundary.Covering protection is carried out to active area using photoresist.Utilize inductively coupled plasma
Etching ICP to other than active area GaN channel layer and AlGaN potential barrier hetero-junctions be removed, etching depth is greater than or equal to
The thickness summation of AlGaN potential barrier and GaN channel layer realizes the isolation between device as shown in Figure 3.
Step S3: prepared by source-drain electrode 2.It is realized by negative-working photoresist technique and is defined on the active area of isolation in step s 2
Source-drain electrode metal is long 100 μm wide 10 μm of rectangle, apart from 2 μm of active-surface.It is leaked electricity by electron beam evaporation sedimentary origin
Very thin films, used multiple layer metal are followed successively by Ti/Al/Ni/Au from top to bottom, and the thickness of Ti/Al/Ni/Au is respectively 20/100/
10/100nm forms source-drain electrode by stripping technology, as shown in Figure 4.Sample is placed under nitrogen atmosphere, is moved back in 850 DEG C
Fiery 1min makes source-drain electrode and AlGaN potential barrier form Ohmic contact.
The S4: the first gate dielectric layer of step 3 deposits.Lead on the face of nitride buffer layer, AlGaN potential barrier and source-drain electrode
Cross plasma reinforced chemical vapour deposition (PECVD deposition) SiO2The first gate dielectric layer 3 is formed, as shown in Figure 5.Its thickness
10nm, sedimentary condition are as follows: chamber pressure 850mTorr, high-purity N2O flow 1000sccm, high-purity N2Flow 400sccm, content are
The SiH of 5% (volume)4And N2Mixed gas flow 50sccm, 350 DEG C of reaction temperature, radio-frequency power 30W.Then print is shifted
To magnetron sputtering cavity.
The S4: the second gate dielectric layer of step 4 deposits.The second layer is formed on the face of the first gate dielectric layer 3 by magnetron sputtering
Medium 4, as shown in Figure 6.This layer of Al2O3Preparation condition are as follows: using the aluminium oxide ceramics target of purity 99.99% as target, lining
300 DEG C of bottom temperature, sputter gas Ar, it is passed through the reaction gas O that flow is 5sccm2, sputtering pressure 6mtorr, radio frequency splashes
Penetrating power is 160W, deposition thickness 15nm.
Step S5: source-drain electrode exposes.Photoresist is covered in non-source drain regions by photoetching process to be protected, and is made
With inductively coupled plasma etching ICP technique.With fluoroform CHF3And O2For process gas, actual conditions are as follows: CHF3Flow is
50sccm, O2Flow is 10sccm, RF radio-frequency power 60W, ICP power 600W.By SiO2Dielectric layer 3 is with Al2O34 quarter of dielectric layer
Etching off removes, and realizes the exposing of source-drain electrode metal.As shown in Figure 7.
Step S6: prepared by gate electrode 5.As shown in figure 8, grid bargraphs and position are defined by negative-working photoresist technique,
Wherein 100 μm wide 3 μm of the rectangle of a length of length of grid lines, between source-drain electrode.It is successively sunk using electron beam evaporation process
The deposit thickness of product nickel and gold, nickel and gold is respectively 50nm and 150nm, realizes Al by stripping technology2O34 top grid of medium
The reservation of electrode 5.
The device is the laminated gate medium MOS high electron mobility transistor based on AlGaN/GaN hetero-junctions, by using
Plasma reinforced chemical vapour deposition PEDCVD forms the first gate dielectric layer SiO2.Wherein with lower silane flow rate, higher deposition
Temperature realizes SiO2The control of film smaller thickness, more high compactness.The second gate dielectric layer Al is formed with magnetron sputtering afterwards2O3It is real
Existing gatestack medium MOS structure, it is preferable that be passed through oxygen in spatter film forming process and participate in reaction, improve Al2O3The insulating properties of film.
First gate dielectric layer SiO2Active area is formed and is protected, damage of the subsequent magnetron sputtering technique to extension can be effectively reduced；Second
Layer high K medium further improves the leakage current characteristic of dielectric layer, and compensates for the first gate dielectric layer SiO2Relative dielectric constant is low
Defect improves grid to the control ability of channel, and then improves the dynamic electrical characteristics of device.Plasma enhanced chemical gas
Mutually deposition PECVD, low-pressure chemical vapor deposition LPCVD and magnetron sputtering PVD belong to the mature work of semi-conductor industry metaplasia production
Skill, the MOS structure of above-mentioned laminated gate medium technique preparation reduce the grid leak electricity of device, improve device suitable for large-scale production
The breakdown characteristics and dynamic electrical characteristics of part.
In application -5V voltage, 2 sample grid leak electricity Ig < 10 of embodiment‐8A/mm, with existing plasma-reinforced chemical gas
Mutually the SiN medium samples of deposition PECVD preparation, which is compared, reduces two orders of magnitude.2 sample breakdown voltage of embodiment reaches 560V,
Nearly 360V is increased compared with plasma reinforced chemical vapour deposition PECVD prepares the 200V of SiN medium samples.2 sample of embodiment
Product mutual conductance peak value reaches 71mS/mm, increases compared with the SiN medium samples of plasma reinforced chemical vapour deposition PECVD preparation
18mS/mm。
Embodiment 3
As shown in Figure 1, corresponding each process description has metal oxide/silica gatestack GaN referring to Fig. 2-Fig. 8
The preparation method of base MOS-HEMT device includes the following steps:
It is prepared by step S1:AlGaN/GaN heterogenous junction epitaxy layer 1.By metal organic chemical vapor deposition (MOCVD), in Si or
Nitride nucleating layer 04, nitride buffer layer 03, the GaN channel layer 02, AlGaN potential barrier 01 successively grown in SiC substrate 05,
As shown in Figure 2.Then AlGaN/GaN heterogenous junction epitaxy layer 1 is soaked in H2SO4:H2O210 points in=6:1 (mass ratio) solution
Clock, to remove surface oxide layer, then using the organic matter on acetone and isopropanol removal AlGaN/GaN heterogenous junction epitaxy layer 1.
Step S2: device isolation is realized.Active area is defined by positive photoresist photoetching process, active area is wide 53 μm 100 μm long
Rectangle.Covering protection is carried out to active area using photoresist.Using sense coupling ICP to active area other than
GaN channel layer and AlGaN potential barrier hetero-junctions be removed, etching depth be greater than or equal to AlGaN potential barrier and GaN channel
The thickness summation of layer realizes the isolation between device as shown in Figure 3.
Step S3: source-drain electrode preparation.It is realized by negative-working photoresist technique and is defined on the active area of isolation in step s 2
Source-drain electrode metal is long 100 μm wide 10 μm of rectangle, apart from 2 μm of active-surface.It is leaked electricity by electron beam evaporation sedimentary origin
Very thin films, used multiple layer metal are followed successively by Ti/Al/Ni/Au from top to bottom, and the thickness of Ti/Al/Ni/Au is respectively 20/100/
10/100nm forms source-drain electrode by stripping technology, as shown in Figure 4.Sample is placed under nitrogen atmosphere, is moved back in 850 DEG C
Fiery 1min makes source-drain electrode and AlGaN potential barrier form Ohmic contact.
The S4: the first gate dielectric layer of step 3 deposits.Lead on the face of nitride buffer layer, AlGaN potential barrier and source-drain electrode
Cross plasma reinforced chemical vapour deposition (PECVD deposition) SiO2The first gate dielectric layer 3 is formed, as shown in Figure 5.Its thickness
15nm, sedimentary condition are as follows: chamber pressure 850mTorr, high-purity N2O flow 1000sccm, high-purity N2Flow 400sccm, content are
The SiH of 5% (volume)4And N2Mixed gas flow 100sccm, 300 DEG C of reaction temperature, radio-frequency power 50W.Then print is turned
Move to magnetron sputtering cavity.
The S4: the second gate dielectric layer of step 4 deposits.The second layer is formed on the face of the first gate dielectric layer 3 by magnetron sputtering
Medium 4, as shown in Figure 6.This layer of medium selects gallium oxide Ga of the relative dielectric constant up to 10 or more2O3, preparation condition are as follows: with pure
The gallium oxide ceramic target of degree 99.99% is as target, and 350 DEG C of underlayer temperature, sputter gas Ar, sputtering pressure is
3.5mtorr, rf sputtering power 140W, deposition thickness 15nm.
Step S5: source-drain electrode 2 exposes.Photoresist is covered in non-source drain regions by photoetching process to be protected,
Use inductively coupled plasma etching ICP technique.With fluoroform CHF3And O2For process gas, actual conditions are as follows: CHF3Flow
For 50sccm, O2Flow is 10sccm, RF radio-frequency power 60W, ICP power 600W.By SiO2Dielectric layer 3 is with Al2O3Dielectric layer 4
Etching removal, realizes the exposing of source-drain electrode metal.As shown in Figure 7.
Step S6: prepared by gate electrode 5.As shown in figure 8, grid bargraphs and position are defined by negative-working photoresist technique,
Wherein 100 μm wide 3 μm of the rectangle of a length of length of grid lines, between source-drain electrode.It is successively sunk using electron beam evaporation process
The deposit thickness of product nickel and gold, nickel and gold is respectively 50nm and 150nm, realizes Al by stripping technology2O34 top grid of medium
The reservation of electrode 5.
The device is the laminated gate medium MOS high electron mobility transistor based on AlGaN/GaN hetero-junctions, by using
Plasma reinforced chemical vapour deposition PEDCVD forms the first gate dielectric layer SiO2, after with magnetron sputtering formed the second gate dielectric layer
Al2O3Realize gatestack medium MOS structure.First gate dielectric layer SiO2Active area is formed and is protected, subsequent magnetic control can be effectively reduced and splash
Penetrate damage of the technique to extension；Second layer high K medium further improves the leakage current characteristic of dielectric layer, and compensates for the first gate medium
Layer SiO2The low defect of relative dielectric constant improves grid to the control ability of channel, and then improves the dynamic electric of device
Characteristic.Plasma enhanced chemical vapor deposition PECVD, low-pressure chemical vapor deposition LPCVD and magnetron sputtering PVD belong to half
The mature technology of conductor industrialized production, the MOS structure of above-mentioned laminated gate medium technique preparation subtract suitable for large-scale production
The grid leak electricity of gadget, the breakdown characteristics and dynamic electrical characteristics for improving device.
In application -5V voltage, 3 sample grid leak electricity Ig < 10 of embodiment‐6A/mm, with existing plasma-reinforced chemical gas
Mutually the SiN medium samples of deposition PECVD preparation, which is compared, reduces an order of magnitude.3 sample breakdown voltage of embodiment reaches 360V,
Nearly 160V is increased compared with the 200V of SiN medium samples.3 sample mutual conductance peak value of embodiment reaches 77mS/mm, enhances with plasma
The SiN medium samples of chemical vapor deposition PECVD preparation, which is compared, increases 24mS/mm.
It will be understood by those skilled in the art that in other embodiments, the sedimentary condition and mode of first layer medium can roots
It is adjusted according to needs, such as plasma reinforced chemical vapour deposition PECVD deposits SiO2Pressure, power, gas flow, or
Person deposits SiO using low-pressure chemical vapor deposition LPCVD2Also it can reach corresponding effect.Magnetron sputtering can similarly be prepared
Al2O3 sedimentary condition is adjusted.
Above-described embodiment is only preferred embodiment of the invention, does not constitute any limitation of the invention, it is clear that for ability
It, can be without departing substantially from the principle and scope of the present invention after understanding the contents of the present invention and principle for the professional in domain
In the case of, carry out various modifications and variations in form and details according to the method for the present invention, but these are based on of the invention
Modifications and variations are still within the scope of the present invention.
Claims (10)
1. having metal oxide/silica gatestack GaN base MOS-HEMT device, which is characterized in that including AlGaN/GaN
Heterogenous junction epitaxy layer, the first gate dielectric layer, the second gate dielectric layer, gate electrode and source-drain electrode；Outside the AlGaN/GaN hetero-junctions
Prolong layer includes substrate, nitride nucleating layer, nitride buffer layer, GaN channel layer and AlGaN potential barrier from bottom to top；
First gate dielectric layer is the SiO being covered on AlGaN/GaN heterogenous junction epitaxy layer2Film, the thickness of the first gate dielectric layer
Degree is 5-15nm；
Second gate dielectric layer is the metal-oxide film being covered on the first gate dielectric layer, and the metal oxide is
Al2O3、Ga2O3、HfO2Or TiOx, the second gate dielectric layer with a thickness of 5-15nm；
First gate dielectric layer, the second gate dielectric layer and AlGaN/GaN heterogenous junction epitaxy layer form MOS structure；
The source-drain electrode is the spaced source electrode and drain electrode on AlGaN potential barrier face；In source electrode and drain electrode
Between be equipped with gate electrode, the gate electrode is arranged on the second gate dielectric layer.
2. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is that the thickness of the gate electrode and source-drain electrode is all 100-300nm.
3. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is that the cross section of the gate electrode and source-drain electrode is all round.
4. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is that the gate electrode cross section is rectangle, a length of 50-2000 μm, 2-10 μm wide.
5. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is, the thickness difference of the substrate, nitride nucleating layer, nitride buffer layer, GaN channel layer and AlGaN potential barrier
For 0.5-2mm, 0.2-1 μm, 500-2500nm, 100-500nm and 10-30nm.
6. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is that the substrate is thin rounded flakes, diameter 4inch-10inch.
7. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is, the SiO2Film is by plasma reinforced chemical vapour deposition (PECVD) or low-pressure chemical vapor deposition (LPCVD
Deposition) it is formed.
8. according to claim 1 have metal oxide/silica gatestack GaN base MOS-HEMT device, spy
Sign is that the metal-oxide film is deposited by magnetron sputtering to be formed.
9. claim 1-8 is described in any item to have metal oxide/silica gatestack GaN base MOS-HEMT device side
Method, it is characterised in that include the following steps:
1) epitaxial growth: by metal organic chemical vapor deposition, successively epitaxial growth nitride nucleating layer, nitride are slow on substrate
Layer, GaN channel layer, AlGaN potential barrier are rushed, AlGaN/GaN heterogenous junction epitaxy layer is formed；
2) device isolation: defining active area, carries out covering protection to active area using photoresist；Utilize inductively coupled plasma
Etching ICP the AlGaN/GaN heterogenous junction epitaxy layer other than active area is removed, etching depth be greater than AlGaN potential barrier and
The thickness of GaN channel layer；
3) prepared by source-drain electrode: being realized in step 2) by negative-working photoresist technique and defines source-drain electrode gold on the active area of isolation
Belong to position and figure, source-drain electrode film is deposited by electron beam evaporation or magnetron sputtering；In nitrogen atmosphere, 800 DEG C or more
Temperature in anneal, so that source-drain electrode and AlGaN potential barrier is formed Ohmic contact；
4) first grid cvd dielectric layer: SiO is deposited on AlGaN/GaN heterogenous junction epitaxy layer2Film forms the first gate dielectric layer
For covering, the first gate dielectric layer with a thickness of 5-15nm；
5) second gate cvd dielectric layer: by magnetron sputtering on the first gate dielectric layer depositing metal oxide film；
6) medium removes: source-drain electrode region first layer medium, second layer dielectric layer being removed, source-drain electrode metal is exposed；First
It is rear to carry out medium removal by photoresist protection Region Medium in addition to source-drain electrode；
7) prepared by gate electrode: preparing gate electrode between source-drain electrode metal by electron beam evaporation or magnetron sputtering.
First layer metal chooses high work function material, and such as nickel metal, the conductions such as golden Au or titanium nitride TiN are can be used in second layer metal
Good, the stable metal of chemical property of property.
10. according to claim 9 have metal oxide/silica gatestack GaN base MOS-HEMT device method,
It is characterized in that, source-drain electrode film described in step 3) is made of Ti/Al metal system multiple layer metal, pass through stripping technology shape
At source-drain electrode metal wire；The Ti/Al metal system is Ti/Al/Ni/Au or Ti/Al/Ni/TiN；
The method that the step 6) medium removes is wet etching or dry etching；The solution that wherein wet etching uses is hydrogen fluorine
Acid or phosphoric acid etc.；The dry etching is sense coupling or reactive ion etching；
Gate electrode described in step 7) is made of double layer of metal, first layer metal select nickel metal, second layer metal select Au or
TiN。
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