CN108986728B

CN108986728B - Display apparatus

Info

Publication number: CN108986728B
Application number: CN201810558126.9A
Authority: CN
Inventors: 朴宗元; 金炫雄
Original assignee: Samsung Display Co Ltd
Current assignee: Samsung Display Co Ltd
Priority date: 2017-06-01
Filing date: 2018-06-01
Publication date: 2024-02-09
Anticipated expiration: 2038-06-01
Also published as: KR20180132200A; US20180350284A1; KR102391459B1; US10733922B2; CN108986728A

Abstract

The present invention relates to a display device. The display device includes: a substrate; pixels provided in a display region of the substrate; signal lines provided on the substrate and connected to the pixels; and a pad portion provided in the peripheral region and including a pad. The signal line includes a first crack detection line provided in the peripheral region and connected to the first test voltage pad, a first data line including a first end connected to the first crack detection line through a corresponding first transistor and a second end connected to a corresponding pixel among the pixels, and a first connection line for connecting the first data line and a pad corresponding to the first data line among the pads, and the first connection line is provided on one layer among at least two different layers.

Description

Display apparatus

Cross Reference to Related Applications

The present application claims priority and rights of korean patent application No. 10-2017-0068586 filed on the korean intellectual property agency on 1 month 6 of 2017, the entire contents of which are incorporated herein by reference.

Technical Field

The present disclosure relates to a display device.

Background

As the display device becomes reduced in size, reduced in weight, and thinner, it is required to improve durability of the display device with respect to a crack, scratch, or fracture phenomenon that may be generated by external impact.

The display device includes a display panel including pixels for displaying an image. When the display panel is broken, impurities such as moisture may penetrate into a display area of the display panel. Penetration of impurities through the cracks causes defects of the display panel. Therefore, it is becoming increasingly important to accurately detect whether the display panel is broken.

In addition to the pixels, a pad portion for inputting and outputting signals for controlling the operation of the display panel is formed on the display panel, and a connection line connected to the pad portion and transmitting signals is formed on the display panel.

When the pixels are arranged at a high density, the connection lines connected to the pad portions and transmitting signals are precisely formed, and thus adjacent connection lines are shorted with each other or the connection lines may be disconnected due to various process reasons, thereby causing defects. Therefore, it is important to accurately detect defects of the wires formed on the display panel.

The above information disclosed in the background section is only for enhancement of understanding of the background art and thus it may contain information that does not form the prior art that is already known to a person of ordinary skill in the art in this country.

Disclosure of Invention

Exemplary embodiments provide a display device for easily detecting defects of the display device caused by cracks.

Exemplary embodiments provide a display apparatus for detecting defects generated on connection lines of a display panel.

Exemplary embodiments provide a display apparatus for forming a circuit for detecting cracks and signal line defects in a narrow region on a substrate of a display panel.

Exemplary embodiments provide a display apparatus including: a substrate including a display region and a peripheral region provided in the vicinity of the display region; a plurality of pixels provided in a display region of the substrate; a plurality of signal lines provided on the substrate and connected to the plurality of pixels; and a pad portion provided in the peripheral region and including a plurality of pads. The plurality of signal lines include a first crack detection line provided in the peripheral region and connected to the first test voltage pad, a plurality of first data lines including a first end connected to the first crack detection line through a corresponding first transistor and connected to a second end of a corresponding pixel among the plurality of pixels, and a plurality of first connection lines for connecting the plurality of first data lines and pads corresponding to the plurality of first data lines among the plurality of pads, and the plurality of first connection lines are provided on one layer among at least two different layers.

The plurality of signal lines may further include a first test voltage line including a first terminal connected to the first test voltage pad and a second terminal connected to a second data line connected to a corresponding pixel among the plurality of pixels through the second transistor.

The first test voltage line may include a resistor having a resistance corresponding to a wire resistance of the first crack detection line.

The resistance of the resistor of the first test voltage line may be proportional to the wire resistance and the number of the first data lines, and may be inversely proportional to the number of the second data lines.

The plurality of signal lines may further include: a second crack detection line provided in the peripheral region and connected to the second test voltage pad; a plurality of third data lines including first ends connected to the second crack detection lines through the corresponding third transistors and second ends connected to corresponding pixels among the plurality of pixels; a plurality of second connection lines for connecting the plurality of third data lines and pads corresponding to the plurality of third data lines among the plurality of pads; and a second test voltage line including a first end connected to the second test voltage pad and a second end connected to a fourth data line, the fourth data line being connected to a corresponding pixel of the plurality of pixels through a fourth transistor, and a plurality of second connection lines being provided on a corresponding one of at least two different layers.

Two adjacent second data lines among the second data lines and two adjacent fourth data lines among the fourth data lines may be alternately disposed.

The plurality of signal lines may further include: a plurality of third connection lines for connecting the second data line and a pad corresponding to the second data line among the plurality of pads, and a plurality of fourth connection lines for connecting the fourth data line and a pad corresponding to the fourth data line among the plurality of pads, and the plurality of third connection lines and the plurality of fourth connection lines are provided on a corresponding one of at least two different layers.

Third connection lines connected to two adjacent second data lines among the plurality of third connection lines are provided on different layers.

In the first inspection mode, a first voltage corresponding to the black gray level may be configured to be applied to the first test voltage pad and the second test voltage pad, and in the second inspection mode, the first voltage may be configured to be applied to the first test voltage pad and a voltage corresponding to the white gray level may be configured to be applied to the second test voltage pad.

The plurality of signal lines may further include control lines connected to the gates of the first, second, third, and fourth transistors.

The first transistor, the second transistor, the third transistor, and the fourth transistor may be provided in a region among the pad, the first data line, the second data line, the third data line, and the fourth data line.

The first crack detection line may be a wire surrounding along an edge of the display area.

The first crack detection line may be a wire alternately reciprocated back and forth along one side of the display area.

Another embodiment provides a display apparatus including: a substrate including a display region and a peripheral region provided in the vicinity of the display region; a plurality of pixels provided in a display region of the substrate; and a plurality of signal lines provided on the substrate and connected to the plurality of pixels, wherein the plurality of signal lines include a plurality of data lines connected to the plurality of pixels, a first crack detection line provided in the peripheral region and configured to receive a black gray voltage, a second crack detection line provided in the peripheral region and configured to receive a white gray voltage, and a control line connected to a gate electrode of the first transistor and a gate electrode of the second transistor.

The display device may further include a plurality of data pads provided in the peripheral region, connected to the plurality of data lines, and configured to transmit data voltages applied to the plurality of pixels, wherein the first and second transistors are provided in regions between the plurality of data pads and the plurality of data lines.

The plurality of signal lines may further include first and second test voltage lines connected to third and fourth data lines among the plurality of data lines except the first and second data lines through third and fourth transistors.

The first test voltage line may include a resistor having a resistance corresponding to a wire resistance of the first crack detection line, and the second test voltage line may include a resistor having a resistance corresponding to a wire resistance of the second crack detection line.

The plurality of signal lines may further include a plurality of connection lines for connecting the plurality of data pads and the plurality of data lines.

The connection lines connected to adjacent data lines among the plurality of connection lines are provided on different layers.

The first and second crack detection lines may be wires that are looped along corresponding edges of the display area.

The display apparatus according to the exemplary embodiments may easily detect cracks and connection line defects of the display panel.

The display device according to the exemplary embodiment may provide a relatively wide display area on the display panel.

Drawings

Fig. 1 illustrates a top view of a display device according to an exemplary embodiment.

Fig. 2 illustrates a layout view of a display device according to an exemplary embodiment.

Fig. 3, 4 and 5 illustrate cross-sectional views of positions of connection lines of a display device according to an exemplary embodiment.

Fig. 6 illustrates a layout view of a display device according to an exemplary embodiment.

Fig. 7 illustrates a signal waveform diagram of a display device in a first detection mode according to an exemplary embodiment.

Fig. 8 shows a detailed waveform diagram of fig. 7.

Fig. 9 illustrates a display area of a display device when a test signal is applied in a first detection mode according to an exemplary embodiment.

Fig. 10 illustrates a signal waveform diagram of a display device in a second detection mode according to an exemplary embodiment.

Fig. 11 shows a detailed waveform diagram of fig. 10.

Fig. 12 illustrates a display area of the display device when a test signal is applied in the second detection mode according to an exemplary embodiment.

Fig. 13 shows a layout view of a display device according to another exemplary embodiment.

Fig. 14 illustrates a display area of a display device when a test signal is applied in a first detection mode according to another exemplary embodiment.

Fig. 15 illustrates a display area of a display device when a test signal is applied in a second detection mode according to another exemplary embodiment.

Detailed Description

The inventive concept will be described more fully hereinafter with reference to the accompanying drawings in which exemplary embodiments are shown. As will be recognized by those skilled in the art, the described embodiments may be modified in various different ways, all without departing from the spirit or scope of the inventive concept.

The drawings and description are to be regarded as illustrative in nature and not as restrictive, and like reference numerals indicate like elements throughout the description.

For better understanding and ease of description, the size and thickness of each component shown in the drawings are arbitrarily shown, but the embodiments are not limited thereto. In the drawings, the thickness of layers, films, panels, regions, etc. are exaggerated for clarity. The thickness of some layers and regions are exaggerated for better understanding and ease of description.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being "directly on" another element, there are no intervening elements present. The words "on …" or "above …" mean on or below the target portion and not necessarily on the upper side of the target portion based on the direction of gravity.

Unless explicitly described to the contrary, the word "comprise" and variations such as "comprises" or "comprising" will be understood to imply the inclusion of stated elements but not the exclusion of any other elements.

The phrase "on a plane" means that the target portion is viewed from the top, and the phrase "on a section" means that the target portion is viewed from the side in a vertically cut section.

A display device according to an exemplary embodiment will now be described with reference to fig. 1 and 2. Fig. 1 illustrates a top view of a display device according to an exemplary embodiment, and fig. 2 illustrates a layout view of the display device according to an exemplary embodiment.

Referring to fig. 1, the display device includes a substrate SUB, a display area DA for displaying an image, and a peripheral area NDA provided on an edge of the display area DA.

The substrate SUB is an insulating substrate comprising glass, polymer or stainless steel. The substrate SUB may be flexible, stretchable, foldable, bendable or crimpable. Thus, the display device may be flexible, telescopic, foldable, bendable or rollable. For example, the substrate SUB may have a form of a flexible film including a resin such as polyimide.

The peripheral area NDA is shown surrounding the display area DA in the illustrated exemplary embodiment, and the peripheral area NDA may be provided on one side or both sides of the display area DA.

As shown in fig. 2, the display device includes a display panel including a substrate SUB. The display panel includes a display area DA for displaying an image, and a peripheral area NDA provided in the vicinity of the display area DA, in which elements and/or signal lines for generating and/or transmitting various signals applied to the display area DA are arranged.

The data pad part DP, the test voltage pads VP1 and VP2, the test control pad TP, and the test transistors T1 To are provided in the peripheral area NDA.

The data pad portion DP is connected to the plurality of data lines D1-Dm in the display area DA, and corresponding data signals are supplied to the pixels P through the data pad portion DP. A printed circuit film, not shown, may be attached to the data pad portion DP, and a bump (bump) of the printed circuit film may be electrically connected to a pad of the data pad portion DP.

The data lines D1-Dm may be connected to the data pad portion DP through connection lines S1-Sm of the area SA. The connection lines S1 to Sm may be provided on the same layer as the data lines D1 to Dm or on different layers. When the connection lines S1 to Sm and the data lines D1 to Dm are provided on different layers, the connection lines S1 to Sm may be connected to the data lines D1 to Dm through the contact holes.

Further, the connection lines S1-Sm may be provided on different layers. For example, some of the connection lines S1-Sm may be provided on a first layer, and others of the connection lines S1-Sm may be provided on a second layer different from the first layer, S3, …, si, si+2, …, sj-1, sj+1, …, sm-2, sm. In this case, adjacent connection lines provided on the same layer may generate short-circuit defects.

These will now be described with reference to fig. 3 to 5. Fig. 3 to 5 illustrate cross-sectional views of positions of connection lines of a display device according to an exemplary embodiment.

As shown in fig. 3, adjacent connection lines may be provided on different layers. The connection lines S1, S3, and S5 are provided on the insulating layer 141. An insulating layer 180a is provided on the connection lines S1, S3, and S5 and the insulating layer 141. The connection lines S2 and S4 are provided on the insulating layer 180 a. An insulating layer 180b is provided on the insulating layer 180a and the connection lines S2 and S4. The insulating layers 180a and 180b may include an organic material.

In another way, as shown in fig. 4 and 5, adjacent connection lines may be provided on different layers or on the same layer. Referring to fig. 4, connection lines S1, S3, S4, and S6 are provided on the insulating layer 141. The insulating layer 180a is provided on the connection lines S1, S3, S4, and S6 and the insulating layer 141.

The connection lines S2 and S5 are provided on the insulating layer 180 a. An insulating layer 180b is provided on the insulating layer 180a and the connection lines S2 and S5. The insulating layers 180a and 180b may include an organic material.

Referring to fig. 5, connection lines S2 and S5 are provided on the insulating layer 141. An insulating layer 180a is provided on the connection lines S2 and S5 and the insulating layer 141. The connection lines S1, S3, S4, and S6 are provided on the insulating layer 180 a. The insulating layer 180b is provided on the insulating layer 180a and the connection lines S1, S3, S4, and S6. The insulating layers 180a and 180b may include an organic material.

Although not shown in fig. 3 to 5, a buffer layer may be further provided under the insulating layer 141, and at least one insulating layer including an organic material may be further provided over the insulating layer 180 b.

Referring To fig. 2, the test voltage pad VP1 is coupled To a first terminal of the test transistors T1, T2, …, tj-2, tj-1, …, to-3, to-2. The test voltage pad VP2 is coupled To a first terminal of the test transistor T3, T4, …, ti+1, ti+2, …, to-1, to. The same test voltage or different test voltages may be supplied to the test voltage pads VP1 and VP2 according to the detection mode.

The test control pad TP is connected To the gates of test transistors T1-To. The test control signal is supplied to the test control pad TP.

The test transistors T1 To are connected between the data lines D1 To Dm and the test voltage pads VP1 and VP2 in the peripheral area NDA.

The corresponding first crack detection line CD1 may be connected between a first end of some of the test transistors (e.g., ti-1 or Ti in the test transistors T1-To) and the test voltage pad VP 1. In a similar manner, a corresponding second crack detection line CD2 may be connected between a first end of some of the test transistors (e.g., tj or tj+1 of the test transistors T1-To) and a corresponding test voltage pad VP 2.

The first test voltage line ML1 may be connected between a first end of the test transistors T1, T2, …, tj-2, tj-1, …, to-3, to-2, which are not connected To the first crack detection line CD1, and the test voltage pad VP 1.

The second test voltage line ML2 may be connected between the first ends of the test transistors T3, T4, …, ti+1, ti+2, …, to-1, to and the test voltage pad VP2, which are not connected To the second crack detection line CD 2.

The first and second crack detection lines CD1 and CD2 may be conductive lines around the outside of the corresponding area of the display area DA.

For example, the first crack detection line CD1 may be provided to the outside of the left area of the display area DA, and the second crack detection line CD2 may be provided to the outside of the right area of the display area DA. Further, at least one of the first and second crack detection lines CD1 and CD2 may be provided to the outside of the upper region of the display area DA.

A configuration of a display device according to an exemplary embodiment will now be described with reference to fig. 6. Fig. 6 illustrates a layout view of a display device according to an exemplary embodiment.

As shown, the display device includes a display panel. The display panel includes a display area DA in which a plurality of pixels P are provided, and a peripheral area NDA provided in the vicinity of the display area DA.

The pixels P are exemplarily arranged in a matrix form in the display area DA of the display panel. The signal lines including the gate lines G1-Gn and the data lines D1-Dm are disposed in the display area DA. The gate lines G1-Gn may extend mainly in a row direction, and the data lines D1-Dm may extend mainly in a column direction crossing the row direction. Each pixel P may be connected to a corresponding gate line among the gate lines G1-Gn and a corresponding data line among the data lines D1-Dm to receive a gate signal and a data voltage from the signal line.

A driving device for generating and/or processing various signals for driving the display panel is provided in the peripheral area NDA. The driving apparatus includes a gate driver 20 for applying gate signals to the gate lines G1-Gn, a data driver, not shown, for applying data signals to the data lines D1-Dm, and a signal controller, not shown, for controlling the gate driver 20 and the data driver.

The gate driver 20 may be integrated with the display panel. The gate driver 20 may be provided on the right or left side of the display area DA. Unlike the illustrated exemplary embodiment, the gate driver 20 may be provided to the right and left sides of the display area DA, respectively, and may be electrically connected to the display panel as a tape carrier package TCP.

The data driver and the signal controller may be provided as a driving circuit chip. The driving circuit chip may be mounted on the display panel as an integrated circuit chip or may be electrically connected to the display panel as a tape carrier package TCP. The data driver and the signal controller may be formed as a single chip or separate chips.

In addition, the first slit detection line CD1, the second slit detection line CD2, the first test voltage line ML1, and the second test voltage line ML2 may be provided in the peripheral area NDA. The peripheral area NDA in which the first and second crack detection lines CD1 and CD2 are provided may be curved.

In detail, the data pads DP1 To DPo, the test voltage pads VP1 and VP2, the test control pad TP, and the test transistors T1 To may be provided in the peripheral area NDA, where o is a positive integer equal To or greater than m.

The data pads DP1-DPo are connected to the data lines D1-Dm by the connection lines S1-Sm of the area SA. Although not shown, the display device may further include a source driving IC, and in this case, the data pads DP1 to DPo are connected to the source driving IC. That is, the source driving ICs supply the data voltages to the data pads DP1 to DPo to supply the data voltages to the data lines D1 to Dm of the display device.

Test control pads TP1 and TP2 are connected To the gates of test transistors T1-To. The test control signal is supplied to the test control pads TP1 and TP2.

Test voltage pads VP1 and VP2 are connected to a first terminal of the test transistor. The test voltage pad VP1 may be connected To the test transistors T1, T2, …, tj-2, tj-1, …, to-3, to-2. The test voltage pad VP2 may be connected To the test transistors T3, T4, …, ti+1, ti+2, …, to-1, to.

The same test voltage or different test voltages may be supplied to the test voltage pads VP1 and VP2 according to the detection mode.

For example, in the first inspection mode, the same test voltage is supplied to the test voltage pads VP1 and VP2, and in the second inspection mode, different test voltages are supplied to the test voltage pads VP1 and VP2. The first detection mode represents a mode for detecting whether the connection lines S1 to Sm are broken and whether the first and second crack detection lines CD1 and CD2 are broken, and the second detection mode represents a mode for detecting whether a short circuit exists among the connection lines S1 to Sm. The test transistors T1 To may be provided in the peripheral area NDA. The test transistors T1 To may be provided between the display area DA and the data pads DP1 To DPo in the peripheral area NDA.

The test transistors T1 To are connected between the data lines D1 To Dm and the test voltage pads VP1 and VP 2. The gates TG of the test transistors T1-To are connected To the test control pads TP1 and TP2.

Each of the first terminals of the test transistors T1 To may be connected To one of the test voltage pads VP1 and VP2, and each of the second terminals may be connected To one of the connection lines S1 To Sm.

The corresponding first crack detection lines CD1 may be provided between the first ends of some of the test transistors Ti-1, ti and the corresponding test voltage pads VP 1. In a similar manner, the corresponding second crack detection line CD2 may be provided between the first ends of some of the test transistors Tj, tj+1 and the corresponding test voltage pad VP 2.

The first crack detection line CD1 may be provided between a first end of the test transistors Ti-1, ti connected to the data lines Di-1, di and the test voltage pad VP 1. The second crack detection line CD2 may be provided between the first ends of the test transistors Tj, tj+1 connected to the data lines Dj, dj+1 and the test voltage pad VP 2.

The first and second crack detection lines CD1 and CD2 may be provided in the peripheral area NDA provided to the outside of the display area DA.

The first and second crack detection lines CD1 and CD2 may be further provided outside the gate driver 20. The first crack detection line CD1 may be provided to surround the outer side of the left area of the display area DA, and the second crack detection line CD2 may be provided to surround the outer side of the right area of the display area DA.

The first crack detection line CD1 may include conductive lines alternately reciprocating back and forth along one side of the display area DA. For example, the first crack detection line CD1 may include a wire PA1 alternately reciprocating back and forth in the Y direction and a wire PA2 alternately reciprocating back and forth in the X direction.

The second crack detection line CD2 may include conductive lines alternately reciprocating back and forth along one side of the display area DA. For example, the second crack detection line CD2 may include a wire PA3 alternately reciprocating back and forth in the Y direction and a wire PA4 alternately reciprocating back and forth in the X direction.

The respective crack detection lines may each be a wire provided on a single layer or wires provided on a plurality of layers and connected to each other through contact holes, and may be provided to surround along the periphery of the display area DA, but they are not limited thereto.

Further, the resistors R1 and R2 may be further provided in the peripheral area NDA of the substrate SUB. The resistors R1 and R2 may be formed of the first test voltage line ML1 or the second test voltage line ML 2.

The resistor R1 may be formed to compensate for a voltage difference between a test voltage value applied to the data lines Di-1, di and a test voltage value applied to the data lines D1, D2, …, dj, dj+1, …, dm-3, dm-2, the voltage difference being generated by a wire resistance of the first crack detection line CD 1.

The resistor R2 may be formed to compensate for a voltage difference between the test voltage value applied to the data lines Dj, dj+1 and the test voltage value applied to the data lines D3, D4, …, di+1, di+2, …, dm-1, dm, the voltage difference being generated by the wire resistance of the second crack detection line CD 2.

That is, the resistor R1 may be connected To a first test voltage line ML1 for connecting a first end of the test transistors T1, T2, …, tj-2, tj-1, …, to-3, to-2, which is not connected To the first crack detection line CD1, with the test voltage pad VP 1. The resistor R2 may be connected To a second test voltage line ML2 for connecting a first end of the test transistors T3, T4, … ti+1, ti+2, … To-1, to, which is not connected To the second crack detector CD2, with the test voltage pad VP 2.

In this case, the deviation of the test voltage caused by the wire resistance of the first crack detection line CD1 may be minimized by designing the resistance of the resistor R1 using the wire resistance of the first crack detection line CD 1. For example, the resistance of the resistor R1 may be designed according to equation 1.

Equation 1

Where R is the resistance of resistor R1, R _CD Is the wire resistance of the first crack detection line CD1, k is the number of data lines connected to the first test voltage line ML1, and T is the number of data lines connected to the first crack detection line CD 1. In this case, 1.25 is a constant that can be changed to a positive integer greater than 0.

The resistor R1 may be designed by modifying the form of the first test voltage line ML1 in the region in which the first test voltage line ML1 is provided. For example, the resistor R1 satisfying the resistance calculated using equation 1 may be formed by controlling the thickness, length, or width of the first test voltage line ML 1.

The first test voltage line ML1 may be provided between a region in which the test voltage pad VP1 is provided and a region in which the first terminal of the test transistor T1 is provided, and thus it is easy to provide a region for arranging the conductive line of the resistor R1.

The design of the resistance of resistor R1 has been described and the resistance of resistor R2 can be designed in a similar manner.

It has been described in the illustrated exemplary embodiment that the data pads DP1 To DPo, the test control pads TP1, TP2, the test voltage pads VP1 and VP2, the test transistors T1 To, and the resistors R1 and R2 are provided at the lower portion of the peripheral area NDA, but the arrangement of the signal lines, the pad portions, the transistors, and the resistors in the peripheral area NDA is not limited thereto.

Fig. 7 shows voltages V1 and V2 applied to the test voltage pads VP1 and VP2, gate signals G [1] -Gn applied to the gate lines G1-Gn, and test control signals TS applied to the test control pads TP1 and TP 2.

Referring to fig. 7, the voltages V1 and V2 applied to the test voltage pads VP1 and VP2 are maintained at the high level voltage H for a period t1-tn during which the test control signal TS has the enable level L1. Hereinafter, the high level voltage H will correspond to black gray.

When the test control signal TS is at the enable level L1, the test transistors T1-To may be turned on. The voltages generated by the test voltages V1 and V2 may be supplied To the data lines D1-Dm through the turned-on test transistors T1-To.

For periods t1-tn, the gate signals G [1] -G [ n ] may be sequentially changed to the enable level L1, in which period t1-tn the test control signal TS is at the enable level L1. For example, the gate signal G [1] changes to the enable level L1 at time t1 and to the inactive level H1 at time t2, and the gate signal G [2] changes to the enable level L1 at time t 2.

When the gate signals G1[1] -gn are supplied to the pixel P, voltages corresponding to the test voltages V1 and V2 may be programmed to the pixel P. The pixel P expresses black gray by a voltage programmed to the pixel P.

Hereinafter, a test method of the display device in the first detection mode according to an exemplary embodiment will now be described with reference to fig. 7, 8, and 9.

Fig. 8 illustrates a detailed waveform diagram of fig. 7, and fig. 9 illustrates a display area of a display device when a test signal is applied in a first detection mode according to an exemplary embodiment.

As shown in fig. 8, when the gate signal G [ n ] changes to the enable level L1 in a period from the time tn-1 to the time tn, the voltage at the first high level VH may be applied to the data lines D1 and D2.

The high level voltage H may be reduced to a voltage at the first high level VH, for example, 6.5V, through the resistor R1, and may be transmitted to the data lines D1 and D2. The pixels connected to the data lines D1 and D2 may express black gray by a voltage at the first high level VH.

Further, the high level voltage H may drop to a voltage at the second high level VH1, for example, 6.7V, through the first crack detection line CD1, and may be transmitted to the data lines Di-1, di. The pixels connected to the data line Di-1 and the data line Di may express black gray by a voltage at the second high level VH 1.

In the first detection mode, when the display device is broken, the first and second crack detection lines CD1 and CD2 may be disconnected, or the resistances of the first and second crack detection lines CD1 and CD2 may be increased. Further, when at least one of the connection lines S1 to Sm is disconnected, the wire resistance of the at least one disconnected connection line may increase.

For example, when the display device breaks to disconnect the second crack detection line CD2, the test voltage at the high level voltage H is not transmitted to the data lines Dj, dj+1 for a period from the time tn-1 to the time tn. The pixels connected to the data lines Dj, dj+1 exhibit white to light gray by a voltage at a level VM2 lower than the voltage at the second high level VH 1. That is, a strong bright line can be seen through the pixels connected to the data lines Dj, dj+1.

For another example, when the display device breaks to increase the wire resistance of the first crack detection line CD1, the voltage transmitted to the data lines Di-1, di has a voltage at the level VM1 lower than the voltage at the second high level VH1 for a period from the time tn-1 to the time tn by a voltage drop caused by the wire resistance increase.

The pixels connected to the data lines Di-1, di exhibit gray scales by a voltage at a level VM1 lower than a voltage at the second high level VH 1. That is, the weak bright line may be visible through the pixels connected to the data lines Di-1, di. In this case, the degree of increase in the wire resistance of the first crack detection line CD1 may be smaller than that caused by the disconnection of the second crack detection line CD2, and thus the level VM1 may have a voltage greater than that of the level VM 2. However, this is an example for illustration, and the exemplary embodiments are not limited thereto.

For another example, when the connection line Sm-1 of the connection lines S1-Sm is disconnected, the test voltage at the high level voltage H is not transmitted to the data line Dm-1 for a period from the time tn-1 to the time tn. The pixel connected to the data line Dm-1 exhibits a white gray to a light gray by a voltage at a level VM3 lower than the voltage at the first high level VH. That is, the bright line is visible through the pixels connected to the data line Dm-1.

The period from time tn-1 to time tn during which the gate signal G [ n ] at the enable level L1 is supplied to the gate line Gn has been described, and the above-mentioned description may be equally applicable to the period from time t1 to time tn-1 during which the gate signals G [1] -G [ n-1] at the enable level L1 are supplied to the gate line G1-Gn-1.

As shown in fig. 9, the pixels connected to the data lines Di-1, di receiving the test voltage through the first slit detection line CD1 exhibit gray scales, and thus they may be visible as weak bright lines shown with dotted lines. It can thus be determined that a minute crack is generated in the region in which the first crack detection line CD1 is provided in the peripheral region NDA.

The pixels connected to the data lines Dj, dj+1 receiving the test voltage through the second slit detection line CD2 exhibit white gray scales, and thus they may be visible as strong bright lines shown with solid lines. It can thus be determined that a region in which the second crack detection line CD2 is provided in the peripheral region NDA generates a considerable crack.

The pixel connected to the data line Dm-1 receiving the test voltage through the connection line Sm-1 exhibits white gray, and thus it can be seen as a strong bright line shown with a solid line. It can thus be determined that the connection line Sm-1 in the peripheral area NDA is disconnected.

As described above, according to an exemplary embodiment, it may be determined whether a display device may have a defect by using the following characteristics: in the first detection mode, the voltage programmed to the corresponding pixel is different according to the disconnection of the connection lines S1 to Sm or the change of the wire resistance, or according to the disconnection of the crack detection lines CD1 and CD2 formed outside the display area DA or the change of the wire resistance.

Fig. 10 illustrates a signal waveform diagram of a display device in a second detection mode according to an exemplary embodiment. Fig. 10 shows voltages V1 and V2 applied to the test voltage pads VP1 and VP2, gate signals G [1] -Gn applied to the gate lines G1-Gn, and a test control signal TS applied to the test control pads TP1 and TP 2.

Referring to fig. 10, for a period t1-tn during which the test control signal TS has an enable level L1, the voltage V1 applied to the test voltage pad VP1 is maintained at the voltage L at a low level and the voltage V2 applied to the test voltage pad VP2 is maintained at the voltage H at a high level. Hereinafter, the voltage L at the low level corresponds to white gray.

When the test control signal TS is at the enable level L1, the test transistors T1-To may be turned on. The voltages corresponding To the test voltages V1 and V2 may be supplied To the data lines D1-Dm through the turned-on test transistors T1-To.

For a period t1-tn, the gate signals G [1] -G [ n ] may sequentially change to the enable level L1, during which the test control signal TS has the enable level L1. For example, the gate signal G [1] changes to the enable level L1 at time t1, and it changes to the inactive level H1 at time t 2. The gate signal G [2] then changes to the enable level L1 at time t 2.

When the gate signals G [1] -gn are supplied to the pixels P, the voltage VL generated by the test voltage V1 at the low level L is programmed to some pixels to thereby represent white gray, and the voltage VH generated by the test voltage V2 at the high level voltage H is programmed to some pixels to thereby represent black gray.

In fig. 6, the data lines D1-Dm are alternately connected to the test voltage pads VP1 or VP2, and thus the entire display area DA may be visible as an intermediate gray between white gray and black gray.

Hereinafter, a method for testing a display device in a second detection mode according to an exemplary embodiment will be described in detail with reference to fig. 10, 11, and 12.

Fig. 11 illustrates a detailed waveform diagram of fig. 10, and fig. 12 illustrates a display area of the display device when a test signal is applied in the second detection mode according to an exemplary embodiment.

As shown in fig. 11, when the gate signal G [ n ] changes to the enable level L1 in a period from the time tn-1 to the time tn, a voltage generated by a voltage at the low level L may be applied to the data lines D1, D2, …, di-1, di, …, dj-2, dj-1, …, dm-3, dm-2 connected to the test voltage pad VP 1.

For example, the voltage at the low level L may be reduced by the resistor R1 to the voltage at the first low level VL and may be transferred to the data lines D1, D2, …, dj-2, dj-1, …, dm-3, dm-2. Further, the voltage at the low level L may be dropped through the first crack detection line CD1, and may be transferred to the data lines Di-1, di. The pixels connected to the data lines D1, D2, …, di-1, di, …, dj-2, dj-1, …, dm-3, dm-2 may exhibit white gray scale by voltages at the low level L.

When the gate signal G [ n ] changes to the enable level L1 in a period from the time tn-1 to the time tn, a voltage generated by a voltage at the high level voltage H may be applied to the data lines D3, D4, …, di+1, di+2, …, dj, dj+1, …, dm-1, dm connected to the test voltage pad VP 2.

For example, the voltage at the high level voltage H may be reduced to the voltage at the first high level VH through the resistor R2, and may be transferred to the data lines D3, D4, …, di+1, di+2, …, dm-1, dm. Further, the voltage at the high level voltage H may be dropped through the second crack detection line CD2, and may be transmitted to the data lines Dj, dj+1. The pixels connected to the data lines D3, D4, …, di+1, di+2, …, dj, dj+1, …, dm-1, dm may represent black gray by voltages at the high level voltage H.

For the period from time tn-1 to time tn, the test voltage at the low level L is transmitted to the connection line S2 through the resistor R1, and the test voltage at the high level voltage H is transmitted to the connection line S4 through the resistor R2.

When a short circuit is generated between the connection lines S2 and S4 provided adjacent to each other on the same layer, a voltage VM4 between the voltages VH, VL transmitted to the two connection lines S2 and S4 may be applied to the data lines D2 and D4. The pixels connected to the data lines D2 and D4 represent deep gray to black gray by the voltage of the voltage VM 4. The pixel connected to the data line D3 exhibits black gray by the voltage at the first high level VH.

That is, as shown in fig. 12, the pixels connected to the three continuous data lines D2, D3, and D4 represent black gray scale or deep gray scale, and thus the region corresponding to the relevant pixel may be visible as a deep line. It can thus be determined that a short circuit is generated between the connection line S2 and the connection line S4.

As described above, the exemplary embodiment can determine whether the display device has a defect by using the fact that the voltage applied to the corresponding pixel is changed by the short circuit of the connection lines S1 to Sm in the second detection mode.

A configuration of a display device according to another exemplary embodiment will now be described with reference to fig. 13.

Fig. 13 shows a layout view of a display device according to another exemplary embodiment. The configuration of the display device corresponds To the display device of fig. 6 according To the exemplary embodiment except for the access structures of the test transistors T1 To and the crack detection lines CD1 and CD2 of fig. 13, and the first and second test voltage lines ML1 and ML2, and thus an explanation of the configuration will not be provided.

The first crack detection line CD1 may be provided between the first ends of some of the test transistors T1 To 1, ti, ti+3, ti+4 and the corresponding test voltage pad VP 1.

The second crack detection line CD2 may be provided between the first ends of some of the test transistors Tj-4, tj-3, tj, tj+1 and the corresponding test voltage pad VP 2.

A first end of the test transistors Ti-1, ti, ti+3, ti+4 may be connected to the first crack detection line CD1, and a first end of the test transistors Tj-4, tj-3, tj, tj+1 may be connected to the second crack detection line CD2.

That is, one crack detection line may be connected to the first ends of a plurality of corresponding test transistors, as compared to the exemplary embodiment shown in fig. 6.

In this case, as represented in equation 1, the value of T increases and the value of k decreases, so the resistance of the resistor R1 or the resistor R2 may increase compared to the exemplary embodiment shown in fig. 6. When the resistance of the resistor R1 increases, the resistor R1 may be designed by changing the form of the resistor R1 in the region in which the first test voltage line ML1 is provided. The first test voltage line ML1 may be provided in a region between a region in which the test voltage pad VP1 is provided and a region in which the first end of the test transistor T1 is provided, and thus it is easy to obtain a region for arranging the wires of the resistor R1.

A method for designing the resistance of the resistor R1 has been described, and the resistance of the resistor R2 can be designed in a similar manner.

The display device described with reference to fig. 13 may be driven by the signals described with reference to fig. 7 and 10. A method for detecting defects of the display device will now be described with reference to fig. 14 and 15.

Fig. 14 illustrates a display area of a display device when a test signal is applied in a first detection mode according to another exemplary embodiment, and fig. 15 illustrates a display area of a display device when a test signal is applied in a second detection mode according to another exemplary embodiment.

The display device may be driven in the first detection mode by the signals shown in fig. 7. As shown in fig. 14, the pixels connected to the data lines Di-1, di, di+3, di+4 receiving the test voltage through the first crack detection line CD1 exhibit light gray scales, and thus they may be visible as weak bright lines shown with dotted lines. It can thus be determined that minute cracks are generated in the region in which the first crack detection line CD1 is provided in the peripheral region NDA.

The pixels connected to the data lines Dj-4, dj-3, dj, dj+1 receiving the test voltages through the second slit detection line CD2 exhibit white gray scales, and thus they may be visible as strong bright lines shown with solid lines. It can thus be determined that a considerable crack is generated in the region in which the second crack detection line CD2 is provided in the peripheral region NDA.

The pixels connected to the data line Dm-1 receiving the test voltage through the connection line Sm-1 exhibit white gray scale, and thus are visible as strong bright lines shown with solid lines. It can thus be determined that the connection line Sm-1 in the peripheral area NDA is disconnected.

As described above, according to another exemplary embodiment, whether a display device may have a defect may be determined by using the following characteristics: in the first detection mode, the voltage programmed to the corresponding pixel is different according to the disconnection of the connection lines S1 to Sm or the change of the wire resistance, or according to the disconnection of the crack detection lines CD1 and CD2 formed outside the display area DA or the change of the wire resistance.

The display device may be driven in the second detection mode by the signals shown in fig. 10. As shown in fig. 15, the pixels connected to the three consecutive data lines Dm-3, dm-2, and Dm-1 represent black gray scale or deep gray scale, and thus the area corresponding to the relevant pixels can be seen as a deep line. It was thus confirmed that a short circuit was generated between the connection line Sm-3 and the connection line Sm-1.

While the inventive concept has been described in connection with what is presently considered to be practical exemplary embodiments, it is to be understood that the inventive concept is not to be limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

Claims

1. A display device, comprising:

a substrate including a display region and a peripheral region provided in the vicinity of the display region;

a plurality of pixels provided in the display region of the substrate;

a plurality of signal lines provided on the substrate and connected to the plurality of pixels; and

a pad portion provided in the peripheral region and including a plurality of pads,

wherein the plurality of signal lines includes:

a first crack detection line provided in the peripheral region and connected to a first test voltage pad,

a plurality of first data lines including a first end connected to the first crack detection line through a corresponding first transistor and a second end connected to a corresponding pixel among the plurality of pixels, an

A plurality of first connection lines for connecting the plurality of first data lines and pads corresponding to the plurality of first data lines among the plurality of pads, an

The plurality of first connection lines are provided on one layer among at least two different layers,

wherein the plurality of signal lines further comprises:

a first test voltage line including a first terminal connected to the first test voltage pad and a second terminal connected to a second data line connected to a corresponding pixel among the plurality of pixels through a second transistor,

wherein the first test voltage line is connected between the first end of the second transistor which is not connected to the first crack detection line and the first test voltage pad, and

wherein the plurality of first data lines and the plurality of second data lines are data lines different from each other.

2. The display device of claim 1, wherein:

the first test voltage line includes a resistor having a resistance corresponding to a wire resistance of the first crack detection line.

3. The display device of claim 2, wherein:

The resistance of the resistor of the first test voltage line is proportional to the wire resistance and the number of the first data lines, and inversely proportional to the number of the second data lines.

4. The display device of claim 1, wherein:

the plurality of signal lines further includes:

a second crack detection line provided in the peripheral region and connected to a second test voltage pad;

a plurality of third data lines including first ends connected to the second crack detection lines through corresponding third transistors and second ends connected to corresponding pixels among the plurality of pixels;

a plurality of second connection lines for connecting the plurality of third data lines and pads corresponding to the plurality of third data lines among the plurality of pads; and

a second test voltage line including a first end connected to the second test voltage pad and a second end connected to a fourth data line connected to a corresponding pixel among the plurality of pixels through a fourth transistor, and

the plurality of second connection lines are provided on a corresponding one of the at least two different layers.

5. The display device of claim 4, wherein:

two adjacent second data lines among the second data lines and two adjacent fourth data lines among the fourth data lines are alternately arranged.

6. The display device of claim 5, wherein:

the plurality of signal lines further includes:

a plurality of third connection lines for connecting the second data line and a pad corresponding to the second data line among the plurality of pads, and a plurality of fourth connection lines for connecting the fourth data line and a pad corresponding to the fourth data line among the plurality of pads, and

the plurality of third connection lines and the plurality of fourth connection lines are provided on a corresponding one of the at least two different layers.

7. The display device of claim 4, wherein:

in a first detection mode, a first voltage corresponding to black gray is configured to be applied to the first test voltage pad and the second test voltage pad, and

in a second inspection mode, the first voltage is configured to be applied to the first test voltage pad and a voltage corresponding to a white gray scale is configured to be applied to the second test voltage pad.

8. The display device of claim 4, wherein:

the plurality of signal lines further includes a control line connected to the gate of the first transistor, the gate of the second transistor, the gate of the third transistor, and the gate of the fourth transistor.

9. The display device of claim 4, wherein:

the first transistor, the second transistor, the third transistor, and the fourth transistor are provided in a region among the pad, the first data line, the second data line, the third data line, and the fourth data line.