CN108983645A - Train and for the multichannel I/O output control system of train, method - Google Patents
Train and for the multichannel I/O output control system of train, method Download PDFInfo
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0428—Safety, monitoring
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2603—Steering car
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/26—Pc applications
- G05B2219/2637—Vehicle, car, auto, wheelchair
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- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
The invention discloses a kind of train and for the multichannel I/O output control system of train, method, wherein, system includes: multiple secure hardware circuits, FPGA logic cell and control unit, it is in communication with each other between control unit and FPGA logic cell, wherein, control unit sends control information to FPGA logic cell, wherein control information includes command information and address information；FPGA logic cell includes multiple output channels, each output channel is correspondingly connected with a secure hardware circuit, FPGA logic cell is used to generate corresponding driving signal according to command information, and decoding processing is carried out to address information and exports driving signal to corresponding secure hardware circuit to obtain one in multiple output channels, and by the output channel of acquisition.The system can be realized the control of multiple-channel output, reduce the load of control unit, improve the speed of service and stability of control system, and at low cost, flexibility, good reliability.
Description
Technical field
The present invention relates to Train Control Technology fields, and in particular to a kind of multichannel I/O output control system for train,
A kind of train and a kind of multichannel I/O output control method for train.
Background technique
With the fast development of track transportation industry, the safety control system of entire industry is increasingly by the weight of people
Depending on.Such as safe IO output control system, it include hardware circuit control and software control in the system, and software control combines
Hardware circuit control is a kind of control mode that track transportation industry is popular instantly.
Currently, safe I/O output control generally carries out security control to output port using impulse level, pulse signal by
The control terminal of MCU (Micro Control Unit, micro-control unit) issues, and hardware circuit is input to, to reach to output
The security control of port.
However, existing safe IO output control method is confined to a small amount of IO output control, once to realize multichannel I/O
Output control just will increase the load of MCU, can occupy a large amount of logical resources, limit the speed of service of MCU.If passing through multiple groups
Circuit controls to realize that multichannel I/O is exported, then will increase the cost designed and developed.
Summary of the invention
The present invention is directed to solve one of the technical problem in above-mentioned technology at least to a certain extent.
For this purpose, the first purpose of this invention is to propose a kind of multichannel I/O output control system for train, this is
System can be realized the control of multiple-channel output, reduces the load of control unit, improves the speed of service and stability of control system, and
It is at low cost, flexibility, good reliability.
Second object of the present invention is to propose a kind of train.
Third object of the present invention is to propose a kind of multichannel I/O output control method for train.
In order to achieve the above objectives, first aspect present invention embodiment proposes a kind of multichannel I/O output control for train
System processed, comprising: multiple secure hardware circuits, FPGA (Field-Programmable Gate Array, field programmable gate
Array), logic unit and control unit, be in communication with each other between described control unit and the FPGA logic cell, wherein
Described control unit sends control information by being communicated with the FPGA logic cell to the FPGA logic cell,
In, the control information includes command information and address information；The FPGA logic cell includes multiple output channels, each defeated
Access is correspondingly connected with to a secure hardware circuit out, and the FPGA logic cell according to the command information received for generating
Corresponding driving signal, and decoding processing is carried out to obtain one in the multiple output channel progress to the address information
Output, and exported the driving signal of generation to corresponding secure hardware circuit by the output channel of acquisition.
Multichannel I/O output control system according to an embodiment of the present invention for train, is designed based on FPGA, makes to control
Unit processed carries out drive control to multiple secure hardware circuits by the inclusion of the FPGA logic cell of multiple output channels, realizes
The control of multichannel I/O output can provide safeguard in safe work state for secure hardware circuit, while improve entire control
The speed of service, stability and the reliability of system processed, and it is at low cost.
Further, the invention proposes a kind of trains comprising the multichannel I/O for train of above-described embodiment is exported
Control system.
The train of the embodiment of the present invention, it is defeated using the multichannel I/O for train based on FPGA design of above-described embodiment
Control system out carries out control unit to multiple secure hardware circuits by the inclusion of the FPGA logic cell of multiple output channels
Drive control realizes the control of multichannel I/O output, can provide safeguard for secure hardware circuit in safe work state,
The speed of service, stability and reliability of entire control system are improved simultaneously, and at low cost.
In order to achieve the above objectives, third aspect present invention embodiment proposes a kind of multichannel I/O output control for train
Method processed, comprising the following steps: FPGA logic cell receives control information, wherein the control information include command information with
Address information；The FPGA logic cell generates corresponding driving signal according to the command information received, and to the address
Information is carried out decoding processing and is exported with one obtained in the multiple output channel；The FPGA logic cell is by obtaining
The output channel taken exports the driving signal of generation to corresponding secure hardware circuit.
Multichannel I/O output control method according to an embodiment of the present invention for train, is designed based on FPGA, is passed through
FPGA logic cell comprising multiple output channels carries out drive control to multiple secure hardware circuits, and it is defeated to realize multichannel I/O
Control out can provide safeguard in safe work state for secure hardware circuit, while improve entire control system
The speed of service, stability and reliability, and it is at low cost.
The additional aspect of the present invention and advantage will be set forth in part in the description, and will partially become from the following description
Obviously, or practice through the invention is recognized.
Detailed description of the invention
Above-mentioned and/or additional aspect of the invention and advantage will become from the description of the embodiment in conjunction with the following figures
Obviously and it is readily appreciated that, in which:
Fig. 1 is the block diagram of the multichannel I/O output control system for train of embodiment according to the present invention；
Fig. 2 is the block diagram of FPGA logic cell according to an embodiment of the invention；
Fig. 3 is the control stream of the multichannel I/O output control system for train of a specific example according to the present invention
Cheng Tu；
Fig. 4 is the block diagram of the train of embodiment according to the present invention；
Fig. 5 is the flow chart of the multichannel I/O output control method according to an embodiment of the invention for train；
Fig. 6 is the flow chart of the one according to the present invention exemplary multichannel I/O output control method for train；
Fig. 7 is the flow chart of the multichannel I/O output control method for train according to another embodiment of the invention.
Specific embodiment
The embodiment of the present invention is described below in detail, examples of the embodiments are shown in the accompanying drawings, wherein from beginning to end
Same or similar label indicates same or similar element or element with the same or similar functions.Below with reference to attached
The embodiment of figure description is exemplary, it is intended to is used to explain the present invention, and is not considered as limiting the invention.
Below with reference to the accompanying drawings the train of the embodiment of the present invention is described and for the multichannel I/O output control system of train, side
Method.
Fig. 1 is the block diagram of the multichannel I/O output control system according to an embodiment of the present invention for train.Such as Fig. 1 institute
Show, which includes: multiple secure hardware circuits 10, FPGA logic cell 20 and control
Unit 30 processed, is in communication with each other between control unit 30 and FPGA logic cell 20.
Wherein, control unit 30 sends control letter by being communicated with FPGA logic cell 20 to FPGA logic cell 20
Breath, wherein control information includes command information and address information.FPGA logic cell 20 includes multiple output channels 21, each
Output channel is correspondingly connected with to a secure hardware circuit, and FPGA logic cell 20 according to the command information received for generating
Corresponding driving signal, and decoding processing is carried out to address information and is exported with one obtained in multiple output channels, with
And the driving signal of generation is exported to corresponding secure hardware circuit 10 by the output channel of acquisition.
In an embodiment of the present invention, FPGA logic cell 20 can have Parallel I/O Interface, and FPGA logic cell 20 can
To realize two-way communication by Parallel I/O Interface and control unit 30.
It is possible to further which sequence circuit corresponding with Parallel I/O Interface is arranged in FPGA logic cell 20, FPGA is patrolled
Collect the control information that unit 20 can be sent according to the sequence circuit reception control unit.
Specifically, as shown in Figure 1, FPGA logic cell 20 is powered on into after operating mode, control unit 30 is patrolled to FPGA
It collects unit 20 and sends the control information comprising address information and command information, such as control train deceleration, FPGA logic cell 20 leads to
It crosses Parallel I/O Interface and corresponding sequence circuit receives control information, and then can be generated according to the command information received corresponding
Driving signal, such as drive the driving signal of train deceleration, and it is logical to obtain multiple outputs to carry out decoding processing to address information
One in road 21, output channel such as corresponding with train speed control circuit is exported, and then the output by obtaining is logical
Road exports the train deceleration driving signal of generation to train speed control circuit, to drive the execution of train speed control circuit to subtract
Speed instruction.
Optionally, if control unit 30 sends multiple control information, and each control to FPGA logic cell 20 simultaneously
Address information in information is different, or sends the control information comprising multiple and different address informations, then fpga logic list
Member 20 can carry out decoding processing to obtain multiple output channels (such as output channel 21a-21c), such as to different address informations
Fruit generates corresponding driving signal according to the command information received, then can be by output channel 21a-21c by generation
Driving signal is sent to corresponding secure hardware circuit 10a-10c.
Hereby it is achieved that the control of multichannel I/O output, reduces the load of control unit, improves the fortune of control system
Scanning frequency degree and stability, and at low cost, flexibility, good reliability.
In one embodiment of the invention, as shown in Fig. 2, FPGA logic cell 20 can also include: logic judgment electricity
Road 22, self-test logic circuit 23 and driving circuit 24.
Wherein, logic judgment module 22 is used to carry out address information decoding processing to obtain one in multiple output channels
It is a to be exported, and whether decision instruction information is output drive signal or shutdown driving signal, and is judging control instruction
To export the first enable signal when output drive signal, the enabled letter of output second when judging control instruction for shutdown driving signal
Number.Self-test logic circuit 23 is connected with logic judging circuit 22, and self-test logic circuit 23 includes self-test timer, self-test logic electricity
Road 23 is used for the control self-test timer when logic judging circuit 22 exports the first enable signal and starts timing, and sentences in logic
Control self-test timer stops timing when deenergizing 22 exports the second enable signal.Driving circuit 24 and 22 phase of logic judging circuit
Even, driving circuit 24 is used to generate driving signal when logic judging circuit 22 exports the first enable signal, and passes through acquisition
Output channel exports the driving signal of generation to corresponding secure hardware circuit, and exports second in logic judging circuit 22
Stop generating driving signal when enable signal.
Optionally, the driving signal that driving circuit 24 generates can be the impulse level signal of fixed frequency.
Specifically, after control unit 20 sends control information to FPGA logic cell 20, logic judgment module 22 can pass through
Parallel I/O Interface sequence circuit receives the control information, so can control the address information in information carry out decoding processing with
It obtains one in multiple output channels to be exported, and judges whether the command information controlled in information is output drive signal
Or shutdown driving signal.
In an example of the invention, the first enable signal is exported when decision instruction information is output drive signal,
Such as the pulse signal of a clock cycle, which will enable the self-test timer in self-test logic circuit 23 and start to count
When, and enabled driving circuit 24 exports the impulse level signal of fixed frequency, and then can be consolidated this by the output channel of acquisition
The impulse level signal for determining frequency is exported to corresponding secure hardware circuit.
Further, a control signal, and the instruction in the control signal are received again in logic judgment module 22
When information is shutdown driving signal, self-test timer stops timing, and driving circuit 24 stops generating driving signal, and then stops
To 20 output drive signal of secure hardware circuit.At this point, FPGA logic cell 20 and then original operating state, that is, power on etc. to be controlled
Unit 30 processed sends control information again.
Further, FPGA logic cell 20 can also include clock circuit, which can be fpga logic list
Other each circuits in member 20 provide reliable and stable such as logic judging circuit 22, self-test logic circuit 23 and driving circuit 24
Clock signal.
In one embodiment of the invention, logic judging circuit 22 is also used to judge whether to connect every the first preset time
The command information of output drive signal is received, and in the command information for receiving output drive signal, the enabled letter of output first
Number.Wherein, self-test logic circuit 23 is also used to control the zero setting of self-test timer when receiving the first enable signal every time and lay equal stress on
New timing.
For example, t0 moment, logic judging circuit 22 receive the command information of output drive signal, self-test timer
Start timing, driving circuit 24 generates driving signal, and is sent to the driving signal of generation pair by the output channel of selection
The secure hardware circuit answered.T1 moment, self-test timer timing time are t1-t0, and t1-t0 < Δ t, wherein Δ t is first
Preset time, logic judging circuit 22 receives the command information of output drive signal again at this time, then in t0+ time Δt, certainly
Timer zero setting and reclocking are examined, driving circuit 24 continues to output driving signal, and will generate by the output channel of selection
Driving signal be sent to corresponding secure hardware circuit.T2 moment, self-test timer timing time are t2-t0- Δ t, and t2-
T0- Δ t < Δ t, logic judging circuit 22 receives again the command information of output drive signal at this time, then in t0+2 Δ t
Moment, the zero setting of self-test timer and reclocking, driving circuit 24 continue to output driving signal, and the output channel for passing through selection
The driving signal of generation is sent to corresponding secure hardware circuit, and so on.
In another embodiment of the present invention, self-test logic circuit 23 is also used to not receive in logic judging circuit 22
To output drive signal command information when, judge whether the timing time of self-test timer reaches the second preset time, and
The timing time of self-test timer generates shutdown pulse signal when reaching the second preset time, and will turn off output of pulse signal extremely
Logic judging circuit 22.Wherein, logic judging circuit 22 is also used to according to shutdown output of pulse signal third enable signal to drive
Dynamic circuit 24, so that driving circuit 24 stops generating driving signal.
Wherein, the second preset time is greater than the first preset time.
For example, t0 moment, logic judging circuit 22 receive the command information of output drive signal, self-test timer
Start timing, driving circuit 24 generates driving signal, and is sent to the driving signal of generation pair by the output channel of selection
The secure hardware circuit answered.T0+ time Δt, self-test timer timing time are Δ t, and logic judging circuit 22 is without again at this time
Secondary to receive command information, self-test timer continues timing, and driving circuit 24 continues to output driving signal.When self-test timer
When timing time reaches the second preset time Δ t ', wherein Δ t ' > Δ t, self-test logic circuit 23 generate shutdown pulse signal,
Such as the pulse signal of a clock cycle, logic judging circuit 22 is according to the output of pulse signal third enable signal, so as to drive
Dynamic circuit 24 stops generating driving signal, and then stops to 20 output drive signal of secure hardware circuit, and self-test timing at this time
Device zero setting simultaneously stops timing.
In an embodiment of the present invention, as shown in Fig. 2, FPGA logic cell 20 can also include multiple input ports, such as
First input end and the second input terminal, wherein first input end can connect external crystal oscillation circuit, to receive external crystal oscillation circuit
The oscillator signal of output, to provide clock input signal for FPGA logic cell 20；Second input terminal can connect reset circuit, use
To receive the reset signal of reset circuit output, to provide reseting input signal for FPGA logic cell 20.
In addition, in one embodiment of the invention, the signal that logic judging circuit 22 and self-test logic circuit 23 export
It can also be transmitted to control unit 30, so that control unit 30 obtains the output state of a control of control system.
Further, which can also include display unit, the display unit
It can be connected with control unit, and then control unit 30 can control the state of a control of display unit display control program, make as a result,
The control situation for obtaining multichannel I/O output control system is more intuitive, convenient for the control to multichannel I/O output control system.
The multichannel I/O output control system for train of the embodiment of the present invention for ease of understanding, can pass through following example
It is illustrated:
Referring to Fig. 3, FPGA logic cell 20 is powered on into after operating mode, is received and is included ground from control unit 30
After location information, the control information of command information, logic judging circuit 22 will carry out logic to address information, command information and sentence
It is disconnected, i.e., decoding judgement is carried out to address information, with the defeated of the impulse level signal (i.e. driving signal) of selection output fixed frequency
Access out, thus, it can be achieved that control to output channel；And decision instruction information is that output drive signal is also off driving letter
Number, to determine whether to export or turn off driving signal.
If command information is expressed as output drive signal, driving circuit 24 will generate driving signal, and pass through choosing
That selects exports the driving signal of generation output channel to corresponding secure hardware circuit, while self-test timer starts to count
When.If command information is expressed as shutdown driving signal, driving circuit 24 will not export impulse level signal.
Further, after self-test timer starts timing, in the first preset time, if logic judging circuit 22
When detecting the command information for the output drive signal that control unit 30 is sent again, driving circuit 24 continues to output pulse
Level signal, while the clearing of self-test timer restarts timing.If not detecting to come again in the first preset time
The command information for the output drive signal sent from control unit 30, then driving circuit 24 will turn off the output of pulse at once,
Timer resets and stops timing, realizes the self-checking function of FPGA logic cell 20, and FPGA logic cell 20 enters at this time
Detection control unit 30 is waited to send the state of information.
To sum up, the multichannel I/O output control system for train of the embodiment of the present invention, is designed based on FPGA, is made
Control unit carries out drive control to multiple secure hardware circuits by the inclusion of the FPGA logic cell of multiple output channels, realizes
The control of multichannel I/O output can provide safeguard for secure hardware circuit in safe work state, while improve entire
The speed of service, stability and the reliability of control system, and it is at low cost.
Further, the invention proposes a kind of trains.
Fig. 4 is the block diagram of train according to an embodiment of the present invention.As shown in figure 4, the train 1000 includes in the present invention
State the multichannel I/O output control system 100 for train of embodiment.
The train of the embodiment of the present invention is based on using the multichannel I/O output control system for train of above-described embodiment
FPGA is designed, and is realized the control of multichannel I/O output, can be in safe work state for secure hardware circuit and provide guarantor
Barrier, while the speed of service, stability and reliability of entire control system are improved, and at low cost.
In addition, other compositions of train according to an embodiment of the present invention and effect are for those of ordinary skill in the art
For be all it is known, in order to reduce redundancy, be not repeated herein.
Fig. 5 is the flow chart of the multichannel I/O output control method according to an embodiment of the invention for train.Such as figure
Shown in 5, which be can comprise the following steps that
S101, FPGA logic cell receive control information.
Wherein, control information includes command information and address information.
In an embodiment of the present invention, when the control unit of train controls secure hardware circuit, can pass through
FPGA logic cell realizes multichannel I/O output control.Specifically, referring to fig. 2, FPGA logic cell can have Parallel I/O and connect
Mouthful, FPGA logic cell can realize two-way communication by Parallel I/O Interface and control unit.
It is possible to further which sequence circuit corresponding with Parallel I/O Interface, fpga logic are arranged in FPGA logic cell
The control information that unit can be sent according to the sequence circuit reception control unit.
S102, FPGA logic cell generate corresponding driving signal according to the command information received, and to address information
Decoding processing is carried out to be exported with one obtained in multiple output channels.
S103, FPGA logic cell are exported the driving signal of generation by the output channel of acquisition hard to corresponding safety
Part circuit.
Specifically, FPGA logic cell is powered on into after operating mode, and control unit includes to FPGA logic cell transmission
The control information of address information and command information, such as controls train deceleration, and FPGA logic cell passes through Parallel I/O Interface and correspondence
Sequence circuit receive control information, and then corresponding driving signal, such as driving column can be generated according to the command information that receives
Vehicle slow down driving signal, and to address information carry out decoding processing to obtain one in multiple output channels, such as and train
The corresponding output channel of speed control circuit, is exported, and then the output channel by obtaining drives the train deceleration of generation
Dynamic signal is exported to train speed control circuit, to drive train speed control circuit to execute deceleration instruction.
Optionally, if control unit sends multiple control information, and each control information to FPGA logic cell simultaneously
In address information it is different, or send one include multiple and different address informations control information, then FPGA logic cell can
To carry out decoding processing to different address informations to obtain multiple output channels (such as output channel 21a-21c), if according to
The command information received generates corresponding driving signal, then can be believed the driving of generation by output channel 21a-21c
Number it is sent to corresponding secure hardware circuit 10a-10c.
Hereby it is achieved that the control of multichannel I/O output, reduces the load of control unit, improves the fortune of control system
Scanning frequency degree and stability, and at low cost, flexibility, good reliability.
In one embodiment of the invention, as shown in fig. 6, it is raw according to the command information received in above-mentioned steps S102
At corresponding driving signal, comprising:
Whether S1021, FPGA logic cell decision instruction information are output drive signal or shutdown driving signal.
Optionally, driving signal can be the impulse level signal of fixed frequency.
Specifically, after control unit sends control information to FPGA logic cell, FPGA logic cell can pass through Parallel I/O
Interface sequence circuit receives the control information, so can control the address information in information carry out decoding processing it is multiple to obtain
One in output channel is exported, and judges to control whether the command information in information is that output drive signal or shutdown are driven
Dynamic signal.
S1022, if control instruction is output drive signal, FPGA logic cell generates corresponding driving signal, and
Self-test timer built in control FPGA logic cell starts to carry out timing to the time of output drive signal.
Specifically, if command information is output drive signal, FPGA logic cell generates and exports fixed frequency
Impulse level signal, and then can be exported the impulse level signal of the fixed frequency to corresponding peace by the output channel of acquisition
Devices at full hardware circuit, while the self-test timer built in FPGA logic cell starts to carry out timing to the time of output drive signal.
S1023, if control instruction is shutdown driving signal, FPGA logic cell stops generating corresponding driving letter
Number, and control self-test timer and stop carrying out timing to the time of output drive signal.
Specifically, the instruction letter if FPGA logic cell receives a control signal again, and in the control signal
Breath is shutdown driving signal, then self-test timer stops timing, and FPGA logic cell stops generating driving signal, and then stops
To 20 output drive signal of secure hardware circuit.At this point, FPGA logic cell can so that original operating state, that is, power on etc. to be controlled
Unit processed sends control information again.
In one embodiment of the invention, as shown in fig. 7, control method can with the following steps are included:
S104, FPGA logic cell judge whether to receive the instruction letter of output drive signal every the first preset time
Breath.
S105, if receiving the command information of output drive signal, FPGA logic cell control self-test timer is set
Zero carries out reclocking with the time to output drive signal.
For example, t0 moment, FPGA logic cell receive the command information of output drive signal, and self-test timer is opened
Beginning timing, FPGA logic cell generates driving signal, and is sent to the driving signal of generation pair by the output channel of selection
The secure hardware circuit answered.T1 moment, self-test timer timing time are t1-t0, and t1-t0 < Δ t, wherein Δ t is first
Preset time, FPGA logic cell receives the command information of output drive signal again at this time, then in t0+ time Δt, self-test
Timer zero setting and reclocking, FPGA logic cell continues to output driving signal, and will be generated by the output channel of selection
Driving signal be sent to corresponding secure hardware circuit.T2 moment, self-test timer timing time are t2-t0- Δ t, and t2-
T0- Δ t < Δ t, FPGA logic cell receives again the command information of output drive signal at this time, then in t0+2 Δ t
It carves, the zero setting of self-test timer and reclocking, FPGA logic cell continue to output driving signal, and the output channel for passing through selection
The driving signal of generation is sent to corresponding secure hardware circuit, and so on.
S106, if being not received by the command information of output drive signal, FPGA logic cell judges self-test timing
Whether the timing time of device reaches the second preset time.
S107, if the timing time of self-test timer reaches the second preset time, FPGA logic cell stops generating
Driving signal.
For example, t0 moment, FPGA logic cell receive the command information of output drive signal, and self-test timer is opened
Beginning timing, FPGA logic cell generates driving signal, and is sent to the driving signal of generation pair by the output channel of selection
The secure hardware circuit answered.T0+ time Δt, self-test timer timing time are Δ t, and FPGA logic cell is without again at this time
Command information is received, self-test timer continues timing, and FPGA logic cell continues to output driving signal.When self-test timer
When timing time reaches the second preset time Δ t ', wherein Δ t ' > Δ t, FPGA logic cell stop generating driving signal, into
And stop to secure hardware circuit output drive signal, and self-test timer zero setting at this time and stop timing.
In one embodiment of the invention, FPGA logic cell can also (as shown in Figure 2 patrols by internal logic circuit
Volume decision circuitry, self-test logic circuit) signal of output is transmitted to control unit, so that control unit 30 obtains control system
Export state of a control.
Further, state of a control can also be sent to a coupled display unit by control unit, aobvious to control
Show that unit shows the state of a control, as a result, the control of multichannel I/O output is more intuitive, convenient for the control exported to multichannel I/O
System.
To sum up, the multichannel I/O output control method for train of the embodiment of the present invention, is designed based on FPGA, is led to
It crosses the FPGA logic cell comprising multiple output channels and drive control is carried out to multiple secure hardware circuits, realize multichannel I/O
The control of output can provide safeguard in safe work state for secure hardware circuit, while improve entire control system
The speed of service, stability and reliability, and it is at low cost.
In the description of the present invention, it is to be understood that, term " first ", " second " are used for description purposes only, and cannot
It is interpreted as indication or suggestion relative importance or implicitly indicates the quantity of indicated technical characteristic.Define as a result, " the
One ", the feature of " second " can explicitly or implicitly include at least one of the features.In the description of the present invention, " multiple "
It is meant that at least two, such as two, three etc., unless otherwise specifically defined.
It should be noted that in flow charts indicate or logic and/or step described otherwise above herein, for example,
It is considered the order list of the executable instruction for realizing logic function, may be embodied in any computer can
Read in medium, for instruction execution system, device or equipment (such as computer based system, including the system of processor or its
He can be from instruction execution system, device or equipment instruction fetch and the system executed instruction) it uses, or combine these instruction executions
System, device or equipment and use.For the purpose of this specification, " computer-readable medium " can be it is any may include, store,
Communicate, propagate, or transport program is for instruction execution system, device or equipment or combines these instruction execution systems, device or sets
The standby and device that uses.The more specific example (non-exhaustive list) of computer-readable medium include the following: have one or
The electrical connection section (electronic device) of multiple wirings, portable computer diskette box (magnetic device), random access memory (RAM), only
It reads memory (ROM), erasable edit read-only storage (EPROM or flash memory), fiber device and portable light
Disk read-only memory (CDROM).In addition, computer-readable medium can even is that the paper that can print described program on it or its
His suitable medium, because can then be edited for example by carrying out optical scanner to paper or other media, be interpreted or must
It is handled when wanting with other suitable methods electronically to obtain described program, is then stored in computer storage
In.
In the present invention unless specifically defined or limited otherwise, term " installation ", " connected ", " connection ", " fixation " etc.
Term shall be understood in a broad sense, for example, it may be being fixedly connected, may be a detachable connection, or integral；It can be mechanical connect
It connects, is also possible to be electrically connected；It can be directly connected, can also can be in two elements indirectly connected through an intermediary
The interaction relationship of the connection in portion or two elements, unless otherwise restricted clearly.For those of ordinary skill in the art
For, the specific meanings of the above terms in the present invention can be understood according to specific conditions.
In the present invention unless specifically defined or limited otherwise, fisrt feature in the second feature " on " or " down " can be with
It is that the first and second features directly contact or the first and second features pass through intermediary mediate contact.Moreover, fisrt feature exists
Second feature " on ", " top " and " above " but fisrt feature be directly above or diagonally above the second feature, or be merely representative of
First feature horizontal height is higher than second feature.Fisrt feature can be under the second feature " below ", " below " and " below "
One feature is directly under or diagonally below the second feature, or is merely representative of first feature horizontal height less than second feature.
In the description of this specification, reference term " one embodiment ", " some embodiments ", " example ", " specifically show
The description of example " or " some examples " etc. means specific features, structure, material or spy described in conjunction with this embodiment or example
Point is included at least one embodiment or example of the invention.In the present specification, schematic expression of the above terms are not
It must be directed to identical embodiment or example.Moreover, particular features, structures, materials, or characteristics described can be in office
It can be combined in any suitable manner in one or more embodiment or examples.In addition, without conflicting with each other, the skill of this field
Art personnel can tie the feature of different embodiments or examples described in this specification and different embodiments or examples
It closes and combines.
Although the embodiments of the present invention has been shown and described above, it is to be understood that above-described embodiment is example
Property, it is not considered as limiting the invention, those skilled in the art within the scope of the invention can be to above-mentioned
Embodiment is changed, modifies, replacement and variant.
Claims (10)
1. a kind of multichannel I/O output control system for train characterized by comprising multiple secure hardware circuits, FPGA
Logic unit and control unit are in communication with each other between described control unit and the FPGA logic cell, wherein
Described control unit sends control information by being communicated with the FPGA logic cell to the FPGA logic cell,
Wherein, the control information includes command information and address information；
The FPGA logic cell includes multiple output channels, and each output channel is correspondingly connected with to a secure hardware circuit,
The FPGA logic cell is used to generate corresponding driving signal according to the command information that receives, and to the address information into
Row decoding processing is exported with one obtained in the multiple output channel, and will be generated by the output channel of acquisition
Driving signal export to corresponding secure hardware circuit.
2. being used for the multichannel I/O output control system of train as described in claim 1, which is characterized in that the fpga logic
Unit, comprising:
Logic judging circuit, the logic judgment module are used to carry out the address information decoding processing the multiple to obtain
One in output channel is exported, and judge described instruction information whether be output drive signal or shutdown driving signal,
And the first enable signal is exported when judging the control instruction for output drive signal, judging the control instruction for pass
The second enable signal is exported when disconnected driving signal；
Self-test logic circuit, the self-test logic circuit are connected with the logic judging circuit, and the self-test logic circuit includes
Self-test timer, the self-test logic circuit are used to control institute when the logic judging circuit exports first enable signal
It states self-test timer and starts timing, and control the self-test when the logic judging circuit exports second enable signal
Timer stops timing；
Driving circuit, the driving circuit are connected with the logic judging circuit, and the driving circuit in the logic for sentencing
Deenergizing generates driving signal when exporting first enable signal, and the output channel by obtaining is by the driving signal of generation
It exports to corresponding secure hardware circuit, and stops generating when the logic judging circuit exports second enable signal
The driving signal.
3. being used for the multichannel I/O output control system of train as claimed in claim 2, which is characterized in that the logic judgment
Circuit is also used to:
The command information that output drive signal whether is received in first preset time is judged every the first preset time,
And in the command information for receiving output drive signal, first enable signal is exported；
Wherein, the self-test logic circuit is also used to control the self-test timing when receiving first enable signal every time
Device zero setting and reclocking.
4. being used for the multichannel I/O output control system of train as claimed in claim 3, which is characterized in that the self-test logic
Circuit is also used to:
When the logic judging circuit is not received by the command information of output drive signal in first preset time,
Judge whether the timing time of the self-test timer reaches the second preset time, and in the timing time of the self-test timer
Generate shutdown pulse signal when reaching second preset time, and by the shutdown output of pulse signal to the logic judgment
Circuit, wherein second preset time is greater than first preset time；
Wherein, the logic judging circuit is also used to according to the shutdown output of pulse signal third enable signal to the driving
Circuit, so that the driving circuit stops generating the driving signal.
5. such as the multichannel I/O output control system of any of claims 1-4 for train, which is characterized in that institute
The signal for stating logic judging circuit and self-test logic circuit output is also transmitted to described control unit, so that the control is single
Member obtains the output state of a control of the control system.
6. a kind of train, which is characterized in that defeated including the multichannel I/O according to any one of claims 1 to 5 for train
Control system out.
7. a kind of multichannel I/O output control method for train, which comprises the following steps:
FPGA logic cell receives control information, wherein the control information includes command information and address information；
The FPGA logic cell generates corresponding driving signal according to the command information that receives, and to the address information into
Row decoding processing is exported with one obtained in the multiple output channel；
The FPGA logic cell is exported the driving signal of generation to corresponding secure hardware electricity by the output channel obtained
Road.
8. being used for the multichannel I/O output control method of train as claimed in claim 7, which is characterized in that the fpga logic
Unit generates corresponding driving signal according to the command information received, comprising:
The FPGA logic cell judges whether described instruction information is output drive signal or shutdown driving signal；
If the control instruction is output drive signal, the FPGA logic cell generates corresponding driving signal, and controls
The self-test timer built in the FPGA logic cell is made to start to carry out timing to the time of output drive signal；
If the control instruction is shutdown driving signal, FPGA logic cell stops generating corresponding driving signal, and controls
The self-test timer is made to stop carrying out timing to the time of output drive signal.
9. being used for the multichannel I/O output control method of train as claimed in claim 8, which is characterized in that further include:
The FPGA logic cell judges whether to receive the command information of output drive signal every the first preset time；
If receiving the command information of output drive signal in first preset time, the FPGA logic cell control
It makes the self-test timer zero setting and reclocking is carried out with the time to output drive signal.
10. being used for the multichannel I/O output control method of train as claimed in claim 9, which is characterized in that further include:
If being not received by the command information of output drive signal in first preset time, the fpga logic list
Member judges whether the timing time of the self-test timer reaches the second preset time；
If the timing time of the self-test timer reaches second preset time, the FPGA logic cell stops life
At driving signal.
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| CN201710403675.4A CN108983645B (en) | 2017-06-01 | 2017-06-01 | Train and multi-path I/O output control system and method for train |
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| CN201710403675.4A CN108983645B (en) | 2017-06-01 | 2017-06-01 | Train and multi-path I/O output control system and method for train |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112441079A (en) * | 2019-08-29 | 2021-03-05 | 比亚迪股份有限公司 | Rail train, vehicle-mounted controller and rail train speed measuring method and device |
| CN114397805A (en) * | 2022-03-24 | 2022-04-26 | 北京全路通信信号研究设计院集团有限公司 | Method and system for safely acquiring input signal by taking two out of two |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007286735A (en) * | 2006-04-13 | 2007-11-01 | Toyota Motor Corp | Vehicle control device |
| CN202563308U (en) * | 2012-03-31 | 2012-11-28 | 中国科学院上海应用物理研究所 | Fast interlock controller |
| CN103117732A (en) * | 2013-02-22 | 2013-05-22 | 哈尔滨工程大学 | Multi-channel video pulse signal generation device and method |
| WO2014116435A1 (en) * | 2013-01-28 | 2014-07-31 | Ge Intelligent Platforms, Inc. | Method and system for a configurable hardware module |
| CN104123187A (en) * | 2013-04-29 | 2014-10-29 | 帝斯贝思数字信号处理和控制工程有限公司 | Flexible distribution of I/O channels of a hardware component |
| CN105117319A (en) * | 2015-08-25 | 2015-12-02 | 烽火通信科技股份有限公司 | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA |
-
2017
- 2017-06-01 CN CN201710403675.4A patent/CN108983645B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2007286735A (en) * | 2006-04-13 | 2007-11-01 | Toyota Motor Corp | Vehicle control device |
| CN202563308U (en) * | 2012-03-31 | 2012-11-28 | 中国科学院上海应用物理研究所 | Fast interlock controller |
| WO2014116435A1 (en) * | 2013-01-28 | 2014-07-31 | Ge Intelligent Platforms, Inc. | Method and system for a configurable hardware module |
| CN103117732A (en) * | 2013-02-22 | 2013-05-22 | 哈尔滨工程大学 | Multi-channel video pulse signal generation device and method |
| CN104123187A (en) * | 2013-04-29 | 2014-10-29 | 帝斯贝思数字信号处理和控制工程有限公司 | Flexible distribution of I/O channels of a hardware component |
| CN105117319A (en) * | 2015-08-25 | 2015-12-02 | 烽火通信科技股份有限公司 | Method for realizing real-time monitoring of multi-channel MDIO (Management Data Input Output) devices based on FPGA |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN112441079A (en) * | 2019-08-29 | 2021-03-05 | 比亚迪股份有限公司 | Rail train, vehicle-mounted controller and rail train speed measuring method and device |
| CN114397805A (en) * | 2022-03-24 | 2022-04-26 | 北京全路通信信号研究设计院集团有限公司 | Method and system for safely acquiring input signal by taking two out of two |
| CN114397805B (en) * | 2022-03-24 | 2022-08-09 | 北京全路通信信号研究设计院集团有限公司 | Method and system for safely acquiring input signal by taking two out of two |
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|---|---|
| CN108983645B (en) | 2020-12-25 |
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