CN108962158B - 3Tr ULP gate drive circuit and control circuit thereof - Google Patents
3Tr ULP gate drive circuit and control circuit thereof Download PDFInfo
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- CN108962158B CN108962158B CN201810621573.4A CN201810621573A CN108962158B CN 108962158 B CN108962158 B CN 108962158B CN 201810621573 A CN201810621573 A CN 201810621573A CN 108962158 B CN108962158 B CN 108962158B
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3674—Details of drivers for scan electrodes
- G09G3/3677—Details of drivers for scan electrodes suitable for active matrices only
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
- G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
- G09G3/3611—Control of matrices with row and column drivers
- G09G3/3696—Generation of voltages supplied to electrode drivers
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Abstract
The invention discloses a 3Tr ULP gate drive circuit and a control circuit thereof, belonging to the technical field of electronics.A special three-Tr design is adopted to integrate two rows of pixels, one gate wire and one Tr switch are reduced, a larger space can be provided to increase the capacitance of C2, and the integration of a gate circuit is facilitated; the combination of GOA and ULP is realized through a GOA integration circuit, and the narrow frame and low power consumption design are realized. For some reflective/semi-transparent low-power-consumption products, the problem of electric leakage under a low refreshing frequency can be reduced through a special design of three Tr, and the problem of pixel voltage maintenance under a low frequency is further increased; and integrating special gate drive signals by using an integration circuit at the periphery of the display area to realize the application of ULP GOA, thereby realizing the application of narrow-frame high-resolution low-power-consumption products.
Description
[ technical field ] A method for producing a semiconductor device
The invention relates to the field of electronic circuits, in particular to a 3Tr ULP gate drive circuit and a control circuit thereof.
[ background of the invention ]
Along with the improvement of people's needs, especially intelligent wrist-watch product also pays attention to the outward appearance when requiring the power consumption, and low-power consumption product grid wiring usually is more, is difficult to accomplish requirements such as narrow frame. The space occupied by the GATE lines and the Tr switches often prevents the capacity increase, and the like, so that the driving circuits with fewer GATE lines and Tr switches need to be designed. Meanwhile, the narrow frame and the low-power-consumption drive cannot be combined together by the conventional circuit design, so that the requirements of low power consumption, narrow frame and the like cannot be met by the drive circuit and the integrated circuit design.
[ summary of the invention ]
The invention aims to disclose a 3Tr ULP GATE drive circuit and a control circuit thereof, wherein two rows of pixels are integrated together through a special three Tr design, a GATE (GATE electrode) wire and a Tr switch are reduced, a larger space can be provided to increase the capacitance of C2, the integration of a GATE circuit is facilitated, the combination of GOA and ULP is realized through a GOA integration circuit, and the design of a narrow frame and low power consumption is realized.
The technical scheme adopted by the invention is as follows:
a3 Tr ULP GATE driving circuit includes a multi-stage driving unit, an nth stage driving unit including an upper pixel module, a switch module and a lower pixel module, wherein n is a positive integer, the switch module is electrically connected to the upper pixel module and the lower pixel module, respectively, the switch module is further connected to a second GATE terminal and a SOURCE terminal, respectively, the upper pixel module is connected to a first GATE terminal and a VCOM terminal, respectively, the lower pixel module is connected to a third GATE terminal and a VCOM terminal, respectively,
the switching module is used for respectively charging the upper pixel module and the lower pixel module at different moments;
the upper pixel module and the lower pixel module are used for being matched with the switch module to carry out interactive charging and controlling an external display area.
Further, the switch module comprises a second thin film transistor, a GATE of the second thin film transistor is electrically connected with a second GATE terminal, a drain of the second thin film transistor is electrically connected with the upper pixel module and the lower pixel module respectively, and a SOURCE of the second thin film transistor is connected with a SOURCE terminal.
Furthermore, the upper pixel module comprises a first thin film transistor, a first capacitor and a second capacitor, the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor and one end of the second capacitor are both connected with the VCOM end, the other end of the first capacitor and the other end of the second capacitor are both connected with the drain electrode of the first thin film transistor, the grid electrode of the first thin film transistor is connected with the first GATE end, and the source electrode of the first thin film transistor is electrically connected with the drain electrode of the second thin film transistor.
Further, the lower pixel module comprises a third thin film transistor, a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor and one end of the fourth capacitor are both connected with the VCOM end, the other end of the third capacitor and the other end of the fourth capacitor are both connected with the source electrode of the third thin film transistor, the GATE electrode of the third thin film transistor is connected with the third GATE end, and the drain electrode of the third thin film transistor is electrically connected with the drain electrode of the second thin film transistor and the source electrode of the first thin film transistor.
A control circuit of a 3Tr ULP gate drive circuit comprises a multi-stage control unit, an nth stage control unit comprises a first control module, a second control module and a third control module, the first control module, the second control module and the third control module are electrically connected in pairs, the first control module is electrically connected with an upper pixel module, the second control module is electrically connected with a switch module, the third control module is electrically connected with a lower pixel module,
wherein, the first control module is used for generating a first GATE end scanning signal to control the upper pixel module,
a second control module for generating a second GATE terminal scan signal to control the switch module,
and the third control module is used for generating a third GATE end scanning signal to control the lower pixel module.
Furthermore, the first control module includes a fourth thin film transistor and a seventh thin film transistor, a drain of the fourth thin film transistor is connected to the first GA signal terminal generated by the GOA circuit, a GATE of the fourth thin film transistor is connected to the CH terminal, and is respectively connected to the second control module and the third control module, a source of the fourth thin film transistor is connected to the drain of the seventh thin film transistor and the first GATE terminal, a GATE of the seventh thin film transistor is connected to the GL terminal, and is respectively connected to the second control module and the third control module, a source of the seventh thin film transistor is connected to the first GB signal terminal generated by the GOA circuit, and a drain of the seventh thin film transistor is connected to the first GATE terminal.
Furthermore, the second control module includes a fifth thin film transistor and an eighth thin film transistor, a drain of the fifth thin film transistor is connected to the second GA signal terminal generated by the GOA circuit, a GATE of the fifth thin film transistor is connected to the CH terminal, and is connected to the GATE of the fourth thin film transistor and the third control module, respectively, a source of the fifth thin film transistor is connected to the drain of the eighth thin film transistor and the second GATE terminal, a GATE of the eighth thin film transistor is connected to the GL terminal, and is connected to the GATE of the seventh thin film transistor and the third control module, respectively, a source of the eighth thin film transistor is connected to the second GB signal terminal generated by the GOA circuit, and a drain of the eighth thin film transistor is connected to the second GATE terminal.
Further, the third control module includes a sixth thin film transistor and a ninth thin film transistor, a drain of the sixth thin film transistor is connected to the third GA signal terminal generated by the GOA circuit, a GATE of the sixth thin film transistor is connected to the CH terminal, and is respectively connected to a GATE of the fourth thin film transistor and a GATE of the fifth thin film transistor, a source of the sixth thin film transistor is connected to a drain of the ninth thin film transistor and the third GATE terminal, a GATE of the ninth thin film transistor is connected to the GL terminal, and is respectively connected to a GATE of the seventh thin film transistor and a GATE of the eighth thin film transistor, a source of the ninth thin film transistor is connected to the third GB signal terminal generated by the GOA circuit, and a drain of the ninth thin film transistor is connected to the third GATE terminal.
The technical scheme of the invention has the following advantages:
1. according to the invention, through a special three-Tr design, two rows of pixels are integrated, one GATE wiring and one Tr switch are reduced, a larger space is provided for increasing the capacitance of C2, and the integration of a grid circuit is facilitated; the combination of GOA and ULP is realized through a GOA integrated circuit, and the design of narrow frame and low power consumption is realized
2. The narrow frame and the low-power-consumption drive can be well combined together, and the requirements of low power consumption, narrow frame and the like are met through a special drive circuit and integrated circuit design.
[ description of the drawings ]
FIG. 1 is a schematic diagram of a 3Tr ULP gate drive circuit in accordance with an embodiment of the present invention;
FIG. 2 is a block diagram of a 3Tr ULP gate drive circuit of the present invention;
FIG. 3 is a control circuit schematic of a 3Tr ULP gate drive circuit of the present invention;
FIG. 4 is a block diagram of a control circuit for a 3Tr ULP gate drive circuit of the present invention;
FIG. 5 is a schematic diagram of the control circuit drive waveforms for a 3Tr ULP gate drive circuit of the present invention;
FIG. 6 is a schematic diagram of the drive waveforms of a 3Tr ULP gate drive circuit of the present invention;
fig. 7 is a schematic design of the present invention.
Description of the main elements
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The following detailed description will further illustrate the invention in conjunction with the above-described figures.
[ detailed description ] embodiments
The technical solutions in the embodiments of the present invention will be described clearly and completely with reference to the accompanying drawings in the embodiments of the present invention, and it is obvious that the described embodiments are only a part of the embodiments of the present invention, and not all of the embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present invention.
It is to be understood that the terminology used in the embodiments of the invention herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used in the examples of the present invention and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any and all possible combinations of one or more of the associated listed items.
The terms "comprising" and "having," and any variations thereof, in the description and claims of this invention and the above-described drawings are intended to cover non-exclusive inclusions. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those steps or elements listed, but may alternatively include other steps or elements not listed, or inherent to such process, method, article, or apparatus.
It is noted that the following detailed description describes embodiments of the invention, examples of which are illustrated in the accompanying drawings, wherein like reference numerals refer to the same or similar elements or elements having the same or similar function throughout. The embodiments described below with reference to the drawings are illustrative only and should not be construed as limiting the invention.
The following disclosure provides many different embodiments, or examples, for implementing different features of the invention. To simplify the disclosure of the present invention, the components and arrangements of specific examples are described below. Of course, they are merely examples and are not intended to limit the present invention. Furthermore, the present invention may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
Referring to fig. 2, a block diagram of a 3Tr ULP gate driving circuit according to an embodiment of the present invention is shown in fig. 2, where the gate driving circuit includes a multi-stage driving unit, and an nth stage driving unit includes an upper pixel module 1, a switch module 2, and a lower pixel module 3, where n is a positive integer. The switching module 2 is electrically connected to the upper pixel module 1 and the lower pixel module 3, respectively. The switch module 2 is also connected to the second GATE terminal GATE2 and SOURCE terminal, respectively. The upper pixel block 1 is connected to a first GATE terminal GATE1 and a VCOM terminal (common voltage adjusting terminal), respectively. The lower pixel block 3 is connected to the third GATE terminal GATE3 and the VCOM terminal (common voltage adjusting terminal), respectively. The switch module 2 is used for respectively charging the upper pixel module and the lower pixel module at different moments, and the upper pixel module 1 and the lower pixel module 3 are used for being matched with the switch module to carry out interactive charging and controlling an external display area.
It can be seen that in the ULP gate driving circuit of 3Tr in the technical solution of the embodiment of the present invention, each stage of driving unit includes an upper pixel module, a switch module, and a lower pixel module.
Fig. 1 is a schematic diagram of a 3Tr ULP gate driving circuit according to an embodiment of the present invention.
Each circuit block is described in detail below.
The switch module 2 includes a second thin film transistor T2, a GATE of the second thin film transistor T2 is electrically connected to a second GATE terminal GATE2, a drain is electrically connected to the upper pixel module 1 and the lower pixel module 3, respectively, and a SOURCE is connected to a SOURCE terminal.
The upper pixel module 1 comprises a first thin film transistor T1, a first capacitor C1 and a second capacitor C2, wherein the first capacitor C1 and the second capacitor C2 are connected in parallel, one end of each of the first capacitor C1 and the second capacitor C2 is connected with a VCOM end, and the other end of each of the first capacitor C1 and the second capacitor C2 is connected with a drain electrode of the first thin film transistor T1. The GATE of the first thin film transistor T1 is connected to the first GATE terminal GATE1, and the source is electrically connected to the drain of the second thin film transistor T2.
The lower pixel module 3 comprises a third thin film transistor T3, a third capacitor C3 and a fourth capacitor C4, wherein the third capacitor C3 and the fourth capacitor C4 are connected in parallel, one end of each of the third capacitor C3 and the fourth capacitor C4 is connected with a VCOM end, the other end of each of the third capacitor C3 and the fourth capacitor C4 is connected with a source electrode of the third thin film transistor T3, a GATE electrode of the third thin film transistor T3 is connected with a GATE electrode GATE end GATE3, and a drain electrode of the third thin film transistor T2 is electrically connected with a drain electrode of the second thin film transistor T2 and a source electrode of the first thin film transistor T1.
As shown in fig. 4, it is a block diagram of a control circuit of a 3Tr ULP gate driving circuit of the present invention:
a control circuit of a 3Tr ULP gate drive circuit includes a multi-stage control unit. The nth level control unit includes a first control module 4, a second control module 5, and a third control module 6. The first control module 4, the second control module 5 and the third control module 6 are electrically connected in pairs. The first control module 4 is respectively connected with the second control module 5 and the third control module 6, the second control module 5 is respectively connected with the first control module 4 and the third control module 6, and the third control module 6 is respectively connected with the first control module 4 and the second control module 5. The first control module 4 is electrically connected to the upper pixel module 1 in the GATE driving circuit through a first GATE terminal GATE1, the second control module 5 is electrically connected to the switch module 2 in the GATE driving circuit through a second GATE terminal GATE2, and the third control module 6 is electrically connected to the lower pixel module 3 in the GATE driving circuit through a third GATE terminal GATE 3. the first control module 4 is configured to generate a first GATE terminal GATE1 scan signal to control the upper pixel module. The second control module 5 is configured to generate a second GATE terminal GATE2 scan signal to control the switch module. The third control module 6 is used for generating a scan signal at the third GATE terminal GATE3 to control the lower pixel module.
It can be seen that in the control circuit of the 3Tr ULP gate driving circuit in the technical solution of the embodiment of the present invention, each control unit includes a first control module, a second control module, and a third control module.
Fig. 3 is a schematic diagram of a control circuit of a 3Tr ULP gate driving circuit according to an embodiment of the present invention.
Each circuit block is described in detail below.
The first control module 4 comprises a fourth thin film transistor T4 and a seventh thin film transistor T7, the drain of the fourth thin film transistor T4 is connected to the first GA signal terminal GA1 generated by the GOA circuit, the GATE is connected to the CH terminal, and is respectively connected to the second control module 5 and the third control module 6, the source is connected to the drain of the seventh thin film transistor T7 and the first GATE terminal GATE1, the GATE of the seventh thin film transistor T7 is connected to the GL terminal, and is respectively connected to the second control module 5 and the third control module 6, the source is connected to the first GB signal terminal GB1 generated by the GOA circuit, and the drain is connected to the first GATE terminal GATE 1.
The second control module 5 includes a fifth thin film transistor T5 and an eighth thin film transistor T8, and the drain of the fifth thin film transistor T5 is connected to the second GA signal terminal GA2 generated by the GOA circuit, and the gate thereof is connected to the CH terminal, and is respectively connected to the gate of the fourth thin film transistor T4 and the third control module 6. The source is connected to the drain of the eighth tft T8 and the second GATE terminal GATE2, the GATE of the eighth tft T8 is connected to the GL terminal and to the GATE of the seventh tft T7 and the third control module 6, respectively, the source is connected to the second GB signal terminal GB2 generated by the GOA circuit, and the drain is connected to the second GATE terminal GATE 2.
The third control module 6 comprises a sixth thin film transistor T6 and a ninth thin film transistor T9, the drain of the sixth thin film transistor T6 is connected to the third GA signal terminal GA3 generated by the GOA circuit, the GATE is connected to the CH terminal, and is respectively connected to the GATE of the fourth thin film transistor T4 and the GATE of the fifth thin film transistor T5, the source is connected to the drain of the ninth thin film transistor T9 and the third GATE terminal GATE3, the GATE of the ninth thin film transistor T9 is connected to the GL terminal, and is respectively connected to the GATE of the seventh thin film transistor T7 and the GATE of the eighth thin film transistor T8, the source is connected to the third GB signal terminal GB3 generated by the GOA circuit, and the drain is connected to the third GATE terminal GATE 3.
The working process is explained according to fig. 5-7, fig. 1 and fig. 3:
in the period of one frame, pixel charging only occurs in an overlap region delta T1 where two adjacent rows GATE in the TA section are simultaneously opened, in the TB section, in order to improve the stress drift problem caused by the fact that Tr is in the same state for a long time, a bias voltage resisting waveform (GB 1/2/3) that T1 and T2(T2 and T3) are alternately opened is set, and the low refreshing frequency ensures the low power consumption requirement of the product.
In addition, in the pixel holding area TB, the pulse widths of the bias signals GB1/GB2/GB3 are each Δ T2, and the delays between the bias signals are each Δ T2, i.e., T1 and T2(T2 and T3) overlap open during this period; the GATE signal GH/GL is set high in sections TB and TA respectively through the integrated circuit, T4 (T5, T6) and T7(T8 and T9) are respectively turned on, three GATE signals integrated by two rows of pixels are mutually staggered, namely the signals in the section TB are three different signals GB1/GB2/GB3, and the GA signal generated by GOA and the bias resisting signal GB are converged into a GATE driving signal GATE (N), wherein N =1, 2.
When the pixel is charged, the GATE signals GATE1, GATE2 and GATE3 turn on T1, T2 and T3 in sequence, and charge the upper pixel in the overlap region Δ T1 where T1 and T2 are simultaneously turned on, and similarly, charge the lower pixel in the overlap region Δ T1 where T2 and T3 are simultaneously turned on, that is, the pixel is completely charged in the front period of time when T2 is turned on, then T1 is turned off, the pixel is completely charged in the rear period of time when T2 is turned on, and then T2 is turned off; the charging of the upper pixel and the lower pixel can be independently controlled, but the self-overlapping capacitance of the three triodes and the W/L ratio are very important because of T2, T1 and T3 common source/drain.
The GATE and SOURCE driving waveforms are divided into a TA section and a TB section, wherein the TA section is a pixel updating area, and the TB section is a pixel maintaining area; the GOA signal works in a TA section, and is pulled down to be low level in a TB section; the bias reject signal is input in the TB segment.
The circuit source lines charge the upper and lower pixels, respectively, at different times simultaneously, the upper pixel when T1 and T2 are turned on simultaneously, the lower pixel when T2 and T3 are turned on simultaneously, and charging occurs only in the TA segment, and T1 and T2(T2 and T3) are turned on in an overlapping manner in the TB segment.
Due to the special design of three integrated TFTs (thin film transistors) of two rows of pixels under the condition of low refreshing frequency (1-20 Hz), the electric leakage of the TFTs is reduced, and the number of grid wire traces and the number of Trs are reduced; meanwhile, the combination of the GOA signal and the ULP signal is realized under the design of a GOA integrated circuit by matching with a special driving waveform.
For some reflective/semi-transparent low-power-consumption products, the problem of electric leakage under a low refreshing frequency can be reduced through a special design of three Tr, and the problem of pixel voltage maintenance under a low frequency is further increased; and integrating special gate drive signals by using an integration circuit at the periphery of the display area to realize the application of ULP GOA, thereby realizing the application of narrow-frame high-resolution low-power-consumption products.
The GOA circuit is designed on two sides, GOA signals are shared pairwise, N +2 GOA units are needed for a screen with N rows of pixels, and the number of the GOA units is almost the same as that of a common GOA screen.
Note: c1, C2C 3 and C4 are respectively the liquid crystal capacitance and the pixel capacitance of the liquid crystal display.
Tr: a thin film transistor;
GOA: gate Driver On Array grid integrated circuit
ULP: ultra Low Power, Low Power product
GATE: a scanning line connected with the gate of Tr for controlling the switch of Tr;
SOURCE: and the data line is connected with the Tr source electrode or the drain electrode and controls the charging and discharging of the pixel capacitor.
The invention has the following beneficial effects:
according to the invention, through a special three-Tr design, two rows of pixels are integrated, one GATE wiring and one Tr switch are reduced, a larger space is provided for increasing the capacitance of C2, and the integration of a grid circuit is facilitated; the combination of GOA and ULP is realized through the GOA integrated circuit, the narrow frame and low-power-consumption driving can be well combined together through the narrow frame and low-power-consumption design, and the requirements of low power consumption, narrow frame and the like are realized through the special driving circuit and the integrated circuit design.
Finally, it should be noted that the above embodiments are only used for illustrating the technical solutions of the embodiments of the present invention and not for limiting the same, and although the embodiments of the present invention are described in detail with reference to the preferred embodiments, it should be understood by those skilled in the art that modifications or equivalent substitutions can be made on the technical solutions of the embodiments of the present invention, and these modifications or equivalent substitutions cannot make the modified technical solutions depart from the scope of the technical solutions of the embodiments of the present invention.
Claims (8)
1. A 3Tr ULP gate drive circuit characterized by: the GATE driving circuit includes a multi-stage driving unit, the nth stage driving unit includes an upper pixel module, a switch module and a lower pixel module, where n is a positive integer, the switch module is electrically connected to the upper pixel module and the lower pixel module, respectively, the switch module is also connected to a second GATE terminal and a SOURCE terminal, respectively, the upper pixel module is connected to a first GATE terminal and a VCOM terminal, respectively, the lower pixel module is connected to a third GATE terminal and a VCOM terminal, respectively,
the switching module is used for respectively charging the upper pixel module and the lower pixel module at different moments;
the upper pixel module and the lower pixel module are used for being matched with the switch module to carry out interactive charging and controlling an external display area;
the upper pixel module comprises a first thin film transistor, the switch module comprises a second thin film transistor, the lower pixel module comprises a third thin film transistor, when pixels are charged, the first thin film transistor, the second thin film transistor and the third thin film transistor are sequentially turned on, the upper pixel module is charged in an overlay area where the first thin film transistor and the second thin film transistor are simultaneously turned on, then the first thin film transistor is turned off to keep the second thin film transistor on, the lower pixel module is charged in the overlay area where the second thin film transistor and the third thin film transistor are simultaneously turned on, and then the second thin film transistor and the third thin film transistor are turned off.
2. A 3Tr ULP gate drive circuit as claimed in claim 1, characterized in that: the switch module comprises a second thin film transistor, the grid electrode of the second thin film transistor is electrically connected with the second GATE end, the drain electrode of the second thin film transistor is electrically connected with the upper pixel module and the lower pixel module respectively, and the SOURCE electrode of the second thin film transistor is connected with the SOURCE end.
3. A 3Tr ULP gate drive circuit according to claim 2, characterized in that: the upper pixel module comprises a first thin film transistor, a first capacitor and a second capacitor, the first capacitor and the second capacitor are connected in parallel, one end of the first capacitor and one end of the second capacitor are both connected with a VCOM end, the other end of the first capacitor and the other end of the second capacitor are both connected with a drain electrode of the first thin film transistor, a grid electrode of the first thin film transistor is connected with a first GATE end, and a source electrode of the first thin film transistor is electrically connected with a drain electrode of the second thin film transistor.
4. A 3Tr ULP gate drive circuit according to claim 3, characterized in that: the lower pixel module comprises a third thin film transistor, a third capacitor and a fourth capacitor, the third capacitor and the fourth capacitor are connected in parallel, one end of the third capacitor and one end of the fourth capacitor are both connected with a VCOM end, the other end of the third capacitor and the other end of the fourth capacitor are both connected with a source electrode of the third thin film transistor, a grid electrode of the third thin film transistor is connected with a third GATE end, and a drain electrode of the third thin film transistor is electrically connected with a drain electrode of the second thin film transistor and a source electrode of the first thin film transistor.
5. A control circuit of a 3Tr ULP gate drive circuit, characterized in that: the control circuit comprises a multi-stage control unit, the nth stage control unit comprises a first control module, a second control module and a third control module, the first control module, the second control module and the third control module are electrically connected in pairs, the first control module is electrically connected with the upper pixel module of claim 1, the second control module is electrically connected with the switch module of claim 1, the third control module is electrically connected with the lower pixel module of claim 1,
wherein, the first control module is used for generating a first GATE end scanning signal to control the upper pixel module,
a second control module for generating a second GATE terminal scan signal to control the switch module,
and the third control module is used for generating a third GATE end scanning signal to control the lower pixel module.
6. The control circuit of a 3Tr ULP gate drive circuit according to claim 5, characterized in that: the first control module comprises a fourth thin film transistor and a seventh thin film transistor, the drain electrode of the fourth thin film transistor is connected with a first GA signal end generated by the GOA circuit, the grid electrode of the fourth thin film transistor is connected with a CH end and is respectively connected with the second control module and the third control module, the source electrode of the fourth thin film transistor is connected with the drain electrode of the seventh thin film transistor and a first GATE end, the grid electrode of the seventh thin film transistor is connected with a GL end and is respectively connected with the second control module and the third control module, the source electrode of the seventh thin film transistor is connected with a first GB signal end generated by the GOA circuit, and the drain electrode of the seventh thin film transistor is connected with the first GATE end.
7. The control circuit of a 3Tr ULP gate drive circuit of claim 6, wherein: the second control module comprises a fifth thin film transistor and an eighth thin film transistor, the drain electrode of the fifth thin film transistor is connected with a second GA signal end generated by the GOA circuit, the grid electrode of the fifth thin film transistor is connected with the CH end and is respectively connected with the grid electrode of the fourth thin film transistor and the third control module, the source electrode of the fifth thin film transistor is connected with the drain electrode of the eighth thin film transistor and the second GATE end, the grid electrode of the eighth thin film transistor is connected with the GL end and is respectively connected with the grid electrode of the seventh thin film transistor and the third control module, the source electrode of the eighth thin film transistor is connected with a second GB signal end generated by the GOA circuit, and the drain electrode of the eighth thin film transistor is connected with the.
8. A control circuit of a 3Tr ULP gate drive circuit as claimed in claim 7, characterized in that: the third control module comprises a sixth thin film transistor and a ninth thin film transistor, wherein the drain electrode of the sixth thin film transistor is connected with a third GA signal end generated by the GOA circuit, the grid electrode of the sixth thin film transistor is connected with the CH end and is respectively connected with the grid electrode of the fourth thin film transistor and the grid electrode of the fifth thin film transistor, the source electrode of the sixth thin film transistor is connected with the drain electrode of the ninth thin film transistor and a third GATE end, the grid electrode of the ninth thin film transistor is connected with the GL end and is respectively connected with the grid electrode of the seventh thin film transistor and the grid electrode of the eighth thin film transistor, the source electrode of the ninth thin film transistor is connected with a third GB signal end generated by the GOA circuit, and the drain electrode of the ninth thin.
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| GB2481008A (en) * | 2010-06-07 | 2011-12-14 | Sharp Kk | Active storage pixel memory |
| CN104062788A (en) * | 2014-07-10 | 2014-09-24 | 信利半导体有限公司 | Pixel structure, array substrate and liquid crystal display panel |
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| KR101813169B1 (en) * | 2017-03-15 | 2017-12-28 | 삼성전자주식회사 | Switching apparatus for active display device and method of driving the same |
| CN107481659B (en) * | 2017-10-16 | 2020-02-11 | 京东方科技集团股份有限公司 | Gate drive circuit, shift register and drive control method thereof |
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