CN108958092B - Singlechip clock anomaly detection method and device, computer readable storage medium and equipment - Google Patents
Singlechip clock anomaly detection method and device, computer readable storage medium and equipment Download PDFInfo
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Abstract
The invention relates to a method and a device for detecting clock abnormality of a single chip microcomputer, a computer readable storage medium and equipment, wherein the method comprises the steps of obtaining a communication signal between the single chip microcomputer and preset equipment; judging whether the deviation of the time interval of the adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold value: if the clock frequency is larger than the preset frequency, the clock of the single chip microcomputer is abnormal; the apparatus, computer readable storage medium, device may perform the steps of the above method. Compared with the prior art, the method and the device for detecting the clock abnormity of the single chip microcomputer, the computer readable storage medium and the computer equipment can accurately detect whether the clock of the single chip microcomputer is abnormal or not, meanwhile, external circuits such as an independent clock reference circuit and the like are not needed to be arranged, and the cost of the single chip microcomputer is reduced.
Description
Technical Field
The invention relates to the technical field of single chip microcomputer control, in particular to a method and a device for detecting clock abnormity of a single chip microcomputer, a computer readable storage medium and computer readable storage equipment.
Background
The single chip microcomputer needs clock support in operation, and if a clock circuit is not used for generating a clock to drive the single chip microcomputer, the single chip microcomputer cannot execute programs, so that the single chip microcomputer can be regarded as a sequential logic circuit under the clock drive. At present, the following two methods can be adopted to detect whether the clock circuit of the single chip microcomputer is abnormal, specifically: the first is that: an external clock circuit, such as a crystal oscillator or a ceramic oscillator, is used for comparing with the clock circuit in the single chip microcomputer, and when the error between the two exceeds a certain range, the abnormality of the clock circuit in the single chip microcomputer can be judged. Secondly, the method comprises the following steps: and comparing the singlechip clock circuit with the commercial power frequency, and judging that the clock circuit in the singlechip is abnormal when the error between the singlechip clock circuit and the commercial power frequency exceeds a certain range. However, the two detection modes both need to be provided with additional circuit structures, such as an external clock circuit and a mains supply detection circuit, so that the design cost and the application cost of the single chip microcomputer are increased. Meanwhile, insulation protection is needed when the second detection mode is adopted.
Disclosure of Invention
In order to solve the above problems in the prior art, that is, to solve the technical problem that the single chip microcomputer needs to rely on a peripheral circuit to detect whether the clock is abnormal, the invention provides a method and an apparatus for detecting the clock abnormality of the single chip microcomputer, a computer-readable storage medium, and a computer-readable device.
In a first aspect, the invention provides a method for detecting clock abnormality of a single chip microcomputer, which comprises the following steps:
the method comprises the following steps:
acquiring a communication signal between the singlechip and preset equipment;
judging whether the deviation of the time interval of the adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold value: if the clock value is larger than the preset value, the clock of the single chip microcomputer is abnormal.
Further, a preferred technical solution provided by the present invention is:
the communication signal is a signal based on clock synchronization or a signal not based on clock synchronization.
Further, a preferred technical solution provided by the present invention is:
the method further comprises the following steps:
acquiring oscillation deviation of the clock of the single chip microcomputer;
comparing the obtained oscillation deviation with a preset oscillation deviation threshold: and if the obtained oscillation deviation is larger than the preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal.
Further, a preferred technical solution provided by the present invention is:
the preset oscillation deviation threshold k is as follows:
wherein, terr is the clock error time, and Tbyte is the preset transmission time of one byte in the communication signal;
the method for determining the clock error time Terr comprises the following steps:
and when the deviation between the time interval of adjacent sampling points in the acquired communication signal and the preset sampling period is greater than a preset threshold value, setting the clock error time as the time length between the rising edge of the sampling level in the communication signal and the preset sampling point.
In a second aspect, the invention provides a technical solution of a device for detecting clock abnormality of a single chip microcomputer, comprising:
the device comprises:
the first signal acquisition module is configured to acquire a communication signal between the single chip microcomputer and preset equipment;
the first signal judgment module is configured to judge whether the deviation between the time interval of adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold value: if the clock value is larger than the preset value, the clock of the single chip microcomputer is abnormal.
Further, a preferred technical solution provided by the present invention is:
the communication signal is a signal based on clock synchronization or a signal not based on clock synchronization.
Further, a preferred technical solution provided by the present invention is:
the device further comprises:
the second signal acquisition module is configured to acquire the oscillation deviation of the clock of the single chip microcomputer;
a second signal determination module configured to compare the obtained oscillation deviation with a preset oscillation deviation threshold: and if the obtained oscillation deviation is larger than the preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal.
Further, a preferred technical scheme provided by the invention is as follows:
the second signal judgment module comprises a preset oscillation deviation threshold model k shown as the following formula:
wherein, terr is the clock error time, and Tbyte is the preset transmission time of one byte in the communication signal;
the second signal judgment module also comprises a clock error time calculation module; the clock error time calculation module is configured to set the clock error time as a time length between a rising edge of a sampling level in the communication signal and a preset sampling point when a deviation between a time interval of adjacent sampling points in the acquired communication signal and a preset sampling period is larger than a preset threshold value.
In a third aspect, a technical solution of a computer-readable storage medium in the present invention is:
the computer readable storage medium stores a computer program, and the program is suitable for being loaded and executed by a processor to realize each step in the method for detecting the clock abnormality of the single chip microcomputer.
In a fourth aspect, a technical solution of a computer device in the present invention is:
the computer device comprises a memory, a processor and a computer program which is stored on the memory and can run on the processor, and when the processor executes the program, each step in the singlechip clock abnormity detection method in the technical scheme is realized.
Compared with the prior art, the technical scheme at least has the following beneficial effects:
1. according to the method for detecting the clock abnormity of the single chip microcomputer, whether the clock of the single chip microcomputer is abnormal or not can be judged according to the communication signals of the single chip microcomputer and the preset equipment, a separate external clock circuit or detection circuit is not required to be arranged, and the cost of the single chip microcomputer is reduced.
2. According to the method for detecting the clock abnormity of the single chip microcomputer, the first signal judgment module can judge whether the clock of the single chip microcomputer is abnormal or not according to the communication signals of the single chip microcomputer and the preset equipment, a separate external clock circuit or detection circuit is not required to be arranged, and the cost of the single chip microcomputer is reduced.
3. The computer readable storage medium stores a computer program, and the program can be applied to be loaded and executed by a processor to realize each step in the single chip microcomputer clock abnormality detection method according to the technical scheme.
4. When the processor of the computer device provided by the invention executes the computer program stored in the memory, the steps of the method for detecting the clock abnormality of the single chip microcomputer in the technical scheme can be realized.
Drawings
FIG. 1 is a flow chart of an embodiment of a method for detecting clock abnormality of a single chip microcomputer;
FIG. 2 is a schematic structural diagram of a device for detecting clock abnormality of a single chip microcomputer according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of the communication of the single chip microcomputer in the embodiment of the invention;
FIG. 4 is a schematic diagram of sampling points of communication signals according to an embodiment of the present invention;
FIG. 5 is a diagram illustrating a normal sampling of a byte in a communication signal according to an embodiment of the present invention;
FIG. 6 is a schematic diagram illustrating an anomalous sampling of a byte in a communication signal according to an embodiment of the present invention;
FIG. 7 is a schematic diagram illustrating an abnormal sampling of a byte in another communication signal according to an embodiment of the present invention;
wherein, 11: a first signal acquisition module; 12: a first signal judgment module; 21: a first single chip microcomputer; 22: and the second singlechip is connected with the first singlechip.
Detailed Description
Preferred embodiments of the present invention are described below with reference to the accompanying drawings. It should be understood by those skilled in the art that these embodiments are only for explaining the technical principle of the present invention, and are not intended to limit the scope of the present invention.
The singlechip can adopt an external clock circuit as a reference clock, and the external clock circuit has higher calibration precision, but the cost of the singlechip is correspondingly increased. Furthermore, the single chip microcomputer can also perform clock calibration by comparing with the commercial power frequency, but the calibration method needs to arrange commercial power detection circuits, such as a zero-crossing detection circuit, an a/D conversion circuit, a voltage measurement circuit and the like, in a control board of the single chip microcomputer, so that not only is the cost of the single chip microcomputer increased, but also the non-isolated sampling circuit needs to be reinforced for insulation or double insulation protection. Based on the clock detection method, the clock detection method using the communication signal of the single chip microcomputer as the criterion does not need to be provided with an independent external clock circuit and a mains supply detection circuit, and meanwhile, because the voltage of the communication signal is the same as the power supply property of the single chip microcomputer, insulation protection is not needed.
The following describes a method for detecting clock abnormality of a single chip according to the present invention with reference to the accompanying drawings.
Fig. 1 exemplarily shows an implementation flow of a method for detecting a clock abnormality of a single chip microcomputer in this embodiment, as shown in the figure, the method for detecting a clock abnormality of a single chip microcomputer in this embodiment may include the following steps:
step S101: and acquiring a communication signal between the singlechip and the preset equipment.
The preset device in this embodiment refers to a device that can be configured to communicate with a single chip, and the device may be a single chip or other configurable electronic device. Meanwhile, the communication mode between the single chip microcomputer and the preset device can be a communication mode adopting a clock synchronization signal line, such as an I2C bus communication mode, or a communication mode not adopting a clock synchronization signal line, such as a serial asynchronous communication mode. Correspondingly, the acquired communication signal between the single chip microcomputer and the preset device can be a signal based on clock synchronization or a signal not based on clock synchronization.
Step S102: judging whether the deviation of the time interval of the adjacent sampling points in the acquired communication signal and the preset sampling period is greater than a preset threshold value: if the clock value is larger than the preset value, the clock of the single chip microcomputer is abnormal.
In this embodiment, the sampling points refer to sampling points of each bit included in one byte of the communication signal, and the bits included in one byte may be a start bit, a data bit, and a stop bit. When the clock of the single chip microcomputer is normal, the deviation between the time interval between two adjacent sampling points in the communication signal and the preset sampling period is smaller than a preset threshold value, and when the deviation between the time interval between the adjacent sampling points and the preset sampling period is larger than the preset threshold value, the sampling points exceed corresponding bits or do not reach the corresponding bits, so that mis-sampling is caused, and data acquisition errors occur to bytes where the mis-sampled bits are located, namely, communication is abnormal. Meanwhile, the sampling point in the communication signal takes the singlechip clock as a time reference, so that the singlechip clock can be judged to be abnormal under the condition of abnormal communication.
The following describes a method for detecting clock abnormality of a single chip microcomputer in this embodiment by taking a communication signal between two single chip microcomputers as an example.
Fig. 3 exemplarily shows two singlechips in a communication state in this embodiment, as shown in the figure, in this embodiment, the first singlechip 21 and the second singlechip 22 adopt UART serial communication, and the baud rate of the UART serial communication is 9600, and the level width Tm of one bit of one byte in the communication signal is as shown in the following equation (1):
meanwhile, if a byte in the communication signal is set to include a start bit, 8 data bits and a stop bit, the transmission time Tbyte of a byte in the communication signal is as shown in the following formula (2):
Tbyte＝Tm×10≈1.04ms (2)
fig. 4 exemplarily shows sampling points of the communication signal in the present embodiment, as shown in the figure, the level width Tm =104 μ s of one bit of one byte of the communication signal in the present embodiment, and the sampling points are middle time points of the level width Tm.
Fig. 5 illustrates a normal sampling of one byte in the communication signal in the present embodiment, and as shown in the figure, each sampling point in the present embodiment is an intermediate time of the level width Tm of each bit in the byte.
Fig. 6 exemplarily shows abnormal sampling of one byte in a communication signal in this embodiment, as shown in the figure, it is set in this embodiment that an abnormality occurs when a clock of a single chip microcomputer at a fourth sampling point of the byte, the fourth sampling point is not a middle time of a level width Tm of a corresponding bit thereof and exceeds the middle time, so that a deviation of a time interval between the third sampling point and the fourth sampling point from a preset sampling period is greater than a preset threshold, which causes a tenth sampling point of the byte to exceed the corresponding bit, and as shown in an area marked by a coil in fig. 6, the bit cannot be correctly sampled, that is, communication abnormality.
Fig. 7 exemplarily shows abnormal sampling of a byte in another communication signal in this embodiment, as shown in the figure, in this embodiment, it is set that an abnormality occurs when a single chip microcomputer clock is at a fourth sampling point of the byte, the fourth sampling point is not a middle time of a level width Tm of a corresponding bit thereof and is smaller than the middle time, so that a deviation between a time interval between the third sampling point and the fourth sampling point and a preset sampling period is greater than a preset threshold, which causes that a tenth sampling point of the byte does not reach the corresponding bit thereof, and as an area marked by a coil in fig. 7, the bit cannot be correctly sampled, that is, communication is abnormal.
Further, based on the communication signal determination condition described in the foregoing embodiment of the method for detecting a clock abnormality of a single chip microcomputer, this embodiment further provides an embodiment of a preferable method for detecting a clock abnormality of a single chip microcomputer, which specifically includes:
step S201: and acquiring the oscillation deviation of the clock of the singlechip.
Step S202: comparing the obtained oscillation deviation with a preset oscillation deviation threshold: and if the obtained oscillation deviation is larger than a preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal.
The preset oscillation deviation threshold k in this embodiment is shown in the following formula (3):
the meaning of the parameter Terr in the formula (3) is the clock error time, and specifically, the clock error time Terr may be determined according to the following method in this embodiment:
and when the deviation between the time interval of adjacent sampling points in the acquired communication signal and the preset sampling period is greater than a preset threshold value, setting the clock error time as the time length between the rising edge of the sampling level in the communication signal and the preset sampling point. For example, the preset sampling point in the communication signal of the first and second singlechips 21 and 22 shown in fig. 3 is the middle time of the level width Tm of one bit of one byte of the communication signal, so that the clock error time Terr =52 μ s can be obtained.
Further, it can be obtained that the oscillation deviation threshold k =5% preset in the present embodiment is when the communication signal is abnormal. Therefore, when the oscillation deviation of the singlechip clock exceeds 5%, the singlechip clock can be judged to be abnormal.
In the embodiment, the oscillation deviation of the single chip microcomputer clock is taken as a criterion, so that the operability of the abnormal detection of the single chip microcomputer clock is improved.
Although the foregoing embodiments describe the steps in the above sequential order, those skilled in the art will understand that, in order to achieve the effect of the present embodiments, the steps may not be executed in such an order, and may be executed simultaneously (in parallel) or in an inverse order, and these simple variations are within the scope of the present invention.
Based on the same technical concept as the method embodiment, the embodiment of the invention also provides a device for detecting the clock abnormity of the single chip microcomputer. The following describes the device for detecting clock abnormality of a single chip microcomputer in detail with reference to the accompanying drawings.
Fig. 2 exemplarily shows a structure of the apparatus for detecting a clock abnormality of a single chip in the present embodiment, and as shown in the figure, the apparatus for detecting a clock abnormality of a single chip in the present embodiment may include a first signal acquiring module 11 and a first signal judging module 12. The first signal obtaining module 11 may be configured to obtain a communication signal between the single chip microcomputer and a preset device. The first signal determining module 12 may be configured to determine whether a deviation between a time interval of adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold: if the clock value is larger than the preset value, the clock of the single chip microcomputer is abnormal.
Specifically, the communication signal in this embodiment is a signal based on clock synchronization or a signal not based on clock synchronization.
Further, the apparatus for detecting clock abnormality of a chip in this embodiment may further include the following structure, specifically:
the apparatus for detecting clock abnormality of a chip computer in this embodiment may further include a second signal acquiring module and a second signal determining module. The second signal acquisition module can be configured to acquire oscillation deviation of the clock of the single chip microcomputer. The second signal determination module may be configured to compare the obtained oscillation deviation with a preset oscillation deviation threshold: and if the obtained oscillation deviation is larger than the preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal.
Meanwhile, the second signal determining module in this embodiment further includes a preset oscillation deviation threshold model k as shown in formula (3), and a clock error time calculating module. The clock error time calculation module may be configured to set the clock error time as a time length between a rising edge of a sampling level in the communication signal and a preset sampling point when a deviation of a time interval of adjacent sampling points in the acquired communication signal from the preset sampling period is greater than a preset threshold.
The above-mentioned embodiment of the apparatus for detecting clock abnormality of a single chip microcomputer can be used to implement the above-mentioned embodiment of the method for detecting clock abnormality of a single chip microcomputer, and the technical principle, the technical problems solved and the technical effects produced are similar, and it can be clearly understood by those skilled in the art that for convenience and conciseness of description, the specific working process and the related description of the above-mentioned described embodiment of the method for detecting clock abnormality of a single chip microcomputer can refer to the corresponding process in the above-mentioned embodiment of the method for detecting clock abnormality of a single chip microcomputer, and will not be described herein again.
Those skilled in the art will appreciate that the above-mentioned apparatus for detecting clock abnormality of a single chip microcomputer further includes some other known structures, such as a processor, a controller, a memory, etc., wherein the memory includes, but is not limited to, a random access memory, a flash memory, a read only memory, a programmable read only memory, a volatile memory, a non-volatile memory, a serial memory, a parallel memory or a register, etc., and the processor includes, but is not limited to, a CPLD/FPGA, a DSP, an ARM processor, a MIPS processor, etc., and these known structures are not shown in fig. 2 in order to unnecessarily obscure the embodiments of the present disclosure.
It should be understood that the number of individual modules in fig. 2 is merely illustrative. The number of modules may be any according to actual needs.
Those skilled in the art will appreciate that the modules in the device in an embodiment may be adaptively changed and disposed in one or more devices different from the embodiment. The modules or units or components of the embodiments may be combined into one module or unit or component, and furthermore they may be divided into a plurality of sub-modules or sub-units or sub-components. All of the features disclosed in this specification (including any accompanying claims, abstract and drawings), and all of the processes or elements of any method or apparatus so disclosed, may be combined in any combination, except combinations where at least some of such features and/or processes or elements are mutually exclusive. Each feature disclosed in this specification (including any accompanying claims, abstract and drawings) may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.
Various component embodiments of the invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. Those skilled in the art will appreciate that a microprocessor or Digital Signal Processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in a server, client, or the like, in accordance with embodiments of the present invention. The present invention may also be embodied as an apparatus or device program (e.g., PC program and PC program product) for carrying out a portion or all of the methods described herein. Such a program implementing the invention may be stored on a PC readable medium or may be in the form of one or more signals. Such a signal may be downloaded from an internet website, or provided on a carrier signal, or provided in any other form.
Based on the above embodiment of the method for detecting clock abnormality of a single chip, the present invention further provides a computer readable storage medium, in which a computer program may be stored. Meanwhile, the computer program can be suitable for being loaded and executed by a processor to realize the steps in the method for detecting the clock abnormality of the single chip microcomputer.
Based on the above embodiment of the method for detecting clock abnormality of a single chip, the present invention further provides a computer device, which may include a memory, a processor, and a computer program stored in the memory and operable on the processor. Meanwhile, when the processor executes a computer program, the steps in the method for detecting the clock abnormality of the single chip microcomputer can be realized.
Furthermore, those skilled in the art will appreciate that while some embodiments described herein include some features included in other embodiments, rather than other features, combinations of features of different embodiments are meant to be within the scope of the invention and form different embodiments. For example, in the claims of the present invention, any of the claimed embodiments may be used in any combination.
It should be noted that the above-mentioned embodiments illustrate rather than limit the invention, and that those skilled in the art will be able to design alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between parentheses shall not be construed as limiting the claim. The word "comprising" does not exclude the presence of elements or steps not listed in a claim. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The invention may be implemented by means of hardware comprising several distinct elements, and by means of a suitably programmed PC. In the unit claims enumerating several means, several of these means may be embodied by one and the same item of hardware. The usage of the words first, second and third, etcetera do not indicate any ordering. These words may be interpreted as names.
So far, the technical solutions of the present invention have been described in connection with the preferred embodiments shown in the drawings, but it is easily understood by those skilled in the art that the scope of the present invention is obviously not limited to these specific embodiments. Equivalent changes or substitutions of related technical features can be made by those skilled in the art without departing from the principle of the invention, and the technical scheme after the changes or substitutions can fall into the protection scope of the invention.
Claims (4)
1. A method for detecting clock abnormity of a single chip microcomputer is characterized by comprising the following steps:
acquiring a communication signal between the singlechip and preset equipment; the communication signal is a signal based on clock synchronization or a signal not based on clock synchronization;
judging whether the deviation of the time interval of the adjacent sampling points in the acquired communication signal and the preset sampling period is greater than a preset threshold value: if the clock frequency is larger than the preset frequency, the clock of the single chip microcomputer is abnormal;
the method further comprises the following steps:
acquiring oscillation deviation of the clock of the single chip microcomputer;
comparing the obtained oscillation deviation with a preset oscillation deviation threshold: if the obtained oscillation deviation is larger than the preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal;
the preset oscillation deviation threshold k is as follows:
wherein Terr is the clock error time, and Tbyte is the preset transmission time of one byte in the communication signal;
the method for determining the clock error time Terr comprises the following steps:
and when the deviation between the time interval of adjacent sampling points in the acquired communication signal and the preset sampling period is greater than a preset threshold value, setting the clock error time as the time length between the rising edge of the sampling level in the communication signal and the preset sampling point.
2. A singlechip clock anomaly detection device is characterized by comprising:
the first signal acquisition module is configured to acquire a communication signal between the single chip microcomputer and preset equipment; the communication signal is a signal based on clock synchronization or a signal not based on clock synchronization;
the first signal judgment module is configured to judge whether the deviation between the time interval of the adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold value: if the clock value is larger than the preset value, the clock of the single chip microcomputer is abnormal;
the device further comprises:
the second signal acquisition module is configured to acquire the oscillation deviation of the clock of the single chip microcomputer;
a second signal determination module configured to compare the obtained oscillation deviation with a preset oscillation deviation threshold: if the obtained oscillation deviation is larger than the preset oscillation deviation threshold value, the clock of the single chip microcomputer is abnormal;
the second signal judgment module comprises a preset oscillation deviation threshold model k shown as the following formula:
wherein, terr is the clock error time, and Tbyte is the preset transmission time of one byte in the communication signal;
the second signal judgment module also comprises a clock error time calculation module; the clock error time calculation module is configured to set the clock error time as a time length between a rising edge of a sampling level in the communication signal and a preset sampling point when a deviation between a time interval of adjacent sampling points in the acquired communication signal and a preset sampling period is greater than a preset threshold value.
3. A computer-readable storage medium, in which a computer program is stored, wherein the program is adapted to be loaded and executed by a processor to implement the steps of the method for detecting clock abnormality of a single chip microcomputer according to claim 1.
4. A computer device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, wherein the processor executes the program to implement the steps of the method for detecting clock abnormality of a single chip microcomputer according to claim 1.
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| CN111860164B (en) * | 2020-06-17 | 2024-02-06 | 深圳星康医疗科技有限公司 | Low-speed pacing detection method, device and storage medium |
| CN112104341B (en) * | 2020-08-10 | 2024-06-14 | 华帝股份有限公司 | System clock calibration method based on self-adaptive power grid power frequency |
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