CN108933113A - Equipped with wiring board, its semiconductor group body and its preparation method for being electrically isolated part and substrate plate - Google Patents
Equipped with wiring board, its semiconductor group body and its preparation method for being electrically isolated part and substrate plate Download PDFInfo
- Publication number
- CN108933113A CN108933113A CN201810293055.4A CN201810293055A CN108933113A CN 108933113 A CN108933113 A CN 108933113A CN 201810293055 A CN201810293055 A CN 201810293055A CN 108933113 A CN108933113 A CN 108933113A
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- China
- Prior art keywords
- substrate plate
- electric isolution
- routing circuit
- wiring board
- molding material
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
- H01L23/49894—Materials of the insulating layers or coatings
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4803—Insulating or insulated parts, e.g. mountings, containers, diamond heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/42—Fillings or auxiliary members in containers or encapsulations selected or arranged to facilitate heating or cooling
- H01L23/433—Auxiliary members in containers characterised by their shape, e.g. pistons
- H01L23/4334—Auxiliary members in encapsulations
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/562—Protection against mechanical damage
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Abstract
Wiring board of the invention includes by the lateral circular electric isolution part and molding material of substrate plate.The thickness for running through in opening, and being electrically isolated part that the electric isolution part is inserted in the substrate plate is greater than the thickness of substrate plate.The molding material covers the top side of the substrate plate and is electrically isolated the side wall of part, and provides reliable interface, so that routing circuit is deposited on.The substrate plate can be used as locating piece when putting separator, or/and provide another way by improve the electrical wiring flexibility ratio of wiring board.
Description
Technical field
The present invention is about a kind of wiring board, its semiconductor group body and its preparation method, and espespecially a kind of be equipped with is electrically isolated part and substrate
The wiring board of plate, its semiconductor group body and its preparation method.
Background technique
Such as the high voltage or high current application of power module or light emitting diode (LED), high-effect route need to be usually used
Plate, so that signal interconnection.However, big calorimetric caused by semiconductor chip will be such that element efficiency deteriorates when power increases, and
Also thermal stress can be caused to chip.Accordingly, since ceramic material (such as aluminium oxide or aluminium nitride) is thermally conductive and electrically insulating material, and
With low thermal coefficient of expansion (CTE), therefore often it is considered as the suitable material of such application.United States patent (USP) reference number 8,895,998 and 7,
670,872 have disclosed various interconnection structures, use ceramics to connect as chip and set cushion material, to reach preferable reliability.This
Outside, the preferred wiring board that copper (direct bond copper, DBC) plate has become many high power module applications is directly covered.DBC
Plate is usually made of ceramic spacer, such as Al2O3(aluminium oxide), A1N (aluminium nitride) or Si3N4(silicon nitride), and burnt by high temperature
Diffusion technique is tied, in layers of copper in two face bondings of ceramics.However, thick copper sheet, which is bonded to separator, usually requires very high burning
Junction temperature, and need certain material or condition that could obtain reliable copper/ceramic interface, will so will lead to qualification rate decline and
Technique is more complicated.Furthermore it directly covers the metallization process in copper technology and usually requires the copper for being all sintered same thickness in two sides
Plate, to avoid ceramic wafer prying.The thick copper of bottom side can be used as radiating seat, but the copper of top side can cause to etch because of thickness problem
Resolution ratio is bad, makes wiring ability critical constraints.Therefore, the flip or surface that are suitable for power module group body are bonded
For (surface mount attachment) technology, existing DBC plate is simultaneously improper.
Summary of the invention
The main purpose of the present invention is to provide a kind of wiring boards, and the high thermal conductivity separator of low CTE is embedded in molding
In material, to solve the problems, such as that thermal expansion coefficient is unmatched between chip and wiring board, and molding material can provide reliable interface, for
Routing circuit is deposited on, thus improves the mechanical reliability and thermal characteristics of semiconductor group body.
Another object of the present invention is to provide a kind of wiring boards, and separator is inserted in and is open running through for substrate plate
In, so that substrate plate is can be used as locating piece when placing separator, avoids separator from being displaced in molding technique, and route can be improved
The electrical wiring flexibility ratio of plate.
According to above-mentioned and other purposes, the present invention provides a kind of wiring board equipped with electric isolution part and vertical connections,
Including：One substrate plate runs through opening it includes a top side, a bottom side, positioned at multiple top contact pads of the top sides and one,
Wherein the bottom side should be extended to from the top side through the inner sidewall of opening；One is electrically isolated part, this for being set to the substrate plate passes through
It wears in opening, wherein the bottom surface of the electric isolution part and the bottom side of the substrate plate are in substantially coplanar, and the electric isolution part
Thickness is greater than the thickness of the substrate plate；One molding material, covers the top side of the substrate plate, and extends into the electric isolution part
Peripheral edge and should be through the gap between the inner sidewall of opening, the wherein outer surface of the molding material and the electric isolution part
Top surface is in substantially coplanar；One routing circuit is set on the outer surface of the molding material；And multiple vertical connections
Part is set on the top side of the substrate plate, and is embedded into the molding material, and is electrically coupled to the routing circuit and the base
The top contact pads of bottom plate.In addition, the present invention also provides a kind of semiconductor group body comprising semiconductor element, which connects, to be placed in
On the electric isolution part top surface of above-mentioned wiring board, and it is electrically connected to routing circuit.
In another program, the present invention provides a kind of equipped with the method for manufacturing circuit board for being electrically isolated part comprising Xia Shubu
Suddenly：One substrate plate is provided, it includes a top side, a bottom side and one through opening, wherein should through opening inner sidewall from the top
Side extends to the bottom side；One electric isolution part is inserted into and was open should running through for the substrate plate, and the peripheral edge of the electric isolution part leans on
Closely should be through the inner sidewall of opening, and the bottom side of the bottom surface of the electric isolution part and the substrate plate is in substantial coplanar,
Wherein the thickness of the electric isolution part is greater than the thickness of the substrate plate；A molding material is provided on the top side of the substrate plate, and should
Molding material extends into the peripheral edge of the electric isolution part and should run through the gap between the inner sidewall of opening, wherein
The outer surface of the molding material and the top surface of the electric isolution part are in substantially coplanar；And a routing circuit is formed in the molding material
The outer surface on.
The step of must occurring unless specifically described or sequentially, there is no restriction for the sequences of above-mentioned steps in listed above, and
It can change or rearrange according to required design.
Wiring board, semiconductor group body and its preparation method of the invention has many advantages.For example, part insertion will be electrically isolated
Substrate plate is especially advantageous, which is because, substrate plate can ensure that being electrically isolated part is accurately set in opening
It puts and/or substrate plate can provide the routing circuit on molding material further routing.It is connected in deposited vertical on substrate plate
Part can provide vertical interface channel, and the routing circuit on molding material is mutually connected to substrate plate.Molding material is bonded to electric isolution
The practice of part can provide a platform, so that high-resolution circuit can be deposited on the platform, and then make have subtle pad spacing
Component is able to be connected on the wiring board such as crystal covered chip and surface adhesion components (surface mount component).
Above-mentioned and other features and advantages of the invention can be more clear bright by the detailed narration of embodiments discussed below
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Detailed description of the invention
With reference to attached drawing, the present invention can be more clear by the narration in detail of embodiments discussed below, wherein：
Fig. 1 and 2 is respectively the diagrammatic cross-section and top perspective schematic diagram of substrate plate in first embodiment of the invention；
Fig. 3 and 4 is respectively to provide the section signal of vertical connections in first embodiment of the invention in Fig. 1 and 2 structures
Figure and top perspective schematic diagram；
Fig. 5 and 6 is respectively in first embodiment of the invention, in Fig. 3 and 4 structures formed through opening diagrammatic cross-section and
Top perspective schematic diagram；
Fig. 7 and 8 is respectively that the diagrammatic cross-section for being electrically isolated part is provided in Fig. 5 and 6 structures in first embodiment of the invention
And top perspective schematic diagram；
Fig. 9 is that the diagrammatic cross-section of molding material is provided in Fig. 7 structure in first embodiment of the invention；
Figure 10 is in first embodiment of the invention, by the diagrammatic cross-section of the molding material upper half removal in Fig. 9 structure；
Figure 11 and 12 is respectively that routing circuit and bottom coating are provided in Figure 10 structure in first embodiment of the invention
To complete the diagrammatic cross-section and top perspective schematic diagram of wiring board production；
Figure 13 and 14 is respectively that the section of semiconductor element is provided in Figure 11 and 12 structures in first embodiment of the invention
Schematic diagram and top perspective schematic diagram；
Figure 15 is the wiring board diagrammatic cross-section of another program in first embodiment of the invention；
Figure 16 is the wiring board diagrammatic cross-section of another aspect in first embodiment of the invention；
Figure 17 is the wiring board diagrammatic cross-section of yet another aspect in first embodiment of the invention；
Figure 18 is the wiring board diagrammatic cross-section of another program in first embodiment of the invention；
Figure 19 is that the diagrammatic cross-section of top dielectric is provided in Figure 11 structure in second embodiment of the invention；
Figure 20 is to provide top conductor line in Figure 19 structure in second embodiment of the invention to complete cuing open for wiring board production
Face schematic diagram；
Figure 21 is that the diagrammatic cross-section of semiconductor element is provided in Figure 20 structure in second embodiment of the invention；
Figure 22 is the diagrammatic cross-section of wiring board in third embodiment of the invention；
Figure 23 is the wiring board diagrammatic cross-section of another program in third embodiment of the invention；
Figure 24 is to provide semiconductor element in Figure 22 structure in third embodiment of the invention and the section of passive device shows
It is intended to；
Figure 25 is to provide semiconductor element in Figure 22 structure, passive and sealing material cut open in third embodiment of the invention
Face schematic diagram；
Figure 26 is that semiconductor element, passive and close is provided in the wiring board of another program in third embodiment of the invention
Seal the diagrammatic cross-section of material；
Figure 27 is that semiconductor element, passive and close is provided in the wiring board of another aspect in third embodiment of the invention
Seal the diagrammatic cross-section of material；
Figure 28 is the diagrammatic cross-section of another wiring board in fourth embodiment of the invention；
Figure 29 is the diagrammatic cross-section of another wiring board in fifth embodiment of the invention；
Figure 30 is that the diagrammatic cross-section of bottom dielectric layer is provided in Figure 29 structure in sixth embodiment of the invention；
Figure 31 is to provide base conductor in Figure 30 structure in sixth embodiment of the invention to complete cuing open for wiring board production
Face schematic diagram.
【Symbol description】
Wiring board 100,200,300,400,500,600
Semiconductor group body 110,120,130,140,150,210,310,320,330,340,350
Substrate plate 10
Top side 101,201
Bottom side 103
Through opening 105
Gap 107
Inner sidewall 109
Core layer 12
Top line layer 13
Top contact pads 131
Bottom metal layers 15
Bottom line layer 16
Bottom engagement pad 161
Insulating layer 17
Metallize perforation 18
Vertical connections 20
Metal column 21
Metal filling perforation 23
Conducting sphere 25
It is electrically isolated part 30
Top surface 301
Bottom surface 303
Molding material 40
Outer surface 401
Blind hole 41,913,933
Routing circuit 50
Heat conductive pad 51
Plated-through hole 55
Bottom coating 60
Semiconductor element 71,72
Passive device 73
Conductive bump 81
Closing line 83
Sealing material 89
Top build-up circuitry 91
Top dielectric 911
Top conductor line 915
Metalized blind vias 917,937
Bottom build-up circuitry 93
Bottom dielectric layer 931
Base conductor 935
Specific embodiment
Hereinafter, it will thus provide embodiment is with the embodiment that the present invention will be described in detail.Advantages of the present invention and effect
Content disclosed through the invention is more significant.Illustrate that appended attached drawing is to simplify and used as illustrating herein.It is attached
Number of elements, shape and size shown in figure can modify according to actual conditions, and the configuration of element is likely more again
It is miscellaneous.Otherwise practice or application can also be carried out in the present invention, and without departing from the item of spirit and scope defined in the present invention
Under part, various change and adjustment can be carried out.
[embodiment 1]
Fig. 1-12 is a kind of production method figure of wiring board in first embodiment of the invention comprising one is electrically isolated part, one
Substrate plate, multiple vertical connections, a molding material, a routing circuit and a bottom coating.
Fig. 1 and Fig. 2 is respectively the diagrammatic cross-section and top perspective schematic diagram of substrate plate 10.In this present embodiment, the base
Bottom plate 10 includes the top line layer 13 for being located at top side 101, positioned at the bottom metal layers 15 of bottom side 103 and positioned at top route
Insulating layer 17 between layer 13 and bottom metal layers 15.17 cocoa of insulating layer is by ceramics, glass, epoxy resin, molding material, glass
Made by epoxy resin, polyimides or its analog.The top line layer 13 is usually patterned copper layer, and includes multiple
Top contact pads 131 (as shown in Figure 2).The bottom metal layers 15 are non-patterned layers of copper, and the insulation is completely covered by lower section
Layer 17.
Fig. 3 and Fig. 4 is respectively the diagrammatic cross-section and top perspective that vertical connections 20 are formed on 10 top side 101 of substrate plate
Schematic diagram.The vertical connections 20 can be made of Cu, Sn, Ti, Ni, Au, Ag, Sn alloy or other suitable conductive materials,
Wherein Sn alloy can contain Ag, Cu, Bi or combinations thereof.Here, can by vacuum splashing and plating, plating, welding (soldering), beat
Line, electric welding (welding) or other appropriate methods, in formation metal column, soldered ball, engagement on the top line layer 13 of substrate plate 10
Line or combinations thereof, using as vertical connections 20.In addition, vertical connections 20 may be made as coupling type structure.For example, vertically connecting
Fitting 20 can be for maqting type solder projection or with the maqting type copper post for linking solder layer.Solder described herein may include lead
(such as Sn/Pb) or be free of lead (such as Au/Sn or Sn/Ag/Cu).In this figure, the vertical connections 20 are the gold that plating is formed
Belong to column 21, is electrically connected on the top contact pads 131 of top line layer 13.
Fig. 5 and Fig. 6 is respectively diagrammatic cross-section and the top perspective signal formed in substrate plate 10 through opening 105
Figure.The inner sidewall 109 for running through opening 105 is to be extended through by 10 top side 101 of substrate plate to 10 bottom side 103 of substrate plate, and pass through
Wearing opening 105 can be formed by various technologies, such as punching (punching), drilling or laser cutting.
Fig. 7 and Fig. 8 is respectively to be electrically isolated diagrammatic cross-section and top of the 30 basement plate 10 of part in opening 105 to stand
Body schematic diagram.The electric isolution part 30 usually has elastic modulus and low thermal coefficient of expansion (for example, 2x 10-6K-1To 10x
10-6K-1), it may be, for example, the electrically insulating material of ceramics, silicon, glass or other tool thermal conduction characteristics.In this embodiment, the electricity every
Off member 30 is ceramic block, and thickness is substantially equal to 10 thickness of substrate plate plus 20 height of vertical connections, and is placed in base
Running through for bottom plate 10 is open in 105, and wherein the bottom side 103 of substrate plate 10 can and be electrically isolated the bottom surface 303 of part 30 in substantial total
Plane.Size due to running through opening 105, which is greater than, is electrically isolated part 30, therefore 10 inner sidewall 109 of substrate plate and 30 periphery of electric isolution part
It is located at the gap 107 in opening 105 between edge there are one.107 side of gap is electrically isolated part 30 to circular, while by substrate
10 flanked of plate.In certain examples, the inner sidewall 109 of substrate plate 10 can be used as locating piece, be put with ensuring to be electrically isolated part 30
Accuracy when setting.Accordingly, it can will be electrically isolated part 30 and accurately be limited to pre-position, and be electrically isolated the peripheral edge of part 30
It can be close to substrate plate 10 through the inner sidewall 109 of opening 105.
Fig. 9 is the diagrammatic cross-section to form molding material 40.The molding material 40 can be by being coated on substrate plate for molding material
It is formed in gap 107 on 10 top sides 101, on electric isolution 30 top surface 301 of part and between substrate plate 10 and electric isolution part 30,
Wherein molding material can print (paste printing), pressing mold forming (compressive molding), metaideophone by rubber cement
Shape (transfer molding), liquid injection molding (liquid injection molding), rotary coating (spin
Coating) or other are suitble to mode to be coated with.Then, it is heat-treated (or setting process), hardens molding material,
Molding material is converted to solid-state mold compound.Accordingly, molding material 40 can cover from above substrate plate 10, vertical connections
20 and be electrically isolated part 30, and laterally cover, surround and similar shape be coated 10 inner sidewall 109 of substrate plate, 20 side wall of vertical connections and
It is electrically isolated 30 side wall of part.
Molding material 40 generally includes to cohere resin, filling material, curing agent, diluent and additive.It is used in the present invention
Cohere resin have no it is specifically limited.For example, cohering resin can be selected from by epoxy resin, phenol resin, polyimides (polyimide)
Resin, Polyurethane (polyurethane) resin, silica resin, polyester resin, acrylic acid (acrylate) resin, span carry out acyl
At least one of imines (bismaleimide, BMI) resin and its equivalent Suo Zu group.Cohere resin can in attachment material with
Close cohesion is provided between filling material.Cohering resin can also be connected by filling the chain of material, to provide heat conductivity.In addition,
The physics and chemical stability of molding material 40 can be improved by cohering resin also.
In addition, filling material used in the present invention have no it is specifically limited.For example, can be used conductive filler material, selected from by
Group composed by aluminium oxide, aluminium nitride, silicon carbide, tungsten carbide, boron carbide, silica and its equivalent.More specifically,
If having filling material dispersion appropriate wherein, molding material 40 can become with thermal conductivity or have low thermal coefficient of expansion
(CTE).For example, aluminium nitride (AlN) or silicon carbide (SiC) have relatively high thermal conductivity, relatively high resistance and opposite
Low thermal expansion coefficient.Accordingly, when used in molding material 40 such material as filling material when, then molding material 40 can show compared with
Good heat dissipation, electrical isolation efficiency, and its low CTE characteristic can avoid circuit or interface occurs removing or crackle.Conductive filler
The maximum particle diameter of material can be for 25 μm or less than 25 μm.The content for filling material can be in the range of 10 to 90 weight percent.If leading
The content of heat filling material is lower than 10 weight percent, then may cause heat conductivity deficiency and viscosity is too low.Low-viscosity indicates, is applying
In cloth or molding process, resin is too easy to flow out from tool, so that technique is not easy to operate and controls.On the other hand, if filling
The content of material is higher than 90 weight percent, then may cause the bond strength decline of molding material, and viscosity is excessively high.It is full-bodied
Molding material can be because in coating or molding process, and material can not be flowed out by tool, thus cause operability bad.In addition,
Molding material 40 may include more than one filling material.For example, can be used polytetrafluoroethylene (PTFE) (PTFE) as second filling material, with into
The electrical insulation characteristics of one step improvement molding material 40.In short, molding material 40 preferably has greater than the modulus of elasticity and about 5x of 1.0GPa
10-6K-1To 15x 10-6K-1Thermal linear expansion coefficient in range.
Figure 10 is the diagrammatic cross-section removed behind 40 upper half of molding material.Here, molding can be removed by flatening process
The upper half of material 40, to appear vertical connections 20 from top and be electrically isolated part 30, wherein flatening process can be to smear mill/disc sharpener
(lapping/grinding) technique or chemical mechanical grinding (CMP) technique.After planarization, molding material 40 with a thickness of
0.05mm to 1mm (in preferably 0.1 to 0.4mm) range, and the outer surface 401 of molding material 40 and 20 top side of vertical connections
201 and be electrically isolated 30 top surface 301 of part in substantially it is coplanar.
The diagrammatic cross-section of routing circuit 50 respectively is made by metal pattern sedimentation by Figure 11 and 12 and top is stood
Body schematic diagram.Firstly, can be by various technologies, such as plating, electroless-plating, vapor deposition, sputter or combinations thereof carries out structure top surface
Metallization, to form the conductive layer (usually layers of copper) of single-layer or multi-layer.The conductive layer can by Cu, Ni, Ti, Au, Ag, Al, its
Combination or other suitable conductive materials are made.In general, can be before electroplated conductive layer to required thickness most prior to structure
Top surface forms seed layer, and wherein seed layer can be made of a diffusion barrier and plating carrier layer (plating bus layer).
The diffusion barrier is the oxidation or erosion for offsetting conductive layer (such as copper).In most of example, diffusion barrier can also be done
For the enhancement layer that sticks together of subsurface material, and can be formed by physical vaporous deposition (PVD), for example, can sputter form thickness about
Ti or TiW layers of 0.01 μm to 0.1 μm.However, diffusion barrier can also be made of other materials, such as TaN or other applicable materials
Material, thickness are not limited to above range.Plating carrier layer is usually to be made of the material for being identical to conductive layer, and thickness range is about
It is 0.1 μm to 1 μm.For example, if plating carrier layer is preferably physical vaporous deposition or wireless plating technology when conductive layer is copper
Made Copper thin film.However, plating carrier layer can also be made of other applicable materials, such as silver, gold, chromium, nickel, tungsten or its group
It closes, thickness is not limited to above range.
After depositing seed layer, in formation photoresist layer (not shown) on seed layer.The photoresist layer can pass through wet type work
Skill (such as spin coating proceeding) or dry process (such as pressing dry film) and formed.It is carried out after forming photoresist layer, then to photoresist layer
Patterning, to form aperture, is then filled up in aperture coated metal (such as copper), and then forms routing circuit 50.Plate metal
Afterwards, then by etching technics, to remove the seed layer appeared, and then conducting wire electrically isolated from one is formed.In this figure, routing electricity
Road 50 is patterned metal layer, extends laterally in 40 outer surface 401 of molding material and is electrically isolated on 30 top surface 301 of part, and contacts
And vertical connections 20 are electrically coupled to, while hot be conducted to is electrically isolated part 30.In addition, also may be selected to carry out structure floor
Metallization contacts from below and is completely covered the bottom metal layers 15 of substrate plate 10 to form bottom coating 60, is electrically isolated
Part 30 and molding material 40.
Accordingly, as shown in Figure 11 and 12, completed wiring board 100 includes a substrate plate 10,20, one electricity of vertical connections
Separator 30, a molding material 40, a routing circuit 50 and a bottom coating 60.The electric isolution part 30 is set to substrate plate 10
In opening 105, and the thickness for being electrically isolated part 30 is greater than the thickness of substrate plate 10.Vertical connections 20 are set to substrate plate 10
Top line layer 13 on, and be electrically coupled to top line layer 13.Molding material 40 covers and around 20 side wall of vertical connections
And it is electrically isolated 30 side wall of part, to provide mechanical engaging force in 10 inner sidewall 109 of substrate plate and between being electrically isolated 30 peripheral edge of part.Road
It is extended laterally in 40 outer surface 401 of molding material by circuit 50 and is electrically isolated on 30 top surface 301 of part, to provide horizontal routing, and electricity
Property be coupled to the vertical connections 20 that vertically route be provided.Therefore, routing circuit 50 can be electrically connected by vertical connections 20
To the top line layer 13 of substrate plate 10.Bottom coating 60 is continuous and non-patterned metal layer, is set to substrate plate 10
And it is electrically isolated the lower section of part 30, to provide the radiating surface that area is greater than electric isolution part 30.
Figure 13 and 14 is respectively the semiconductor group body that semiconductor element 71 is electrically connected to wiring board 100 shown in Figure 11 and 12
110 diagrammatic cross-section and top perspective schematic diagram.Semiconductor element 71 (being depicted as chip) is to connect to be placed in electricity with rewinding method
On the top surface of separator 30, and routing circuit 50 is electrically coupled to by conductive bump 81.
Figure 15 is the wiring board diagrammatic cross-section of another program in first embodiment of the invention.The wiring board 120 is similar to
Structure shown in Figure 11, difference is, it includes there is metal filling perforation 23, using as vertical connections 20.Here, can be by molding
Deposited metal in the blind hole 41 of material 40, to form the metal filling perforation 23 of contact 10 top line layer 13 of substrate plate.
Figure 16 is the wiring board diagrammatic cross-section of another aspect in first embodiment of the invention.The wiring board 130 is similar to
Structure shown in Figure 11, difference is, it includes there is conducting sphere 25 (such as copper ball), using as vertical connections 20.
Figure 17 is the wiring board diagrammatic cross-section of yet another aspect in first embodiment of the invention.The wiring board 140 is similar to
Structure shown in Figure 11, difference is, it includes having metal filling perforation 23 and conducting sphere 25, using as vertical connections 20.Here, can
By the deposited metal in the blind hole 41 of molding material 40, to form the metal filling perforation 23 of contact conducting sphere 25.
Figure 18 is the wiring board diagrammatic cross-section of another program in first embodiment of the invention.The wiring board 150 is similar to
Structure shown in Figure 11, difference are, further include the passive device 73 being embedded into molding material 40.The electrical coupling of the passive device 73
It is connected to the top line layer 13 of substrate plate 10, thus routing circuit 50 can be electrically connected to by vertical connections 20.
[embodiment 2]
Figure 19-20 is the method for manufacturing circuit board figure in second embodiment of the invention with top build-up circuitry.
For the purpose of brief description, any narration for making same application, and need not all and in this in above-described embodiment 1
Repeat identical narration.
Figure 19 is the diagrammatic cross-section that top dielectric 911 and blind hole 913 are more formed in Figure 11 structure, wherein top dielectric
Layer 911 is located at routing circuit 50, is electrically isolated on part 30 and molding material 40, and blind hole 913 is then formed in top dielectric 911.
The top dielectric 911 can generally be deposited by lamination or coating method, and contact is electrically isolated part 30, the road molding Cai40Ji
By circuit 50, and is covered by top and extended laterally on electric isolution part 30, molding material 40 and routing circuit 50.Top dielectric
911 usually with 50 microns of thickness, and can be made by epoxy resin, glass epoxy resin, polyimides or its analog
At.After depositing top dielectric 911, blind hole 913 can be formed by various technologies comprising laser drill, plasma are carved
Erosion and photoetching technique, and blind hole 913 is usually with 50 microns of diameter.Pulse laser can be used to improve laser drill efficiency.Or
Scanning laser beam, and metal light cover of arranging in pairs or groups can be used in person.Blind hole 913 extends through top dielectric 911, and is directed at routing electricity
The selected part on road 50.
With reference to Figure 20, top conductor line 915 is formed in top dielectric 911 by metal deposit and metal patterning processes
On.Top conductor line 915 extends upward from routing circuit 50, and fills up blind hole 913, to form the gold for directly contacting routing circuit 50
Categoryization blind hole 917, while extending laterally in top dielectric 911.Therefore, top conductor line 915 can provide the water of X and Y-direction
Ordinary mail number routing and the vertical routing across blind hole 913, using the electric connection as routing circuit 50.
Top conductor line 915 can be deposited as single-layer or multi-layer by various technologies, such as plating, electroless-plating, vapor deposition, sputter or
A combination thereof.For example, produce top dielectric 911 and electroless copper by immersing the structure in activator solution first
Raw catalyst reaction, is then coated a thin copper layer as seed layer in a manner of electroless-plating, then with plating mode by required thickness
The second layers of copper be formed on seed layer.Alternatively, the seed layer can pass through sputtering way before depositing copper electroplating layer on seed layer
Form such as titanium/copper crystal seed layer film.Once reaching required thickness, that is, various technology patterning coatings can be used, with shape
Etched at top conductor line 915, such as wet etching, electrochemical etching, laser assisted or combinations thereof, and (figure is not using etching mask plate
Show), to define top conductor line 915.
Accordingly, as shown in figure 20, completed wiring board 200 includes a substrate plate 10, the electric isolution of vertical connections 20, one
Part 30, a molding material 40, a routing circuit 50, a bottom coating 60 and a top build-up circuitry 91.In this figure, the top
Build-up circuitry 91 is multilayer build-up circuitry comprising a top dielectric 911 and top conductor line 915.Accordingly, top line layer
13, the combination of vertical fitting 20 and top build-up circuitry 91 semiconductor element being assembled on wiring board 200 can be provided routing/
Interconnection.
Figure 21 is the diagrammatic cross-section of semiconductor group body 210, and semiconductor element 71 is electrically connected to the route of Figure 20
Plate 200.Semiconductor element 71 (being depicted as chip) alignment is electrically isolated part 30, and is connect with rewinding method and be placed in top build-up circuitry 91
On, to be electrically coupled to top conductor line 915 by conductive bump 81.Since top build-up circuitry 91 can be by as heat-dissipating pipe
Metalized blind vias 917 and the electric isolution hot conducting of part 30, therefore heat caused by semiconductor element can be conducted to after being electrically isolated part 30
It dissipates out again.
[embodiment 3]
Figure 22 is the wiring board diagrammatic cross-section of third embodiment of the invention, and routing circuit is electrically connected to substrate plate
Bottom line layer.
For the purpose of brief description, any narration for making same application, and need not all and in this in above-described embodiment
Repeat identical narration.
The wiring board 300 is similar with structure shown in Figure 11, and difference is, which is multilayer circuit board, and bottom
Coating 60 is patterned metal layer.In this figure, which includes a core layer 12, a top line layer 13, a bottom
Portion's line layer 16 and metallization perforation 18.The top line layer 13 and the bottom line layer 16 are extended laterally respectively in core layer 12
Two sides on.Top line layer 13 includes top contact pads 131, is electrically connected to vertical connections 20, and bottom route
Layer 16 includes bottom engagement pad 161, is electrically connected with following one level.The metallization perforation 18 extends through core layer 12, with
Electric connection between top contact pads 131 and bottom engagement pad 161 is provided.Therefore, it is electrically isolated outside 30 top surface of part and molding material 40
Routing circuit 50 on surface can be electrically connected to base by vertical connections 20, top line layer 13 and metallization perforation 18
The bottom line layer 16 of bottom plate 10.In this present embodiment, which is not limited to multilayer circuit board, also can be common burning porcelain
(co-fired ceramic), molding substrate (molded interconnect substrate, abbreviation MIS) or increasing layer substrate.
Figure 23 is the wiring board diagrammatic cross-section of another program in third embodiment of the invention.The wiring board 310 it is similar with
Structure shown in Figure 22, difference are, further include the plated-through hole 55 of direct contact routing circuit 50 and bottom line layer 16.
The plated-through hole 55 extends through substrate plate 10 and molding material 40, and provides routing circuit 55 and 10 bottom route of substrate plate
Electric connection between layer 16.
Figure 24 is the semiconductor group body that semiconductor element 71 and passive device 73 are electrically connected to wiring board 300 shown in Figure 22
320 diagrammatic cross-section.Semiconductor element 71 is to be connect on the top surface for being placed in and being electrically isolated part 30 with rewinding method, and pass through conductive stud
Block 81 is electrically coupled to routing circuit 50.Passive device 73, which then connects, to be placed on the top side of molding material 40, and is electrically coupled to routing
Circuit 50.
Figure 25 is the semiconductor group body diagrammatic cross-section of another program in third embodiment of the invention.The semiconductor group body
330 are similar to structure shown in Figure 24, and it further includes additional semiconductor element 72 and sealing material 89 that difference, which is,.This is additionally partly led
Volume elements part 72, which connects, to be placed on semiconductor element 71, and by closing line 83, is electrically coupled to routing circuit 50.The sealing material 89 is then
By top covering semiconductor element 71,72, passive device 73 and closing line 83.
Figure 26 is the semiconductor group body diagrammatic cross-section of another aspect in third embodiment of the invention.The semiconductor group body
340 are similar to structure shown in Figure 24, and difference is, (i) routing circuit 50, which does not extend laterally to, is electrically isolated on part 30, and (ii) is partly led
Volume elements part 71 connects to be placed in and be electrically isolated on part 30, and is electrically coupled to routing circuit 50 by closing line 83, and it is close that (iii) more provides one
Material 89 is sealed, by top covering semiconductor element 71, passive device 73 and closing line 83.
Figure 27 is the semiconductor group body diagrammatic cross-section of yet another aspect in third embodiment of the invention.The semiconductor group body
350 are similar to structure shown in Figure 26, and difference is, which more extends laterally in being electrically isolated on part 30, in electricity every
One heat conductive pad 51 is provided between off member 30 and semiconductor element 71.In this figure, the heat conductive pad 51 is electrical by vertical connections 20
It is connected to substrate plate 10, to constitute grounding connection.
[embodiment 4]
Figure 28 is the wiring board diagrammatic cross-section of fourth embodiment of the invention, is not embedded into vertical connections in molding material.
For the purpose of brief description, any narration for making same application, and need not all and in this in above-described embodiment
Repeat identical narration.
The wiring board 400 is similar with structure shown in Figure 11, and difference is, the not set top line layer in 10 top side of substrate plate,
And it does not deposit and to form vertical connections in 10 top side of substrate plate.In this present embodiment, the controllable electricity of the inner sidewall 109 of substrate plate 10
Accuracy when separator 30 is put.Accordingly, it can will be electrically isolated part 30 to be accurately controlled in pre-position, and be electrically isolated part 30
Peripheral edge can be close to substrate plate 10 through 105 inner sidewalls 109 of opening.In addition, substrate plate 10 also can be single layer structure, and
It can be made of composite material, such as FR-4 (being soaked with the weaving glass fiber cloth of epoxy resin, have flame resistance), bismaleimide
Amine-triazine resin (bismaleimide-triazine (BT) resin), molding material, ceramics, glass, plastics, metal or
Other materials.
[embodiment 5]
Figure 29 is the wiring board diagrammatic cross-section of fifth embodiment of the invention, with top build-up circuitry, electrically to connect
It is connected to the bottom line layer of substrate plate.
For the purpose of brief description, any narration for making same application, and need not all and in this in above-described embodiment
Repeat identical narration.
The wiring board 500 is similar with structure shown in Figure 22, and it further includes a top build-up circuitry 91 that difference, which is,.In this
In figure, which is multilayer build-up circuitry comprising a top dielectric 911 and top conductor line 915.The top
The contact of dielectric layer 911 is electrically isolated part 30, molding material 40 and routing circuit 50, and is covered by top and extended laterally in electric isolution part
30, on molding material 40 and routing circuit 50.Top conductor line 915 is extended laterally in top dielectric 911, and including being located at top
Metalized blind vias 917 in dielectric layer 911.Therefore, which can be by the metal that contacts with routing circuit 50
Change blind hole 917, be electrically connected to routing circuit 50, and be electrically isolated the hot conducting of part 30.
[embodiment 6]
Figure 30-31 is the wiring board production with top build-up circuitry and bottom build-up circuitry in sixth embodiment of the invention
Method figure.
For the purpose of brief description, any narration for making same application, and need not all and in this in above-described embodiment
Repeat identical narration.
Figure 30 is the diagrammatic cross-section that bottom dielectric layer 931 and blind hole 933 are formed in Figure 29 structure, wherein bottom dielectric layer
931 are located on bottom coating 60, and blind hole 933 is located in bottom dielectric layer 931.The bottom dielectric layer 931 contacts bottom quilt
Coating 60, and covered by lower section and extended laterally on bottom coating 60.The blind hole 933 extends through bottom dielectric layer
931, and it is directed at the selected position of bottom coating 60.
With reference to Figure 31, base conductor 935 is formed in bottom dielectric layer 931 by metal deposit and metal patterning processes
On.Base conductor 935 extends downward from bottom coating 60, and fills up blind hole 933, directly contacts bottom coating 60 to be formed
Metalized blind vias 937, while extending laterally in bottom dielectric layer 931.In this stage, bottom build-up circuitry 93 is just formed
In the lower section of substrate plate 10 and electric isolution part 30, and by metalized blind vias 937, it is electrically coupled to the bottom route of substrate plate 10
Layer 16 and it is hot be conducted to be electrically isolated part 30.In this figure, which is multilayer build-up circuitry comprising bottom
Dielectric layer 931 and base conductor 935.
Accordingly, as shown in figure 31, completed wiring board 600 includes a substrate plate 10, the electric isolution of vertical connections 20, one
Part 30, a molding material 40, a routing circuit 50, a bottom coating 60, a top build-up circuitry 91 and a bottom build-up circuitry
93.In this present embodiment, the combination of substrate plate 10, vertical connections 20 and routing circuit 50 can be in top build-up circuitry 91 and bottom
Electric connection is provided between portion's build-up circuitry 93, so that wiring board 600 has heap stack capability.In addition, the gold of top build-up circuitry 91
The metalized blind vias 937 of categoryization blind hole 917 and bottom build-up circuitry 97 can be used as the heat conducting pipe of heat transmission.
As shown in the embodiment above, the present invention builds up a kind of unique wiring board, has and is electrically isolated part and substrate
Plate, and reliability is good.Preferably, which mainly includes an electric isolution part, a substrate plate, a molding material and a routing electricity
Road, wherein (i) be electrically isolated part be inserted in substrate plate through opening in, and be electrically isolated part thickness be greater than substrate plate thickness；
(ii) molding material covering substrate plate top side and electric isolution part side wall, and fill up and be electrically isolated part peripheral edge and run through opening inner side wall
Between gap；(iii) routing circuit is deposited on molding material outer surface, and is selectively further extended laterally in electric isolution
On part top surface.
The wiring board more may include multiple vertical connections, wherein (i) top side of each vertical connections is not by molding material
Covering, and bottom side then contacts and is electrically coupled to the top contact pads of substrate plate, (ii) molding material covers the side of vertical connections
Wall, (iii) routing circuit contact and are electrically coupled to the top side of vertical connections.
Electric isolution part, which can provide, connects the platform for setting chip, and the selective vertical connections can provide vertical signal
Conducting path, or ground connection/voltage plane of energy transmission and return is provided.More specifically, the electric isolution part can by thermally conductive and
Electrically insulating material is made, and usually has high elastic coefficient and low thermal coefficient of expansion (for example, 2x 10-6K-1To 10x 10-6K-1)。
Therefore, the thermal expansion coefficient of the electric isolution part can match with the semiconductor element set thereon is connect, to provide semiconductor element
CTE compensating platform, and substantially can compensate or reduce CTE and mismatch caused internal stress.In addition, the electric isolution part also provides
The preliminary heat conduction path of semiconductor element, so that heat caused by semiconductor element can be conducted.
Substrate plate can be used for controlling the accuracy placed when being electrically isolated part, or/and provide for deposited vertical connection
The platform of part.More specifically, which can be metal plate or the single or multi-layer structure with insulating layer, and substrate plate
Inner sidewall can be used as the locating piece put when being electrically isolated part.The inner sidewall of substrate plate can lateral alignment be electrically isolated part four side tables
Face avoids being electrically isolated part generation lateral displacement to define and be electrically isolated the same or similar region of part shape.Therefore, substrate
The inner sidewall of plate can be close to the peripheral edge for being electrically isolated part, to control the storing precision for being electrically isolated part.And/or substrate
Plate can be used for improving the wiring flexibility ratio of route version.For example, the top side of substrate plate can be equipped with top line layer, to provide volume
Outer routing can be electrically connected by the vertical connections being embedded into molding material with the routing circuit on molding material.The routing
The bottom side of circuit can more be equipped with multiple bottom engagement pads, be electrically coupled to top contact pads.Accordingly, which can be in top side
And electrical contact is provided at bottom side.In a preferred embodiment, the bottom engagement pad can be by the bottom of substrate plate bottom side
Line layer provides, and is electrically coupled to top line layer by the metallization perforation in substrate plate.
The molding material can be printed by rubber cement (paste printing), pressing mold forming (compressive molding),
Metaideophone shapes (transfer molding), liquid injection molding (liquid injection molding), rotary coating
(spin coating) or other appropriate methods are formed, to engage with electric isolution part and substrate plate.Preferably, which has
Modulus of elasticity and range greater than 1.0GPa are about 5x10-6K-1To 15x 10-6K-1Thermal linear expansion coefficient, and contact substrate
Molding material thickness range at plate is 0.05 to 1mm.Furthermore for enough heat conductivities and viscosity appropriate, the molding material
It may include the conductive filler material of 10 to 90 weight percent.For example, conductive filler material can be by aluminium nitride (AlN), aluminium oxide, carbonization
Silicon (SiC), tungsten carbide, boron carbide, silica or its analog are made, and preferably have opposite high thermal conductivity degree, relatively high electricity
Resistance rate and the relative low-heat coefficient of expansion.Accordingly, which can show preferable heat dissipation, electrical isolation efficiency, and its low CTE
Characteristic, which can avoid routing circuit or interface, to be occurred removing or crackle.In addition, the maximum particle diameter of conductive filler material can be 25 μm or small
In 25 μm.
Routing circuit on molding material outer surface may be further extended to electric isolution part top surface.Therefore, routing circuit can
Electrical contact is provided in being electrically isolated on part, is electrically isolated on part or routing circuit can be in so that semiconductor element flip connects to be placed in
It is electrically isolated on part and heat conductive pad is provided, be placed in so that semiconductor element connects upward.The routing circuit can pass through photoetching process
Metal deposit forms.Preferably, which is then to carry out electroplating technology by sputter to be formed.
Before or after molding material is provided, it can be electrically connected to the vertical connections of substrate plate.Vertical connections
Citing include, but are not limited to metal column, conducting sphere, closing line, metal filling perforation or combinations thereof.More specifically, described vertical
The top side of connector can contact routing circuit, and bottom side then contacts the top contact pads of substrate plate, and then in routing circuit and base
Electric connection is provided between bottom plate.For example, vertical connections can contact and be electrically coupled in substrate plate the selected of top line layer
Position.Accordingly, the wiring flexibility ratio of wiring board can be improved in the double-deck routing comprising top route and bottom line layer.
To be further routed, which more may include a top build-up circuitry and/or a bottom build-up circuitry, wherein pushing up
Portion's build-up circuitry is located on routing circuit, and bottom build-up circuitry is then located at the lower section for being electrically isolated part bottom surface and substrate plate bottom side.
The top build-up circuitry, which can cover, is electrically isolated part top surface and molding material outer surface, and is electrically coupled to routing circuit, while hot
It is conducted to electric isolution part.The bottom build-up circuitry, which can cover, is electrically isolated part bottom surface and substrate plate bottom side, and is electrically coupled to substrate
The bottom engagement pad of plate, while hot being conducted to electric isolution part.Preferably, top build-up circuitry and bottom build-up circuitry are not have
The multilayer build-up circuitry of core layer respectively includes at least a dielectric layer and conducting wire, and conducting wire fills up the blind hole in dielectric layer, and
It extends laterally on dielectric layer.Dielectric layer can continuously alternate turns be formed with conducting wire, and repeated and formed if needing.Accordingly,
Top build-up circuitry and bottom build-up circuitry can be hot to be conducted to electric isolution part, and difference electric property coupling by metalized blind vias
To routing circuit and substrate plate.In addition, the outermost layer conductor of top build-up circuitry and bottom build-up circuitry can connect set conduction respectively
Contact, such as soldered ball or closing line, with electrically transmission and mechanicalness are connect with a group body, electronic component or other components.
The present invention also provides a kind of semiconductor group body, is to connect semiconductor element (such as chip) to be placed in above-mentioned wiring board
Electric isolution part top surface on, and be electrically coupled to routing circuit.It more specifically, can be by various connection media, by semiconductor
Element is electrically connected to wiring board, wherein connection medium may include conductive bump (such as gold being set on wiring board routing circuit
Convex block or solder projection), or it is connected to the closing line of wiring board routing circuit.When wiring board includes top build-up circuitry,
Semiconductor element can be set in the build-up circuitry of top, while so that semiconductor element alignment is electrically isolated part and being electrically coupled to top
Portion's build-up circuitry.
This group of body can be the first order or second level monocrystalline or polycrystalline device.For example, this group of body can for comprising one chip or
First level encapsulation body of more pieces of chips.Alternatively, this group of body can be the second level module comprising single packaging body or multiple packaging bodies,
Wherein each packaging body may include single one or more pieces of chips.The semiconductor element can be encapsulation chip or unpackaged chip.In addition,
The semiconductor element can be bare chip or wafer-level packaging crystal grain etc..
" covering " word refers to incomplete in vertical and/or side surface direction and is completely covered.For example, bottom increasing layer is electric
Road can cover in lower section and be electrically isolated part, molding material and substrate plate, no matter whether another element (such as bottom coating) is located at bottom
Between build-up circuitry and electric isolution part, between bottom build-up circuitry and molding material and between bottom build-up circuitry and substrate plate.
" connect and be placed in " and " a being connected to " meaning of one's words include with the contact of single or multiple interelement with it is non-contact.For example, partly leading
Volume elements part can connect is placed in be electrically isolated part on, though this semiconductor element whether with the electric isolution part with routing circuit and conductive bump
It is separated by.
" alignment " word means the relative position of interelement, no matter whether keep at a distance or abut each other between element, or
One element is inserted into and extends into another element.For example, when imaginary horizontal line and substrate plate inner sidewall and being electrically isolated outside part
Peripheral edge intersect when, substrate plate inner sidewall, that is, lateral alignment in be electrically isolated part peripheral edge, no matter substrate plate inner sidewall and electricity every
The element whether intersect with imaginary horizontal line with other between off member peripheral edge, and whether have it is another and it is electric every
The intersection of off member peripheral edge but intersect with substrate plate inner sidewall or intersect with substrate plate inner sidewall but not with to be electrically isolated part peripheral
The vertual (virtual) horizontal line of edge intersection.Similarly, in a preferred embodiment, the portion of top build-up circuitry and bottom build-up circuitry
Divide metalized blind vias in alignment with electric isolution part.
" close " word means that the width in the gap of interelement is no more than maximum acceptable range.Such as the existing skill in this field
Art then will can not accurately be electrically isolated part when the gap being electrically isolated between part peripheral edge and substrate plate inner sidewall is not narrow enough
It is limited to predetermined position.The desired order of accuarcy reached when can be set to predetermined position according to part is electrically isolated, to determine to be electrically isolated
The maximum acceptable limit value in gap between part peripheral edge and substrate plate inner sidewall.Therefore, " electric isolution part peripheral edge is close to be run through
The narration of opening inner side wall " and " substrate plate inner sidewall is close to electric isolution part peripheral edge ", which refers to, to be electrically isolated part peripheral edge and passes through
It wears the gap between opening inner side wall and is too narrow to the location error for being enough to prevent to be electrically isolated part more than acceptable worst error limit value.It lifts
For example, it is electrically isolated part peripheral edge and gap between opening inner side wall is reducible in the range of 25 microns to 100 microns.
The word of " electric connection " and " electric property coupling " means directly or indirectly to be electrically connected.For example, the semiconductor element
Routing circuit can be electrically connected to by top build-up circuitry, but semiconductor element and not in contact with routing circuit.
Wiring board of the invention has many advantages.For example, which can provide the platform of compensation CTE, use
Semiconductor element is set to connect, and a sinking path is provided simultaneously, heat dissipation caused by semiconductor element is gone out.The molding material
It can provide mechanical support, and can be used as between routing circuit and substrate plate and be electrically isolated between part and selective vertical connections
Separator.Routing circuit can provide the level electrically routing of wiring board, and the vertical connections of selectivity can provide vertical electricity
Property routing, with another horizontal electrically routing in the routing circuit and substrate plate that are electrically connected on molding material.By the method system
It is standby at wiring board be that reliability is high, cheap and be very suitable to largely manufacture and produce.
Production method of the invention has high applicability, and the various maturations of R. concomitans in a manner of unique, progressive
Electrical property and mechanicalness interconnection technique.In addition, to be not required to expensive tool i.e. implementable for production method of the invention.Therefore, compared to biography
Yield, qualification rate, efficiency and cost-effectiveness can be substantially improved in system technology, this production method.
Embodiment described herein is used to illustrate, and wherein these embodiments may simplify or omit the art
Well known element or step, in order to avoid the fuzzy features of the present invention.Similarly, to keep attached drawing clear, attached drawing may also be omitted and be repeated
Or non-essential element and component symbol.
Claims (22)
1. a kind of wiring board comprising：
One substrate plate runs through opening it includes a top side, a bottom side, positioned at multiple top contact pads of the top sides and one,
In should through opening inner sidewall extend to the bottom side from the top side；
One is electrically isolated part, is set to should running through in opening for the substrate plate, wherein the bottom surface of the electric isolution part and the substrate plate
The bottom side in coplanar, and the thickness of the electric isolution part is greater than the thickness of the substrate plate；
One molding material, covers the top side of the substrate plate, and extend into the peripheral edge of the electric isolution part with should be through opening
A gap between the inner sidewall of mouth, wherein the outer surface of the molding material and the top surface of the electric isolution part are in coplanar；
One routing circuit is set on the outer surface of the molding material；And
Multiple vertical connections are set on the top side of the substrate plate, and are embedded into the molding material, and be electrically coupled to
The top contact pads of the routing circuit and the substrate plate.
2. wiring board as described in claim 1, wherein the routing circuit is more extended laterally in the top surface of the electric isolution part
On.
3. wiring board as described in claim 1, wherein the top contact pads are the selected position of a top line layer, and
The top line layer is located at the top sides of the substrate plate.
4. wiring board as described in claim 1, wherein the substrate plate also includes multiple bottoms contact at the bottom side
Pad is electrically coupled to the top contact pads by the metallization perforation in the substrate plate.
5. wiring board as described in claim 1 further includes a bottom coating, it is located at the bottom surface of the electric isolution part
Place, and the hot conducting in the bottom side with the substrate plate.
6. wiring board as described in claim 1, wherein the electric isolution part is the electric insulation ceramics block for having thermal conductivity.
7. wiring board as described in claim 1, wherein the vertical connections are made of metal, the metal be selected from by Cu,
Group composed by Ti, Ni, Au, Ag, Sn and Sn alloy, and the Sn alloy contains Ag, Cu, Bi or combinations thereof.
8. wiring board as described in claim 1 further includes a top build-up circuitry, is set on the routing circuit, and electricity
Property is coupled to the routing circuit, and hot is conducted to the electric isolution part.
9. wiring board as claimed in claim 4 further includes a bottom build-up circuitry, is set to the bottom surface of the electric isolution part
And the lower section of the bottom side of the substrate plate, and it is electrically coupled to the bottom engagement pad of the substrate plate, and hot be conducted to this
It is electrically isolated part.
10. a kind of semiconductor group body, including：
The wiring board as described in claim 1；And
Semiconductor element is set on the top surface of the electric isolution part, and is electrically coupled to the routing circuit.
11. semiconductor group body as claimed in claim 10, wherein the semiconductor element is electrically coupled to this by closing line
Routing circuit.
12. semiconductor group body as claimed in claim 10, wherein the routing circuit more extends laterally being somebody's turn to do in the electric isolution part
On top surface, and the semiconductor element is electrically coupled to the routing circuit by conductive bump.
13. semiconductor group body as claimed in claim 10, wherein the substrate plate also includes to connect positioned at multiple bottoms of the bottom side
Touch pad is electrically coupled to the top contact pads.
14. semiconductor group body as claimed in claim 10, wherein the wiring board further includes a top build-up circuitry, setting
In on the routing circuit, and be electrically coupled to the routing circuit, and it is hot be conducted to the electric isolution part, and the semiconductor element is set
It is placed in the top build-up circuitry, and by the top build-up circuitry, is electrically coupled to the routing circuit.
15. semiconductor group body as claimed in claim 13, wherein the wiring board further includes a bottom build-up circuitry, setting
In the lower section of the bottom side of bottom surface and substrate plate of the electric isolution part, and the bottom for being electrically coupled to the substrate plate connects
Touch pad, and hot it is conducted to the electric isolution part.
16. a kind of equipped with the method for manufacturing circuit board for being electrically isolated part comprising following step：
One substrate plate is provided, it includes a top side, a bottom side and one through opening, wherein should through opening inner sidewall from the top
Side extends to the bottom side；
By one electric isolution part be inserted into the substrate plate should through opening, and the electric isolution part peripheral edge close to should through opening
The inner sidewall, and the bottom side of the bottom surface of the electric isolution part and the substrate plate is in coplanar, wherein the thickness of the electric isolution part
Degree is greater than the thickness of the substrate plate；
A molding material is provided on the top side of the substrate plate, and the molding material extends into the periphery sides of the electric isolution part
Edge and the gap being somebody's turn to do between the inner sidewall of opening, wherein the outer surface of the molding material and the top surface of the electric isolution part are in
It is coplanar；And
A routing circuit is formed on the outer surface of the molding material.
17. production method as claimed in claim 16 further includes a step：Multiple vertical connections are formed in the substrate plate
On the top side, wherein the substrate plate also includes multiple top contact pads positioned at the top sides, and the vertical connections are electrical
It is coupled to the routing circuit and the top contact pads of the substrate plate.
18. production method as claimed in claim 16, wherein the routing circuit is more extended laterally in the top of the electric isolution part
On face.
19. production method as claimed in claim 17, wherein the substrate plate also includes that multiple bottoms at the bottom side connect
Touch pad is electrically coupled to the top contact pads.
20. production method as claimed in claim 16, wherein forming the routing circuit in the step on the molding material includes
One sputtering process.
21. production method as claimed in claim 16 further includes a step：A top build-up circuitry is formed in the routing circuit
On, wherein the top build-up circuitry is electrically coupled to the routing circuit, and hot is conducted to the electric isolution part.
22. production method as claimed in claim 19 further includes a step：A bottom build-up circuitry is formed in the electric isolution part
The bottom surface and the substrate plate the bottom side lower section, wherein the bottom build-up circuitry is electrically coupled to the bottom of the substrate plate
Portion's engagement pad, and hot it is conducted to the electric isolution part.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US15/605,920 | 2017-05-25 | ||
| US15/605,920 US20170263546A1 (en) | 2014-03-07 | 2017-05-25 | Wiring board with electrical isolator and base board incorporated therein and semiconductor assembly and manufacturing method thereof |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN108933113A true CN108933113A (en) | 2018-12-04 |
Family
ID=64448981
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN201810293055.4A Pending CN108933113A (en) | 2017-05-25 | 2018-03-30 | Equipped with wiring board, its semiconductor group body and its preparation method for being electrically isolated part and substrate plate |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN108933113A (en) |
| TW (1) | TWI657546B (en) |
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| CN113675173A (en) * | 2020-05-13 | 2021-11-19 | 南亚科技股份有限公司 | Semiconductor package |
| CN114171663A (en) * | 2021-12-07 | 2022-03-11 | 丰鹏电子(珠海)有限公司 | Heat dissipation substrate and preparation method thereof |
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| US11166363B2 (en) * | 2019-01-11 | 2021-11-02 | Tactotek Oy | Electrical node, method for manufacturing electrical node and multilayer structure comprising electrical node |
| TWI795696B (en) * | 2020-12-04 | 2023-03-11 | 吳聲欣 | Semiconductor device package structure and manufacturing method thereof |
| TWI792356B (en) * | 2021-06-17 | 2023-02-11 | 大陸商慶鼎精密電子（淮安）有限公司 | Circuit board assembly and method for manufacturing the same |
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| US20150257316A1 (en) * | 2014-03-07 | 2015-09-10 | Bridge Semiconductor Corporation | Method of making thermally enhanced wiring board having isolator incorporated therein |
| TWI599003B (en) * | 2015-09-07 | 2017-09-11 | 鈺橋半導體股份有限公司 | Thermally enhanced wiring board having metal slug and moisture inhibiting cap incorporated therein and method of making the same |
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- 2018-03-30 CN CN201810293055.4A patent/CN108933113A/en active Pending
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| US20100001395A1 (en) * | 2008-03-25 | 2010-01-07 | Bridge Semiconductor Corporation | Semiconductor chip assembly with post/base heat spreader and vertical signal routing |
| CN103841750A (en) * | 2012-11-23 | 2014-06-04 | 旭德科技股份有限公司 | Package carrier |
| CN104039070A (en) * | 2013-03-07 | 2014-09-10 | 钰桥半导体股份有限公司 | Thermally enhanced wiring board with built-in heat sink and build-up circuitry |
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| CN113675173A (en) * | 2020-05-13 | 2021-11-19 | 南亚科技股份有限公司 | Semiconductor package |
| CN114171663A (en) * | 2021-12-07 | 2022-03-11 | 丰鹏电子(珠海)有限公司 | Heat dissipation substrate and preparation method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| TW201901871A (en) | 2019-01-01 |
| TWI657546B (en) | 2019-04-21 |
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