CN108932966A

CN108932966A - Semiconductor device and data processing system

Info

Publication number: CN108932966A
Application number: CN201810430859.4A
Authority: CN
Inventors: 广部厚纪
Original assignee: Renesas Electronics Corp
Current assignee: Renesas Electronics Corp
Priority date: 2017-05-24
Filing date: 2018-05-08
Publication date: 2018-12-04
Anticipated expiration: 2038-05-08
Also published as: JP2018198017A; EP3467664B1; EP3467664A1; CN108932966B; US11126373B2; KR20180128847A; JP6815277B2; TW201901452A; US20180341431A1; TWI771416B

Abstract

The present invention relates to semiconductor device and data processing system, a kind of technology of management that can promote to include data in the memory device in the semiconductor device of memory device and data processing equipment is provided.The semiconductor device includes the first external terminal, the second external terminal, data processing equipment and memory device.The semiconductor device further includes：First bus is coupled between the data processing equipment and the memory device；Second bus is coupled between the data processing equipment and second external terminal；Third bus is coupled to first external terminal；And control circuit, it is coupled to first bus and the third bus.The control circuit has the management function using the third bus to the memory device.

Description

Semiconductor device and data processing system

Cross reference to related applications

The Japanese patent application No.2017- submitted on May 24th, 2017 including specification, drawings and abstract 103138 disclosure is incorporated herein by reference with entire content.

Background technique

The disclosure can be suitable for the semiconductor device including memory device and data processing equipment, and use and partly lead The data processing system of body device.

It is developing to use and is using through silicon via in semiconductor packages identical with the semiconductor packages of data processing equipment (TSV) 2.5 dimension mounting techniques of the memory that technology sealing stacks and 3 dimension mounting techniques.

For example, SK hynix Inc., Joonyoung Kim and YounsuKim, HBM:Memory Solution for Bandwidth-Hungry Processors, in August, 2014, internet<URL:https://ja.scribd.com/ document/258652867/HC26-11-310-HBM-Bandwidt h-Kim-Hynix-Hot-Chips-HBM-2014-v7 >Retrieve the date:Disclose host IF, memory I/F and basic logic/IP wherein within 20 days 2 months (non-patent literature 1) 2017 Block is provided to the configuration of the substrate of the stacked memory of 2.5 dimension mounting techniques.Further, non-patent literature 1 discloses Wherein the region DFT, TSV region and PHY (interface with Soc) are provided to substrate.

Summary of the invention

The target of the disclosure, which is to provide, a kind of can promote to include that the semiconductor of memory device and data processing equipment fills The technology of the management for the data in memory device set.

Other targets and novel feature will become apparent from the description of the specification and drawings.

The general introduction of the typical invention among the invention disclosed in the disclosure is explained briefly below.

Semiconductor device includes the first external terminal, the second external terminal, data processing equipment and memory device.Partly lead Body device further includes：First bus, is coupled between data processing equipment and memory device；Second bus, is coupled in Between data processing equipment and the second external terminal；Third bus is coupled to the first external terminal；And control circuit, It is coupled to the first bus and third bus.Control circuit has the management function using third bus to memory device.

According to semiconductor device as described above, it is possible for promoting the management of the data in memory.

Detailed description of the invention

Fig. 1 is the conceptual cross-sectional view of semiconductor device according to first embodiment.

Fig. 2 is the enlarged drawing of the semiconductor device of Fig. 1.

Fig. 3 is the conceptual block diagram of semiconductor device according to first embodiment.

Fig. 4 is the conceptual block diagram according to the semiconductor device of comparative example.

Fig. 5 is the conceptual composition figure of data processing system according to first embodiment.

Fig. 6 is the block diagram of memory device according to first embodiment.

Fig. 7 is according to first embodiment for conceptually explaining the diagram of the operation of control circuit.

Fig. 8 is the exemplary diagram for showing the format of control signal C1 and C2.

Fig. 9 is another exemplary diagram for showing the format of control signal C1 and C2.

Figure 10 is the diagram for showing the modification 1 of the memory device of Fig. 7.

Figure 11 is the diagram for showing the modification 2 of the memory device of Fig. 7.

Figure 12 is the diagram for showing another allocation example of channel distribution of Figure 11.

Figure 13 is the diagram for showing the modification 3 of the memory device of Fig. 7.

Figure 14 is the diagram of the modification 1 for the data processing system for showing Fig. 5.

Figure 15 is the conceptual block diagram of semiconductor device according to the second embodiment.

Figure 16 is the composition figure according to the data processing system of the semiconductor device of Figure 15.

Figure 17 is the composition figure according to another data processing system of the semiconductor device of Figure 15.

Figure 18 is the block diagram of the modification of semiconductor device according to the third embodiment.

Figure 19 is the composition figure according to the data processing system of the semiconductor device of Figure 18.

Figure 20 is the composition figure according to another data processing system of the semiconductor device of Figure 18.

Figure 21 is the composition figure according to the data processing system of fourth embodiment.

Figure 22 is the diagram for showing the configuration example of the semiconductor device according to modification 1.

Figure 23 is the diagram for showing the configuration example of the semiconductor device according to modification 2.

Figure 24 is the diagram for showing the configuration example of the data processing system according to modification 2.

Figure 25 is the diagram for showing the configuration example of the data processing system according to modification 3.

Figure 26 is the diagram for showing the configuration example of the semiconductor device according to modification 4.

Specific embodiment

Hereinafter, embodiment, comparative example and modification will be described with reference to the drawings.However, in the following description, identical portions Part is indicated by same reference numerals and its repeated description can be omitted.Compared with actual form, attached drawing can be about every Width, thickness, shape of a component etc. schematically show more acurrate to make to describe.However, attached drawing is only example and not Limit explanation of the invention.

[first embodiment]

Fig. 1 is the conceptual cross-sectional view of semiconductor device according to first embodiment.Fig. 2 shows the semiconductor of Fig. 1 dresses The enlarged drawing of a part set.

Semiconductor device 1 has memory device 2 and data processing equipment (MPU (NPU)) 3, and is configured as one Semiconductor packages.Memory device 2 includes base chip (substrate) 21 and semiconductor memory (multiple semiconductor memory cores Piece) 22, it is stacked in base chip 21.Base chip 21 and multiple semiconductor memory chips 22 are by using TSV (to pass through The Si of electrode：Through silicon via) and the coupled structure 23 of metal electrode (dimpling block) of such as scolding tin couple.21 sum number of base chip It is coupled to the first substrate 4 such as silicon intermediary layer for example, by the metal electrode (dimpling block) of such as scolding tin according to processing unit 3.First Substrate 4 is coupled to the second substrate 5 for example, by the metal electrode (dimpling block) of such as scolding tin, is used as the circuit lining of encapsulation Bottom.Second substrate 5 is provided with multiple ball electrodes (external terminal) 6, is made of the metal electrode of such as scolding tin.Second substrate 5 are provided with such as lid 7, by overlaying memory device 2 and data processing equipment 3 so as to sealed storage device device 2 and data Metal of processing unit 3 or the like formation.MPU (NCU) is microprocessor (microprocessor unit) or network processing unit (net Network processing unit).

The ball electrode (external terminal) 6 for being provided to the second substrate 5 has multiple first external terminals 61 and multiple second External terminal 62.Multiple first external electrodes 61 pass through the wired coupling in the first substrate 4 and the second substrate 5 and dimpling block to base The second interface unit IF2 of plinth chip 21.Second external terminal 62 passes through in the first substrate 4 and the second substrate 5 and dimpling block Wired coupling is to data processing equipment 3.As described later, the second external terminal 62 is provided total to be coupled to the first system Line SBUS1, and the first external terminal 61 is provided to be coupled to second system bus SBUS2, is secondary bus or expansion Open up bus.

Base chip 21 is also with the first interface unit IF1 of data processing equipment 3.First interface unit IF1 passes through the Wired coupling in one substrate 4 and dimpling block is to data processing equipment 3.

As shown in FIG. 2, semiconductor device 1 is provided with：First bus (the first signal path) 31, is provided at Between first interface unit IF1 and data processing equipment 3；Second bus (second signal path) 32, is provided at data It manages between device 3 and the second external terminal 62；And third bus (third signal path) 33, it is provided at second interface list Between first IF2 and the first external terminal 61.In Fig. 2, draws be directed to the first bus 31, the second bus 32 and third bus respectively Arrow shown in 33 promotes to understand illustratively to indicate bus 31,32 and 33.

Coupling wiring between first interface unit IF1 and data processing equipment 3 is illustratively shown as by Fig. 1 and Fig. 2 Two or three coupling wirings.Further, Fig. 1 and Fig. 2 is illustratively by second interface unit IF2 and the second external terminal 62 Between coupling wiring be shown as two wiring.The number of coupling wiring between first interface unit IF1 and data processing equipment 3 Amount is assumed it is such as about 1000.The quantity of coupling wiring between second interface unit IF2 and the second external terminal 62 It is assumed such as 80 to 100.In other words, the quantity of the wiring of the first bus 31 is greater than the number of the wiring of third bus 33 Amount, and the quantity of the wiring of the second bus 32 is greater than the quantity of the wiring of third bus 33.

In fig. 1 and 2, memory chip 22 can be such as SDR (single data rate) type DRAM (dynamic random deposited Access to memory) or DDR (double data rate) type DRAM.Although showing four memory chips 22 in this example, It is that the quantity of memory chip can be one or four or more memory chips and can be stacked.It can be used only A type of memory chip, or a plurality of types of memory chips can be combined.A plurality of types of memory chips can To be selected from DRAM (dynamic random access memory), static types RAM (random access memory), nonvolatile memory etc.. Nonvolatile memory can be selected from ROM (read-only memory), flash memory etc..Data processing equipment 3 can be micro process Device (MPU), network processing unit (NPU), graphics processor (GPU) etc..

Fig. 3 is the conceptual block diagram of semiconductor device according to first embodiment.Fig. 4 is filled according to the semiconductor of comparative example The conceptual block diagram set.

As shown in FIG. 3, semiconductor device 1 has memory device 2, data processing equipment 3 and control circuit CNT. Although not particularly restricted, data processing equipment 3 includes central processing unit or graphics processor (CPU/GPU) and high speed Buffer memory (L1, L2 and L3/LLC).In this example, cache memory includes (1 grade of primary cache memory Cache) (L1), secondary cache memory (2 grades of caches) (L2) and three-level cache memory (3 grades of high speeds Caching or last level cache) (L3/LLC).

Semiconductor device 1 has：First bus (the first signal path, memory bus) 31, is provided at memory Between device 2 and data processing equipment 3；Second bus (second signal path) 32 is provided at data processing equipment 3 and Between two external terminals 62；And third bus (third signal path) 33, it is provided at outside control circuit CNT and first Between terminal 61.Control circuit CNT is coupled to the first bus 31 and is additionally coupled to the 4th bus (fourth signal path) 34, It is provided between control circuit CNT and data processing equipment 3.The details of control circuit CNT will be described later.

The first bus 31 is provided to make data processing equipment 3 read data from memory device 2 and write data into Memory device 2.The second bus 32 is provided to read and write number between 1 outside of data processing equipment 3 and semiconductor device According to.Third bus 33 is provided so that data and the first control are transmitted and received between 1 outside control circuit CNT and semiconductor device Information (control signal).The 4th bus 34 is provided so that second is transmitted and received between data processing equipment 3 and control circuit CNT Control information (control signal).

By configuring as described above, there are two access path for the tool of memory device 2 shown in Fig. 3, are：The One access path, wherein data processing equipment 3 is read and write by the execution of the first bus 31；And second access path, In read and write and executed by using third bus 33, control circuit CNT with the first bus 31.Therefore, except by using Except first access path is to the management of the memory content in memory device 2, memory device 2 can shown in Fig. 3 Management to the storage content in memory device 2 is executed by using the second access path.

Fig. 4 is the conceptual block diagram according to the semiconductor device of comparative example.Portion about the semiconductor device 100 in Fig. 4 The component of semiconductor device 1 in part and Fig. 3 is indicated corresponding to mutual component by same reference numeral.Semiconductor in Fig. 4 The point different from the semiconductor device 1 in Fig. 3 of device 100 is that the semiconductor device 100 in Fig. 4 is not provided with control circuit CNT, third bus 33 and the 4th bus 34.Although memory device 2 in semiconductor device 1 has as described above the One access path and the second access path, but the memory device 2 in semiconductor device 100 has only the first access path. Therefore, for the storage content in the memory device 2 in managing semiconductor device 100, there is no remove to pass through semiconductor device Data processing equipment 3 in 100 uses the other way of the first access path.

Fig. 5 is the conceptual composition figure of data processing system according to first embodiment.Fig. 5 is shown partly to be led including multiple Body device 1_1,1_2 ... and the data processing system of 1_n.Semiconductor device 1_1,1_2 ... and each of 1_n is partly led Body device corresponds to the semiconductor device 1 in Fig. 3.In Fig. 5, component in semiconductor device 1 shown in Fig. 3 (X=2,3, 31,32,33,34,61,62 and CNT) by using correspond to semiconductor device 1_1,1_2 ... and 1_n reference symbol it is all As X_1, X_2 ... and X_n indicate so that the corresponding relationship between component and semiconductor device is shown.However, about One interface unit IF1 and second interface unit IF2, semiconductor device 1_1,1_2 ... and in 1_n each semiconductor dress It sets middle using same reference numeral.

Semiconductor device 1_1,1_2 ... and 1_n second bus 32_1,32_2 ... and 32_n is separately by the Two external terminal 62_1,62_2 ... and 62_n is coupled to the first system bus SBUS1.Semiconductor device 1_1,1_2 ... With third bus 33_1,33_2 of 1_n ... and 33_n separately by first external terminal 61_1,61_2 ... and 61_n The new second system bus SBUS2 provided or add is provided.Second system bus SUBS2 mainly be used to manage half Conductor device 1_1,1_2 ... and memory device 2_1,2_2 provided in 1_n ... and the storage content of 2_n.First Each of system bus SBUS1 and second system bus SBUS2 and system storage SMEM1, SMEM2 ... and SMEMn Coupling.For system storage SMEM1, SMEM2 ... and each system storage in SMEMn shows tool there are two defeated Enter/the example of the two-port memory of output port.As shown in FIG. 5, system storage SMEM1, SMEM2 ... and In each system storage in SMEMn, a port is coupled to the first system bus SBUS1 and another port is coupled to Two system bus SBUS2.Though it is shown that wherein providing the example of multiple system storages, but in this example, system The quantity of memory can be one.

For example, second system bus SBUS2 can be used it is as follows：

(1)：Single write-in 1：The content of the memory device 2_1 of semiconductor device 1_1 can be by using second system Bus SBUS2 is copied to the memory device 2_2 of semiconductor device 1_2.

(2)：Multiple write-ins 1：The content of the memory device 2_1 of semiconductor device 1_1 can be by using second system Bus SBUS2 is copied to the memory device 2_n of the memory device 2_2 and semiconductor device 1_n of semiconductor device 1_2.

(3) 2 are individually written：The content of the memory device 2_1 of semiconductor device 1_1 can be total by using second system Line SBUS2 is copied to system storage (SMEM1, SMEM2 ... or SMEMn).

(4) multiple write-ins 2：The content of the memory device 2_1 of semiconductor device 1_1 can be total by using second system Line SBUS2 be copied to semiconductor device 1_2 memory device 2_2 and system storage (SMEM1, SMEM2 ... or SMEMn)。

(5) 3 are individually written：The content of system storage (SMEM1, SMEM2 ... or SMEMn) can be by using Second system bus SBUS2 is copied to the memory device 2_1 of semiconductor device 1_1.

(6) multiple write-ins 3：The content of system storage (SMEM1, SMEM2 ... or SMEMn) can be by using Second system bus SBUS2 is copied to the memory of the memory device 2_1 and semiconductor device 1_2 of semiconductor device 1_1 Device 2_2.

By configuration as described above, by using second system bus SBUS2 without the use of the first system bus SBUS1 management system memory SMEM1, SMEM2 ... and SMEMn content and semiconductor device 1_1,1_2 ... and 1_n In memory device 2_1,2_2 ... and the content of 2_n is possible.In other words, it is filled by data processing not limiting Set 3_1,3_2 ... and 3_n using second bus 33_1,33_2 ... and the case where 33_n and the first system bus SBUS1 Under, by using third bus 33_1,33_2 ... and 33_n and second system bus SBUS2 management system memory SMEM1, SMEM2 ... and SMEMn content and semiconductor device 1_1,1_2 ... and memory device 2_1 in 1_n, 2_2 ... and the content of 2_n is possible.

By using second bus 32_1,32_2 ... and 32_n and the first system bus SBUS1 set and third it is total Line 33_1,33_2 ... and both set of 33_n and second system bus SBUS2 management system memory SMEM1, SMEM2 ... and SMEMn content and semiconductor device 1_1,1_2 ... and memory device 2_1,2_ in 1_n 2 ... and the content of 2_n is also possible.

Fig. 6 shows the block diagram of memory device according to first embodiment.Fig. 6 shows the dress of the semiconductor including Fig. 3 Set the example of the block diagram of the memory device 2 of 1 control circuit CNT.Memory device 3 has base chip 21 and multiple stackings Memory chip 22 (221,222,223 and 224).Control circuit CNT is provided in base chip 21.Base chip 21 with First bus 31, third bus 33 and the coupling of the 4th bus 34.

First bus 31 has：First data/address bus 31D supplies data by it；And the first control bus 31CA, lead to Cross its provision commands (CMD), address (ADD) etc..As shown in Fig. 3 or Fig. 5, the first bus 31 is coupled to identical semiconductor dress Set the data processing equipment 3 (3_1) in 1 (1_1).

Third bus 33 has：First data/address bus 33D supplies data by it；And third control bus 33CA, lead to Cross the control signal C1 that its supply includes order (CMD), address (ADD) etc..As shown in FIG. 5, when data system is configured When, third bus 33 is coupled to second system bus SBUS2.Second system bus SBUS2 be coupled to for example with semiconductor device 1 The control circuit (CNT_2, CNT_n) of (1_1) different other semiconductor devices (1_2,1_n).Fig. 6 is illustratively shown difference Semiconductor device (1_2) in control circuit (CNT_2) as third bus 33 coupling destination to avoid attached drawing Complexity.In other words, the control circuit (CNT_2) in different semiconductor device (1_2) is shown as reference symbol CNT_2 (1_2)。

It includes ordering the bus for controlling signal C2 of (CMD), address (ADD) etc. that 4th bus 34, which is by its supply,.Such as Shown in Fig. 3 or Fig. 5, the 4th bus 34 is coupled to the data processing equipment 3 (3_1) in identical semiconductor device 1 (1_1).

Base chip 21 includes control circuit CNT and test circuit TEST.Control circuit CNT further includes：First control electricity Road CNT1 is coupled to the first control bus 31CA；Second control circuit CNT2 is coupled to third control bus 33CA and Four buses 34；And selection circuit SEL1.

First control circuit CNT1 is supplied with order (CMD) from the first control bus 31CA, address (ADD) etc., The a part of address (ADD) is decoded, and generates channel selecting signal.First control circuit CNT1 passes through control bus 31CA1 by the remainder for ordering (CMD), channel selecting signal and address (ADD) be supplied to multiple memory chips 22 (221, 222,223 and 224).In other words, first control circuit CNT1 has the function of Memory Controller and has multiple storages The channel selecting function in the input/output channel of device chip 22 (221,222,223 and 224).For example, four memory chips 221, each memory chip tool in 222,223 and 224 is stored there are four channel as input/output channel, and entirely Device device 2 has 16 channels.In this case, first control circuit CNT1 is formed according to order (CMD) and address (ADD) Channel for the one or more input/output channels for being used to read data according to order (CMD) selection or data being written Selection signal, and channel selecting signal is output to control bus 31CA1 together with order (CMD) and address (ADD).The Four memory chip 221,222,223 and 224 according to received from control bus 31CA1 channel selecting signal, order (CMD) With address (ADD), enter selected state using to read data or multiple input/output channels of data are written.When Order (CMD) is when reading data, from the memory list corresponding to the address (ADD) by the selected channel of channel selecting signal The data that member is read are supplied to data processing equipment 3 (3-1) by data/address bus 31D.When order (CMD) is write-in data When, the data for being output to data/address bus 31D from data processing equipment 3 (3-1), which are written to, to be corresponded to by channel selecting signal The memory cell of the address (ADD) in selected channel.Ordering (CMD) includes refresh command.

First control circuit CNT1 also has the use state (read, write-in or refresh) in output and channel related the The function of one channel information CH1.First control circuit CNT1 also have input with from second control circuit CNT2 export channel The related second channel information CH2 of solicited message and identical mode is believed according to second channel in the manner as described above Cease the function of CH2 output channel selection signal.

Second control circuit CNT2 receives the control signal C1 supplied from the 4th bus 34, from third control bus 33CA The control signal C2 and channel information CH from first control circuit CNT1 supplied.Second control circuit CNT2 is according to control Signal C1, control signal C2 and channel information CH processed generate command/address CAd and selection signal S1.Command/address CAd is defeated First control circuit CNT1 is arrived out.On the other hand, selection signal S1 is output to selection circuit SEL1.Selection circuit SEL1 according to Selection signal S1 controls the coupling between the first data/address bus 31D and third data/address bus 33D.For example it is assumed that wherein partly leading Data processing equipment 3 (3_1) in body device 1 (1-1) is controlled in the case where reading data or write-in data using channel 1 to 14 The case where signal C1 processed or control signal C2 request are using such as channel 14 to 16.In this case, channel 1 to 14 is busy Commonplace channel, and just used from channel 1 to 14 known to channel information CH1 by data processing equipment 3 (3_1).Therefore, the second control Circuit CNT2 generates selection signal S1 and control selections circuit SEL1 to select being not used in addition to competing channel 14 to lead to The data line in one or more of road 15 and 16.In other words, second control circuit CNT2 has the function of channel arbitration circuit Energy.Therefore, corresponding to the data line in the selected channel in the unused channel 15 and 16 in the first data/address bus 31D and Data line in three data/address bus 33D is selectively coupled according to selection signal S1 by selection circuit SEL1.Further, second Control circuit CNT2 generates channel request information related with channel 15 and 16 and leads to as second channel information CH2 and by second Road information CH2 is output to first control circuit CNT1 to select unused channel 15 and 16.To first control circuit CNT1 According to from second control circuit CNT2 second channel information CH2 and command/address CAd will correspond to channel 15 and 16 and life Order/address CAd channel selecting signal is output to control bus 31CA1.

To, according to control signal C1 and control signal C2 execute memory device 2 channel selection operation and to institute The read operation of the write operation of the data in the channel of selection and the data from selected channel is possible.

As control signal C1 and control signal C2 is substantially simultaneously entered and the use of same channels is by control signal When C1 and control signal C2 are requested, it is preferred that by using the function of the operating system (OS) of data processing equipment 3 (3_1) Determination is that control signal C1 is prioritized or controls the priority orders that signal C2 is prioritized.

In Fig. 6, test circuit TEST instruction is provided the memory BIST to test or check memory device 22 (Built-in Self Test).Test circuit TEST can be coupled between the first bus 31 and third bus 33 (the first external terminal). In order to avoid the complexity of attached drawing, Fig. 6 is illustratively shown the first data/address bus 31D and the only for test circuit TEST Coupling between three data/address bus 33D.In Fig. 6, although not particularly restricted, cache memory and computing circuit energy It is enough provided in third data/address bus 33D as circuit block CB.

Fig. 7 is according to first embodiment for conceptually explaining the diagram of the operation of control circuit.In Fig. 7, storage Device chip 22 includes channel 1 to 16, and describes channel 1 to 16 by selection circuit SEL1, first control circuit CNT1 and the Two control circuit CNT2 selection.In Fig. 7, the left side is shown in the identical semiconductor device 1 (1_1) about Fig. 3 or Fig. 5 The coupled relation of data processing equipment 3 (3_1), and the right is shown about different from semiconductor device 1 (1_1) other half The coupled relation of control circuit (CNT_2, CNT_n) in conductor device (1_2,1_n).In order to avoid complexity, Fig. 7 is illustrative Control circuit CNT_2 in semiconductor device 1_2 is shown as reference symbol CNT_2 (1_2) by ground.In the following description, it partly leads Data processing equipment 3 (3_1) in body device 1 (1-1) is defined as main side, and is coupled in semiconductor device (1_2) The data processing equipment 3_2 of control circuit (CNT_2) is defined as from side.

As shown in Figure 6 as described in, first control circuit CNT1 is according to command/address CAd and channel information CH2 by channel Selection signal is output to third control bus 33CA1.To one or more channels in selector channel 1 to 16.Selection circuit SEL1 is not used by the selection signal S1 from second control circuit CNT2 by main side data processing equipment 3 (3_1) selection logical The operation of third bus 33D is coupled in road and execution.On the other hand, selection circuit SEL2 is provided to schematically show The selection in the one or more channels used by main side data processing equipment 3 (3_1) in order to understanding configuration and pass through the One data/address bus 31D is coupled to data processing equipment 3 (3_1).

Second control circuit CNT2 is coupled in the semiconductor device 1 (1-1) of Fig. 3 or Fig. 5 by the 4th bus 34 Main side data processing equipment 3 (3_1).Second control circuit CNT2 is additionally coupled to third control bus 33CA.Such as the institute in Fig. 5 Show, third control bus 33CA is coupled to the control circuit in different semiconductor device 1-2 by second system bus SBUS2 CNT_2 and from side data processing unit 3_2.

Hereinafter, description is used for the example of the input/output control signal of second control circuit CNT2.

Main side system calling (main system calling) is transmitted to main side number by the 4th bus 34 by second control circuit CNT2 Main side system calling (main system calling) is received according to processing unit 3 (3_1) and from main side data processing equipment 3 (3_1).Second Control circuit CNT_2 will be called (from system tune by third control bus 33CA and second system bus SBUS2 from side system With) the control circuit CNT2 that is transmitted to from the semiconductor device 1_2 of side or data processing equipment 3_2 and from from side semiconductor Control circuit CNT2 or data processing equipment 3_2 in device 1_2, which are received, to be called and (calls from system) from side system.

It includes main side request ReqM1 and main side response ResM1 that main side system, which calls (main system calling), is main side request The response signal of ReqM1.Calling and (call from system) from side system includes requesting ReqS1 from side and responding ResS1 from side, is From the response signal of side request ReqS1.

It includes such as transfer destination address information, transmission source address information, memory control letter that ReqM1 is requested in main side Breath, busy channel information and access block message.It includes for example requesting source address information, busy channel information that main side, which responds ResM1, With access block message.From side, request ReqS1 includes such as transfer destination address information, transmission source address information, memory control Information, busy channel information and access block message processed.From side, response ResS1 includes for example requesting source address information, busy channel Information, access block message etc..

Second control circuit CNT2 receives main side request ReqM1 from main side data processing equipment 3 (3_1) and rings main side ResM1 is answered to be transmitted to response of the main side data processing equipment 3 (3_1) as main side request ReqM1.To second control circuit CNT2 will control signal C1 and be output to third control bus 33CA or control signal C2 is output to the 4th bus 34.Control letter Number C1 is supplied to the control circuit CNT_2 from the semiconductor device 1_2 of side by second system bus SBUS2, and stores Device device 2_2 and desired system storage (SMEM1, SMEM2 ... and/or SMEMn) accessed.On the other hand, control letter Number C2 is supplied to the first system bus SBUS1 from main side data processing equipment 3 (3_1) by the second bus 32_1, and deposits Reservoir device 2_2 by from the semiconductor device 1_2 of side data processing equipment 3_2 access or desired system storage (SMEM1, SMEM2 ... and/or SMEMn) accessed.

Second control circuit CNT2 is received from from the control circuit CNT2 in the semiconductor device 1_2 of side from side request ReqS1 And ReqS1 is requested using the control circuit CNT2 from the semiconductor device 1_2 of side is transmitted to as to from side from side response ResS1 Response.To, identical mode in the manner as described above, the control circuit CNT_2 in semiconductor device 1_2 will be controlled The third control bus 33CA or control signal C2 is output to semiconductor dress that signal C1 processed is output in semiconductor device 1_2 Set the 4th bus 34 in 1_2.

Control signal C1 is supplied to the control circuit in the semiconductor device 1-1 of main side by second system bus SBUS2 CNT_1, and memory device 2_1 and desired system storage (SMEM1, SMEM2 ... and/or SMEMn) accessed. It controls signal C2 and the first system bus SBUS1 is supplied to from from side data processing unit 3_2 by the second bus 32_2, and Memory device 2_1 is accessed by the data processing equipment 3_1 in the semiconductor device 1_1 of main side or desired system storage (SMEM1, SMEM2 ... and/or SMEMn) accessed.The function of operating system (OS) depending on data processing equipment 3_1 And determine whether that using only controlling signal C1, only controlling both signal C2 or control signal C1 and C2 be possible.

Fig. 8 is the exemplary diagram for showing the format of control signal C1 and C2.Controlling signal C1 and C2 includes memory mark Remember field MTAG, memory function control field MCONT and data area field DAREA.

Memory tag field MTAG includes transfer destination memory specifications field DSMEM and transfer source memory specifications Field SOMEM.In transfer destination memory specifications field DSMEM, will from memory device (2_1,2_2 ..., 2_n, SMEM1, SMEM2 ... and SMEMn) to be appointed as transfer destination be possible for one or more memory devices of selection.? In transfer source memory specifications field SOMEM, will from memory device (2_1,2_2 ..., 2_n, SMEM1, SMEM2 ... And SMEMn) to be appointed as transfer source be possible for a memory device of selection.However, in transfer destination memory specifications In field DSMEM specify one or more memory devices with selected in transfer source memory specifications field SOMEM One memory device difference, and do not allow overlay specification.

Memory function control field MCONT includes memory command field MCMD, busy channel information attribute field BUSYFLAG and address field Add.In memory command field MCMD, for transfer destination memory specifications field In DSMEM specify one or more memory devices (2_1,2_2 ... 2_n, SMEM1, SMEM2 ... and/or SMEMn) Specified reading order or writing commands are possible.It is specified currently to make in busy channel information attribute field BUSYFLAG The sequence number in channel is possible.In address field Add, in transfer destination memory specifications field DSMEM In specify one or more memory devices (2_1,2_2 ... 2_n, SMEM1, SMEM2 ... and/or SMEMn) in It is possible that each memory device, which specifies transfer destination address range,.The range of transfer destination storage address can be by It is specified using the range of row address (x1, x2) and column address (y1, y2) such as (x1, y1)-(x2, y2).According to memory Command field MCMD and address field Add generates described command/address CAd in figure 6 and figure 7.

In the field DAREA of data area, the transfer source specified in transfer source memory specifications field SOMEM is specified to deposit The range of transfer source storage address (Access mBloc) in reservoir device is possible.The model of transfer source storage address Enclosing can be by using the range of row address (x1, x2) and column address (y1, y2) such as (x1, y1)-(x2, y2) specified.

Therefore, memory management is executed as control signal C1 as described below by the specified for example above format The operation of (duplication or consistent management) is possible.

1 (memory device 2_1- is individually written in canonical example (1)>Memory device 2_2)：

Memory device 2_2 is specified in transfer destination memory specifications field DSMEM, and memory device 2_1 is being passed It send in source memory normative field SOMEM and specifies, and writing commands are specified in memory command field MCMD.Further Ground, desired address range are specified in data area field DAREA and address field Add.In this case, in memory The data for the address range specified in the data area field DAREA of device 2_1 pass through third data/address bus 33D and second system It control circuit CNT2 that bus SBUS2 is supplied in memory device 2_2 and is written into and (is replicated) in address field The address range of the memory device 2_2 specified in Add.In this case, it is known that transfer source memory specifications field SOMEM It is the memory device 2_1 of main side semiconductor device 1_1, so that omitting the specification of transfer source memory specifications field SOMEM is It is possible.

1 (memory device 2_1- of the multiple write-ins of canonical example (2)>Memory device 2_2,2_n)：

Memory device 2_2 and 2_n is specified in transfer destination memory specifications field DSMEM, memory device 2_1 It is specified in transfer source memory specifications field SOMEM, and writing commands are specified in memory command field MCMD.Into one Step ground, desired address range are specified in data area field DAREA and address field Add.In this case, it is storing The data for the address range specified in the data area field DAREA of device device 2_1 pass through third data/address bus 33D and the second system It the control circuit CNT2 that is supplied in memory device 2_2 and 2_n of system bus SBUS2 and is written into and (is replicated) on ground The address range of the memory device 2_2 and 2_n that are specified in the field Add of location.In this case, it is known that transmission source memory rule Model field SOMEM is the memory device 2_1 of main side semiconductor device 1_1, so that omitting transfer source memory specifications field The specification of SOMEM is possible.

When memory device 2_2 ... and 2_n refers in transfer destination memory specifications field DSMEM periodically, depositing In the data area field DAREA of reservoir device 2_1 specify address range data be written to except memory device 2_1 it Outer all memory devices (2_2 ... and 2_n).

2 (memory device 2_1- are individually written in canonical example (3)>System storage SMEM1)：

System storage SMEM1 device is specified in transfer destination memory specifications field DSMEM, memory device 2_ 1 specifies in transfer source memory specifications field SOMEM, and reading order is specified in memory command field MCMD.Into One step, desired address range is specified in data area field DAREA and address field Add.In this case, it is depositing The data for the address range specified in the data area field DAREA of reservoir device 2_1 pass through third data/address bus 33D and second System bus SBUS2 is written into and (is replicated) address range to the system storage SMEM1 specified in address field Add. In this case, it is known that transfer source memory specifications field SOMEM is the memory device 2_1 of main side semiconductor device 1_1, So that the specification for omitting transfer source memory specifications field SOMEM is possible.

2 (memory device 2_1- of the multiple write-ins of canonical example (4)>Memory device 2_2, system storage SMEM1)：

Memory device 2_2 and system storage SMEM1 is specified in transfer destination memory specifications field DSMEM, Memory device 2_1 is specified in transfer source memory specifications field SOMEM, and writing commands are in memory command field It is specified in MCMD.Further, it is desirable to address range in data area field DAREA and address field Add specify.At this In the case of kind, the data for the address range specified in the data area field DAREA of memory device 2_1 pass through memory device Set the control circuit that second system bus SBUS2 and third the data/address bus 33D in 2_2 are supplied in memory device 2_2 CNT2 and the address range for being written into and (being replicated) into address field Add specified memory device 2_2.Further, The data for the address range specified in the data area field DAREA of memory device 2_1 pass through second system bus SBUS2 It is written into and (is replicated) to the address range specified in the address field Add of system storage SMEM1.In this case, Known transfer source memory specifications field SOMEM is the memory device 2_1 of main side semiconductor device 1_1, so that omitting transmission The specification of source memory normative field SOMEM is possible.

When specified in transfer destination memory specifications field DSMEM memory device 2_2 ... and 2_n and system Memory SMEM1, SMEM2 ... and when SMEMn, the specified ground in the data area field DAREA of memory device 2_1 The data of location range are written to all memory devices (2_2 ... and 2_n) in addition to memory device 2_1 and all System storage (SMEM1, SMEM2 ... and SMEMn).

3 (system storage SMEM1- are individually written in canonical example (5)>Memory device 2_1)：

Memory device 2_1 is specified in transfer destination memory specifications field DSMEM, and system storage SMEM1 exists It is specified in transfer source memory specifications field SOMEM, and reading order is specified in memory command field MCMD.Further Ground, desired address range are specified in data area field DAREA and address field Add.In this case, it is deposited in system The data for the address range specified in the data area field DAREA of reservoir SMEM1 pass through the second system in memory device 2_1 It the control circuit CNT2 that is supplied in memory device 2_1 of system bus SBUS2 and third data/address bus 33D and is written into The address range for the memory device 2_1 that (being replicated) specifies into address field Add.

3 (system storage SMEM1- of the multiple write-ins of canonical example (6)>Memory device 2_1,2_2)：

Memory device 2_1 and 2_2 is specified in transfer destination memory specifications field DSMEM, system storage SMEM1 is specified in transfer source memory specifications field SOMEM, and reading order refers in memory command field MCMD It is fixed.Further, it is desirable to address range in data area field DAREA and address field Add specify.In such case Under, the data for the address range specified in the data area field DAREA of system storage SMEM1 pass through memory device 2_ Second system bus SBUS2 and third data/address bus 33D in 1 are supplied to the control circuit CNT2 in memory device 2_1 And it is written to the address range of the memory device 2_1 specified in address field Add.Further, in data area word The data of the address range of the system storage SMEM1 specified in section DAREA are total by the second system in memory device 2_2 Control circuit CNT2 that line SBUS2 and third data/address bus 33D are supplied in memory device 2_2 and being written into (is answered System) into address field Add specify memory device 2_2 address range.When all memory device 2_1,2_2 ... Refer to timing in transfer destination memory specifications field DSMEM with 2_n, in the data area field of system storage SMEM1 The data for the address range specified in DAREA are written to all memory device 2_1, the 2_ specified in address field Add ... and the address range of 2_n 2,.

Those skilled in the art can easily understand that the specification of the above format when application above description, so that institute The description that there is something special is omitted.By using format as described above, using as aforementioned 1) to second described in 6) System bus SBUS2 is possible.Therefore, it is not limiting through data processing equipment using the second bus and the first system bus In the case where SBUS1, system (is replicated and consistently manages) by using third bus and second system bus SBUS2 management Memory SMEM1, SMEM2 ... the content and memory device 2_1,2_2 of SMEMn ... and the content of 2_n is possible.

Fig. 9 is another exemplary diagram for showing the format of control signal C1 and C2.In format shown in Fig. 9 and Fig. 8 Shown in difference between format be that memory mark information field TAG is also added to depositing in format shown in Fig. 9 Reservoir function control field MCONT.In data processing system shown in fig. 5, as memory device (2_1,2_ ready for use 2 ..., 2_n, SMEM1, SMEM2 ... and SMEMn) include different types memory device such as DRAM, SRAM and When flash memory, the memory command of each memory device is different from each other.Memory mark information field TAG is provided with energy Enough identify the type of memory device.In memory function control field MCONT, designated memory mark information field TAG, Memory command field MCMD, busy channel information attribute field BUSYFLAG and address field Add are possible.For example, working as Such as multiple DARM of a plurality of types of memory devices, multiple SRAM and multiple flash memory NVM/Flash are mixedly made With in a data processing system when, corresponding to TAG, MCMD, BUSYFLAG and Add of each DARM, corresponding to each SRAM's TAG, MCMD, BUSYFLAG and Add, and TAG, MCMD, BUSYFLAG and Add corresponding to each flash memory is in memory It is specified in function control field MCONT.Further, when each storage in memory device (2_1,2_2 ... and 2_n) Device device is mixed in an identical manner such as wherein dram chip, multiple sram chips, multiple flash memory dies When the stacked memory of ground installation, corresponding to TAG, MCMD, BUSYFLAG and Add of each dram chip, corresponding to each TAG, MCMD, BUSYFLAG and Add of sram chip and corresponding to each flash memory dies TAG, MCMD, BUSYFLAG and Add can be specified in memory function control field MCONT.

To, even if in the data processing system of memory device for including different types, it is total using second system The content that line SBUS2 manages memory device is also possible.

(modification 1 of memory device)

Figure 10 is the diagram for showing the modification 1 of the memory device of Fig. 7.Figure 10 is shown provides cache wherein Configuration example of the memory cache as 22 part of memory device of Fig. 7 in the case where circuit block CB shown in Fig. 6. Other configurations are identical as the configuration of Fig. 7.Cache memory cache, which is provided at, is coupled to the interior of selection circuit SEL1 Between portion data/address bus 33Di and third data/address bus 33D.Cache memory cache is provided so that block transmits Can as the data transmission using the second system bus SBUS2 between memory device, such as memory device 2_1 be Data transmission between system memory SMEM2.To which it is possible for promoting data administrator.

(modification 2 of memory device)

Figure 11 is the diagram for showing the modification 2 of the memory device of Fig. 7.When Figure 10 is shown in which to provide cache Memory cache is as when the configuration example of circuit block CB, Figure 11 is shown in which to provide computing circuit shown in Fig. 6 Configuration example of the AC as circuit block CB.Other configurations are identical as those of Fig. 7 and Figure 10 configuration.It is able to carry out simple operation operation Computing circuit AC be provided at be coupled to selection circuit SEL1 internal data bus 33Di and third data/address bus 33D it Between.By providing computing circuit AC, held in the data inputted by second system bus SBUS2 and third data/address bus 33D The desired arithmetic operation of row makes data for using, and to become optimal in data processing equipment be possible.For example, by Fortune is provided from the data processing equipment that sensor receives analog information and directly executes arithmetic operation in analog information Circuit AC is calculated, data processing equipment can schedule to last analog information conversion by executing desired arithmetic operation in analog information The digital information of prestige.To which it is possible for improving the efficiency of the data processing in data processing equipment.Computing circuit AC can be Digital operational circuit, programmable computing circuit, digital signal processor etc..

Figure 11 also shows the example of channel distribution.In Figure 11, the instruction of channel 1 and 3 to 16 is directed to data processing equipment The channel of the foreground processing distribution of 3_1.On the other hand, channel of the instruction of channel 2 for memory management distribution.Herein, channel 2 It can be considered as the channel of the processing in the backstage that be used to handle relative to foreground.At the end of memory management, divided The channel 2 for being fitted on background process can be changed to another channel such as channel 1 by the control of data processing equipment 3_1.It can The channel handled using assignment channel 2 as foreground.Data processing system 3_1 in its operating system (OS) there is channel to distribute function Energy.Channel request information can be transmitted to second control circuit from the 4th bus 34 as data processing equipment 3_1 by channel distribution It is performed when CNT2.In this case, when executing channel arbitration, it is desirable that will be from the channel that data processing equipment 3_1 is transmitted The priority level initializing of solicited message is to high-level.

Figure 12 is the diagram for showing another allocation example of channel distribution of Figure 11.In Figure 12, channel 1 to 3 is assigned To background process and channel 4 to 16 is assigned to foreground processing.Other configurations are identical as those of Fig. 7 and Figure 11 configuration.It should Configuration can be used for the processing that identical data is such as written to channel 1 to 3.When by multiple channels such as channel 1 to 3 When being assigned to background process, for example, by channel distribution normative field being newly added to the format of Fig. 8 and make can will be multiple It is possible that channel, which is assigned in channel distribution normative field and executes distribution,.

(modification 3 of memory device)

Figure 13 is the diagram for showing the modification 3 of the memory device of Fig. 7.Figure 13 is shown when by memory device 2_ 1 channel 1 (L1) and channel 2 (L2) realize primary cache memory L1 shown in Fig. 3 and secondary cache storage Schematic constitution example when device L2.Primary cache memory (channel 1 (L1)) and secondary cache memory (channel 2 (L2)) cache control circuit CACHE_CONT is drawn to be disposed in selection circuit SEL1 and channel 1 (L1) and 2 (L2) between.It is (logical that primary cache memory is executed by using second system bus SBUS2 and third data/address bus 33D Road 1 (L1)) and the management of storage content of secondary cache memory (channel 2 (L2)) be possible.

(modification 1 of data processing system)

Figure 14 is the diagram of the modification 1 for the data processing system for showing Fig. 5.In Fig. 5, the first system bus SBUS1 With second system bus SBUS2 be coupled to system storage SMEM1, SMEM2 ... and SMEMn, is Two-port netwerk memory. In Figure 14, system storage SMEM1, SMEM2 ... and each system storage in SMEMn is that have input/defeated The one-port memory of exit port, and input/output end port is coupled to the first system bus SBUS1.Therefore, in the example In, crossbar switch CrossSW is provided between the first system bus SBUS1 and second system bus SBUS2, so that system is deposited Reservoir SMEM1, SMEM2 ... and SMEMn can be coupled with second system bus SBUS2.The configuration phase of other configurations and Fig. 5 Together.

Also in configuration as described above, by using second system bus SBUS2 without the use of the first system bus SBUS1 managing semiconductor device 1_1,1_2 ... and system storage SMEM1, SMEM2 in 1_n ... and SMEMn's is interior Hold and memory device 2_1,2_2 ... and the content of 2_n is possible.

[second embodiment]

Figure 15 is the conceptual block diagram of semiconductor device according to the second embodiment.Although the semiconductor device 1 of Fig. 3 is mentioned It is provided with a data processing equipment 3 and a memory device 2, but the semiconductor device 1a of Figure 15 is provided with a data Processing unit 3 and four memory devices (first memory device, second memory device, third memory devices and the 4th Memory device) 2-1,2-2,2-3 and 2-4.Therefore, the semiconductor device 1a of Figure 15 is provided there are four the first external terminal 61-1,61-2,61-3 and 61-4 are second interface unit IF2.By with it is identical in Fig. 3 in a manner of, the first bus is provided 31, third bus 33, the 4th bus 34 and control circuit CNT are deposited for each of memory device 2-1,2-2,2-3 and 2-4 Reservoir device.Other configurations are identical as the configuration of Fig. 3 of first embodiment.The first bus 31, third bus 33 in Figure 15, Four buses 34 and control circuit CNT are identical as those of in Fig. 6, so that its description is omitted.

Figure 16 is the composition figure according to the data processing system of the semiconductor device of Figure 15.The data processing system packet of Figure 16 Include multiple semiconductor device 1a_1,1a_2 ... and 1a_n.Semiconductor device 1a_1,1a_2 ... and each of 1a_n half Conductor device corresponds to the semiconductor device 1a in Figure 15.Semiconductor device 1a_1 have multiple first external terminal 61-1_1, 61-2_1,61-3_1 and 61-4_1 are coupled to second system bus SBUS2.Semiconductor device 1a_1 also has outside second Terminal 62-1 is coupled to the first system bus SBUS1.Similarly, semiconductor device 1a_2 ... and 1a_n has multiple the One external terminal (61-1_2,61-2_2,61-3_2 and 61-4_2 ... and 61-1_n, 61-2_n, 61-3_n and 61-4_n), It is coupled to second system bus SBUS2.Further, similarly, semiconductor device 1a_2 ... and 1a_n have second outside Portion's terminal (62_2 ... and 62_n), it is coupled to the first system bus SBUS1.By with it is identical in Fig. 5 in a manner of, system Memory SMEM1, SMEM2 ... and each system storage in SMEMn is Two-port netwerk memory.One in two ports It is a to be coupled to the first system bus SBUS1 and second system bus SBUS2 is coupled in another port.

Figure 17 is the composition figure according to another data processing system of the semiconductor device of Figure 15.With the data processing of Figure 16 System the difference is that, system storage SMEM1, SMEM2 ... and the input of each system storage in SMEMn/defeated Exit port is single port and crossbar switch CrossBar is provided at the first system bus SBUS1 and second system bus Between SBUS2.In other words, at the data for being used in Figure 14 Figure 17 shows multiple semiconductor device 1a in wherein Figure 15 Data processing system in reason system.Other configurations are identical as the configuration of Figure 16.

Also in the configuration of second embodiment as described above, by using second system bus SBUS2 without the use of The first system bus SBUS1 managing semiconductor device 1_1,1_2 ... and system storage SMEM1 in 1_n, SMEM2 ... and SMEMn content and memory device 2_1,2_2 ... and the content of 2_n is possible.

[3rd embodiment]

Figure 18 is the block diagram of the modification of semiconductor device according to the third embodiment.The semiconductor device 1a and figure of Figure 15 Difference between 18 semiconductor device 1b is that there are four memory devices although the semiconductor device 1b of Figure 18 is provided (first memory device, second memory device, third memory device and the 4th memory device) 2-1,2-2,2-3 and 2- 4, but semiconductor device 1b is provided with only one external terminal 61.Particularly, although by with it is identical in Figure 15 in a manner of The first bus 31, third bus 33, the 4th bus 34 and control circuit CNT are provided for four memory devices 2-1,2-2,2- Each memory device in 3 and 2-4, but the third bus 33 of four memory devices is coupled to public third bus 33C And public third bus 33C is coupled to first external terminal 61.As shown in the dotted line in the top as Figure 18, public Three bus 33C can be provided in semiconductor device 1b with annular shape.

Figure 19 is the composition figure according to the data processing system of the semiconductor device of Figure 18.The data processing system packet of Figure 19 Include multiple semiconductor device 1b_1,1b_2 ... and 1b_n.Semiconductor device 1b_1,1b_2 ... and each of 1b_n half Conductor device corresponds to the semiconductor device 1b in Figure 18.Semiconductor device 1b_1 has the first external terminal 61_1, coupling To second system bus SBUS2.Semiconductor device 1b_1 also has the second external terminal 62_1, is coupled to the first system bus SBUS1.Similarly, semiconductor device 1b_2 ... and 1b_n also have multiple first external terminals (61_2 ... and 61_ N), it is coupled to second system bus SBUS2.Further, similarly, semiconductor device 1b_2 ... and 1b_n has the Two external terminals (62_2 ... and 62_n), it is coupled to the first system bus SBUS1.By with it is identical in Fig. 5 in a manner of, System storage SMEM1, SMEM2 ... and each system storage in SMEMn is Two-port netwerk memory.In two ports One be coupled to the first system bus SBUS1 and second system bus SBUS2 is coupled in another port.

Figure 20 is the composition figure according to another data processing system of the semiconductor device of Figure 18.With the data processing of Figure 19 System the difference is that, system storage SMEM1, SMEM2 ... and the input of each system storage in SMEMn/defeated Exit port is single port and crossbar switch CrossBar is provided at the first system bus SBUS1 and second system bus Between SBUS2.In other words, Figure 20 is shown at the data that multiple semiconductor device 1b of wherein Figure 18 are used in Figure 14 Data processing system in reason system.Other configurations are identical as the configuration of Figure 19.

Also in the configuration of 3rd embodiment as described above, by using second system bus SBUS2 without the use of The first system bus SBUS1 managing semiconductor device 1_1,1_2 ... and system storage SMEM1 in 1_n, SMEM2 ... and SMEMn content and memory device 2_1,2_2 ... and the content of 2_n is possible.

[fourth embodiment]

Figure 21 is the composition figure according to the data processing system of fourth embodiment.Figure 21 is shown in which the data in Fig. 5 The subsystem memory for being coupled to the first system bus SBUS1 and second system bus SBUS2 is newly provided in processing system The configuration of SUSYSM.Subsystem memory SUSYSM is provided to add one layer of shared memory for second system bus SBUS2 And integrally management requires public shared data.The first system bus SBUS1 general view is by subsystem memory SUSYSM Host, make parallelization data processing equipment 1_1,1_2 ... and 1_n virtualization and controls data plane.Subsystem storage Device SUSYSM includes shared memory SHMEM, and public shared data is required to be stored in shared memory SHMEM. Subsystem memory SUSYSM has：Shared memory SHMEM shares storage device 2_1,2_ of multicore data processing system 2 ... and the storage space of 2_n is as system pool；And controller, control shared memory SHMEM.

By in multicore data processing system, executing wherein storage device 2_1,2_ in configuration as described above 2, the control ... being integrated in entire data system with the storage content in 2_n is possible.Further, pass through addition One layer of shared memory is so that shared memory stratification is performed simultaneously the control in data processing equipment and carrys out distributed data transmission Load with data processing is possible.

(modification)

Hereinafter, example the modification according to the present invention will be described.

Hereinafter, description is wherein provided to described control circuit CNT (CNT_1, CNT_ in the first embodiment 2 ... and CNT_n) part as modification.Circuit block CB (the cache memory in Figure 10 as described in Figure 6 Computing circuit in cache, Figure 11) it can be included in control circuit CNT.

(modification 1)

Figure 22 is the diagram for showing the configuration example of the semiconductor device according to modification 1.In Fig. 6 of first embodiment, Show the example in the configuration for wherein providing control circuit CNT in base chip 21.It partly leads shown in (a) of Figure 22 In body device 1c, control circuit CNT is provided at data processing equipment 3 rather than in the base chip 21 of memory device 2.? In this case, for example, it is preferable that, included Memory Controller includes control circuit CNT in data processing equipment 3 Function.(b) of Figure 22 is to be installed in the configuration on the upper surface of data processing equipment 3, i.e., three in wherein memory device 2 The conceptual cross-sectional view of dimension installation semiconductor device 1c.

In such a configuration, it is also possible for obtaining effect identical with the effect of first embodiment.

(modification 2)

Figure 23 is the diagram for showing the configuration example of the semiconductor device according to modification 2.Figure 24 is shown according to modification 2 Data processing system configuration example diagram.In modification 2, as shown in Figure 24, control circuit CNT is provided to Subsystem memory SUSYSM described in Figure 21.In this case, semiconductor device 1d_1,1d_ shown in Figure 24 2 ... and each semiconductor device in 1d_n is the data processing equipment 1d with configuration as shown in Figure 23.Scheming In data processing equipment 1d shown in 23, the configuration of the control circuit CNT in base chip 21 is not provided in data processing In device 1d.On the contrary, control circuit CNT is provided to subsystem memory SUSYSM.In some cases, including second controls The circuit part of circuit CNT2 and selection circuit SEL1 can be provided to subsystem memory SUSYSM.

(modification 3)

Figure 25 is the diagram for showing the configuration example of the data processing system according to modification 3.In the modification 2 of Figure 24, Control circuit CNT is provided to subsystem memory SUSYSM.In modification 3, the subsystem including control circuit NCT is not provided Unite memory SUSYSM.On the contrary, control circuit CNT is coupled between the first system bus SBUS1 and second system bus SBUS. As data processing equipment 1d_1,1d_2 ... and 1d_n, using having shown in Figure 23 described in modification 2 The data processing equipment 1d of configuration is possible.In some cases, including second control circuit CNT2 and selection circuit SEL1 Circuit part may be provided between the first system bus SBUS1 and second system bus SBUS2.

(modification 4)

Figure 26 is the diagram for showing the configuration example of the semiconductor device according to modification 4.Figure 26 is memory device wherein The configuration on the upper surface that 2 are installed in data processing equipment 3 is set (that is, the conceptual section view of three-dimensional installation semiconductor device 1e Figure).In the modification 1 of Figure 22, it is shown in which the example that control circuit CNT is provided in data processing equipment 3.At this In example, control circuit CNT is provided in such as memory chip 224.Control circuit CNT may be provided in storage core In any of piece 221,222,223 and 224.Alternatively, control circuit CNT can dispersedly be provided to memory chip 221,222,223 and 224.

Although based on the particularly described present invention made by inventor of embodiment, but it go without saying that the present invention is unlimited It can modify in embodiment and differently.

Claims

1. a kind of semiconductor device, including：

First external terminal；

Second external terminal；

Data processing equipment；

Memory device；

First bus, first bus are coupled between the data processing equipment and the memory device；

Second bus, second bus are coupled between the data processing equipment and second external terminal；

Third bus, the third bus are coupled to first external terminal；And

Control circuit, the control circuit are coupled to first bus and the third bus；

Wherein, the control circuit has the management function using the third bus to the memory device.

2. semiconductor device according to claim 1,

Wherein, the data processing equipment includes central processing unit and cache memory.

3. semiconductor device according to claim 2,

Wherein, the memory device includes

Base chip, and

Semiconductor memory, the semiconductor memory are installed in the base chip, and

Wherein, the control circuit is provided in the base chip.

4. semiconductor device according to claim 3,

Wherein, the semiconductor memory includes the semiconductor chip of multiple stackings.

5. semiconductor device according to claim 3,

Wherein, the memory device includes first memory device, second memory device, third memory device and the 4th Memory device, and

Wherein, first external terminal includes：First terminal, the first terminal are coupled to the first memory device； Second terminal, the Second terminal are coupled to the second memory device；Third terminal, the third terminal are coupled to described Third memory device；And forth terminal, the forth terminal are coupled to the 4th memory device.

6. semiconductor device according to claim 3,

Wherein, the first memory device, the second memory device, the third memory device and the described 4th are deposited Each of reservoir device is coupled to first external terminal by the third bus.

7. a kind of data processing system, including：

System bus；

Secondary bus；

System storage, the system storage are coupled to the system bus and the secondary bus；

Multiple semiconductor devices, the multiple semiconductor device are coupled to the system bus and the secondary bus, and institute Stating each of multiple semiconductor devices includes data processing equipment and memory device；And

Control circuit,

Wherein, the control circuit has the pipe using the third bus to the memory device and the system storage Manage function.

8. data processing system according to claim 7,

Wherein, the control circuit is provided to each of described semiconductor device.

9. data processing system according to claim 8,

Wherein, each of described semiconductor device includes

First external terminal, first external terminal are coupled to the secondary bus,

Second external terminal, second external terminal are coupled to the system bus,

Second bus, second bus are coupled between the data processing equipment and second external terminal；And

Third bus, the third bus are coupled to first external terminal, and

Wherein, the control circuit is coupled to first bus and the third bus.

10. data processing system according to claim 9,

Wherein, the memory device includes

Base chip, and

Semiconductor memory, the semiconductor memory are mounted in the base chip, and

Wherein, the control circuit is provided in the base chip.

11. data processing system according to claim 10,

12. data processing system according to claim 10,

13. data processing system according to claim 10,

14. data processing system according to claim 7,

Wherein, the control circuit is provided between the system bus and the secondary bus.

15. data processing system according to claim 7, further includes：

Subsystem memory, the subsystem memory are coupled between the system bus and the secondary bus.

16. data processing system according to claim 15,

Wherein, the control circuit is provided in the subsystem memory.