Summary of the invention
Present invention solves the technical problem that being how to improve the PPI and resolution ratio of image display device.
In order to solve the above technical problems, the embodiment of the present invention provides a kind of OLED pixel circuit, the OLED pixel circuit
Including:OLED element, first end access the first supply voltage;Driving circuit, output end couple the of the OLED element
Two ends, input terminal access second source voltage, and the driving circuit is suitable for generating driving current, and the driving current is for driving
The OLED element is moved to shine;First switch, in response to the first scanning voltage, the first switch is suitable for image data voltage
It is transmitted to the control terminal of the driving circuit, described image data voltage is used to control the size of the driving current;Wherein, institute
The symbol of the first supply voltage and second source voltage is stated on the contrary, and each falling within and being defined by positive boundary voltage and negative edge voltage
Technological limits voltage range.
Optionally, first supply voltage is less than 0V, and the second source voltage is greater than 0V, and the of the OLED element
One end is cathode, and the second end of the OLED element is anode.
Optionally, the OLED pixel circuit further includes:Second switch, one end couple the anode of the OLED element,
Its other end accesses resetting voltage, and in response to the second scanning voltage, the resetting voltage is transmitted to described by the second switch
The anode of OLED element, wherein the resetting voltage is for resetting the OLED element.
Optionally, the second switch includes:The first transistor, control terminal access second scanning voltage, the
The resetting voltage is accessed in one end, and second end couples the anode of the OLED element.
Optionally, the resetting voltage is less than 0V, and the first transistor is the deep trap being prepared using deep trap technique
Transistor.
Optionally, the first transistor is N-type MOS transistor, and grid end accesses second scanning voltage, source
The resetting voltage is accessed with body end, drain terminal couples the anode of the OLED element, and deep trap is terminated into the second source
Voltage, substrate terminal ground connection.
Optionally, the driving circuit includes:Transistor is driven, control terminal couples the control terminal of the driving circuit,
Its second end couples the output end of the driving circuit;Third switch, one end couple the first end of the driving transistor, institute
The second end for stating third switch accesses the second source voltage, and in response to light-emission control voltage, the third switch is suitable for passing
The defeated second source voltage is to the driving transistor;Voltage holding circuit, suitable for maintaining the control of the driving transistor
The voltage at end.
Optionally, the voltage holding circuit includes:The second source voltage is accessed in one end of capacitor, the capacitor,
The other end of the capacitor couples the control terminal of the driving transistor.
Optionally, the first switch includes:Second transistor, control terminal access first scanning voltage, the
Described image data voltage is accessed in one end, and second end couples the control terminal of the driving transistor;The third switchs:
Third transistor, control terminal access the light-emission control voltage, and first end accesses the second source voltage, second end
Couple the driving transistor;Wherein, the first transistor, second transistor, third transistor and driving transistor preparation
In same substrate, the second transistor, third transistor and driving transistor are the depths being prepared using deep trap technique
Trap transistor.
Optionally, the second transistor is N-type MOS transistor, and the third transistor and driving transistor are p-type
MOS transistor;Wherein, the grid end of the second transistor accesses first scanning voltage, and source accesses described image number
According to voltage, drain terminal couples the control terminal of the driving transistor, body end ground connection, and deep trap is terminated into the second source electricity
Pressure, substrate terminal ground connection;The grid end of the third transistor accesses the light-emission control voltage, source access second electricity
Source voltage, drain terminal couple the source of the driving transistor, and body end accesses the second source voltage, substrate termination
Ground;The grid end of the driving transistor couples the control terminal of the driving circuit, and drain terminal couples the output of the driving circuit
End, body end access the second source voltage, substrate terminal ground connection.
Optionally, when the OLED pixel circuit works in reseting stage, first scanning voltage control described the
One switch OFF, the light-emission control voltage control the third switch OFF, the second scanning voltage control described second
Switch conduction.
Optionally, when the OLED pixel circuit works in data write phase, the light-emission control voltage controls institute
Third switch OFF is stated, second scanning voltage controls the second switch and turns off, described in the first scanning voltage control
First switch conducting.
Optionally, when the OLED pixel circuit works in light emitting phase, second scanning voltage control described the
Two switch OFFs, first scanning voltage control the first switch shutdown, and the light-emission control voltage controls the third
Switch conduction.
In order to solve the above technical problems, the embodiment of the present invention also provides a kind of image display device, described image display dress
It sets including above-mentioned OLED pixel circuit.
Compared with prior art, the technical solution of the embodiment of the present invention has the advantages that:
The OLED pixel circuit of the embodiment of the present invention may include OLED element, driving circuit and first switch, and described
One end incoming image data voltage of one switch, the OLED pixel circuit work in the first supply voltage and second source voltage
Between, the symbol of first supply voltage and second source voltage is on the contrary, and each fall within by positive boundary voltage and negative edge electricity
Press the technological limits voltage range defined, that is to say, that first supply voltage and second source in the embodiment of the present invention
The power supply voltage range that voltage is defined is the maximum supply voltage range that preset technique allows.Wherein, the driving circuit
The voltage range that can be worked is that the part for the pressure drop that the OLED element occupies is removed in maximum supply voltage range, in institute
It states and is the largest under preset technique, which dictates that the effective voltage value range of described image data voltage is described preset
Be under technique it is widest, for scheme compared with the prior art, the scheme of the embodiment of the present invention is more conducive to image and shows
The high-resolution realization of high PPI of device.
Furthermore, the OLED pixel circuit of the embodiment of the present invention can also include second switch, and one end couples institute
The anode of OLED element is stated, the other end accesses resetting voltage;The second switch may include:The first transistor;It is described multiple
Position voltage can be less than 0V, and the first transistor can be the deep trap transistor being prepared using deep trap technique, Ke Yi
While guaranteeing the power supply voltage range of OLED pixel circuit, so that OLED pixel circuit has good noiseproof feature.
Furthermore, the driving circuit may include driving transistor, third switch.The first switch can wrap
Second transistor is included, the third switch includes third transistor.The first transistor, second transistor, third transistor
It can be prepared in same substrate with driving transistor, the second transistor, third transistor and driving transistor can be
The deep trap transistor being prepared using deep trap technique, can be effectively avoided and cause island effect in semiconductor processing, mention
The degree of integration of pixel of hi-vision display device is more conducive to the high-resolution realization of high PPI.
Specific embodiment
As described in the background section, currently, due to being limited by many factors such as techniques, silicon-based organic light-emitting two
OLED pixel circuit general work in pole pipe (Organic Light-Emitting Diode, abbreviation OLED) display is in 0
To between the voltage of positive boundary or 0 between negative edge voltage, and in view of OLED from it is luminous when the cross-pressure that generates, make
The effective voltage value range for obtaining above-mentioned image data voltage is very narrow, is unfavorable for the high-resolution reality of high PPI of OLED display
It is existing.
The present invention proposes a kind of OLED pixel circuit, takes full advantage of the technological limits voltage model in integrated circuit technology
It encloses, the effective value range for the image data voltage that can be widened, is conducive to the high-resolution reality of high PPI of OLED display
It is existing.
It is understandable to enable above-mentioned purpose of the invention, feature and beneficial effect to become apparent, with reference to the accompanying drawing to this
The specific embodiment of invention is described in detail.
Fig. 1 shows a kind of schematic block diagram of OLED pixel circuit according to an embodiment of the present invention.Referring to Fig. 1,
OLED pixel circuit 100 can be applied in image display device (not shown).Specifically, the OLED pixel circuit 100 can
To include OLED element D1, driving circuit 10 and first switch SW1.
Wherein, the OLED element D1 belongs to current drive-type element, within the scope of reasonable size of current, flows through described
The electric current of OLED element D1 is bigger, and luminous intensity is higher.The OLED element D1 itself will occupy a part when luminous
The size of pressure drop, the pressure drop is determined by the material of the OLED element D1.
In the present embodiment, the first end of the OLED element D1 can access the first supply voltage VSS.The driving electricity
The output end on road 10 couples the second end of the OLED element D1, and the input terminal of the driving circuit 10 can access second source
Voltage VDD, the driving circuit 10 are suitable for generating driving current Id, and the driving current Id is for driving the OLED element D1
It shines.
The first switch SW1 is in response to the first scanning voltage SCAN1, suitable for image data voltage DATA is transmitted to institute
The control terminal of driving circuit 10 is stated, described image data voltage DATA is used to control the size of the driving current Id.Wherein, institute
Stating image data voltage DATA and the first scanning voltage SCAN1 can be generated by control device (not shown).Under normal circumstances, institute
It is bigger to state image data voltage DATA, the driving current Id is bigger, and the OLED element D1 luminous intensity is higher.Therefore,
Effective value range of described image data voltage DATA is wider, it is meant that the fineness of OLED luminous intensity is thinner, then image
The PPI and resolution ratio of display device are higher.
In the present embodiment, the symbol of the first supply voltage VSS and second source voltage VDD are on the contrary, and each fall within
The technological limits voltage range defined by positive boundary voltage and negative edge voltage.For example, the technological limits voltage is by positive side
The technological limits voltage range [- 5V, 5V] that boundary voltage 5V and negative edge voltage -5V are defined.At this point, first supply voltage
VSS can be -5V, and the second source voltage VDD can be 5V;Alternatively, the first supply voltage VSS can be -3.3V,
The second source voltage VDD can be 4V;Again alternatively, the first supply voltage VSS can be -2.5V, second electricity
Source voltage VDD can be 1.8V etc..Certainly, the technological limits voltage range can also be defined by other boundary voltages,
This is generally restricted by the technique of integrated circuit (for example, intending the technique selected in ic manufacturing process), herein no longer one by one
It illustrates.
In specific implementation, it can be the first supply voltage VSS to be greater than less than 0V, the second source voltage VDD
The first end of 0V, the OLED element D1 are cathode, and the second end of the OLED element D1 is anode, that is to say in Fig. 1 and show
The case where.
In a change case, it can be the second source voltage VDD and be greater than less than 0V, the first supply voltage VSS
The second end of 0V, the OLED element D1 are cathode, and the first end of the OLED element D1 is anode.For example, first electricity
Source voltage VSS can be successively via the anode of the OLED element D1, the cathode of the OLED element D1, the driving circuit 10
It is transmitted to the port where the second source voltage VDD.
The OLED pixel circuit 100 works between the first supply voltage VSS and second source voltage VDD, this
The power supply voltage range that the first supply voltage VSS and second source voltage VDD in embodiment are defined is preset work
The maximum supply voltage range that skill allows.The voltage range that the driving circuit 10 can work is in maximum supply voltage range
The middle part for removing the pressure drop that the OLED element D1 is occupied, is the largest, which dictates that described under the preset technique
The effective voltage value range of image data voltage DATA be under the preset technique it is widest, compared with the prior art
For scheme, the scheme of the embodiment of the present invention is more conducive to the high-resolution realization of high PPI of image display device.For example,
The first supply voltage VSS can be -5V, and the second source voltage VDD can be 5V, and the OLED element D1 is shining
The pressure drop of Shi Zhanyong is 2V to 5V, namely is up to 5V, and therefore, the voltage range that the driving circuit 10 can work is at least
0V to 5V, or -5V to 0V.Accordingly, the effective voltage value range of described image data voltage DATA is also at least 0V extremely
5V, or -5V to 0V.
Below will be with the first supply voltage VSS for -5V, the second source voltage VDD is 5V, the OLED element
The first end of D1 is cathode, and the second end of the OLED element D1 is to be illustrated for anode.
Fig. 2 shows the schematic block diagrams of another OLED pixel circuit according to an embodiment of the present invention.In Fig. 2
The structure of OLED pixel circuit 200 is similar with OLED pixel circuit 100 hereinbefore, and the main distinction is, the OLED picture
Plain circuit 200 can also include:Second switch SW2, one end couple the anode of the OLED element D1, and other end access is multiple
Position voltage VREF, in response to the second scanning voltage SCAN2, for example, when the second scanning voltage SCAN2 is logic high
When, the resetting voltage VREF is transmitted to the anode of the OLED element D1 by the second switch SW2, for example, when described the
When two scanning voltage SCAN2 are logic low, the second switch SW2 will cut off the resetting voltage VREF be transmitted to it is described
The access of the anode of OLED element D1.Wherein, the resetting voltage VREF is used to reset the OLED element D1, due to
The OLED element D1 may have residual charge in its anode after controlled shine, and above-mentioned reset is represented to the OLED element D1
In the process released of residual charge, to prevent OLED element D1 from accidentally shining.
In specific implementation, generally setting reset circuit (not shown) resets the OLED element D1, described multiple
Position circuit output has the resetting voltage VREF.Optionally, in the reset circuit can stream have resetting current (not shown) with
So that releasing above-mentioned residual charge to ground.
Fig. 2 and Fig. 3 is combined together, and in specific implementation, the second switch SW2 includes the first transistor M1, control
It terminates into the second scanning voltage SCAN2, first end accesses the resetting voltage VREF, and second end couples the OLED
The anode of element D1.
In the present embodiment, since the OLED element D1 is when luminous, the current potential of anode levels off to 0V, therefore,
In this case, it is that negative voltage namely the resetting voltage VREF can be less than 0V that the resetting voltage VREF, which can be set,.By
The device of existing transmission positive voltage in the OLED pixel circuit 200, and have the device of transmission negative voltage, and the OLED
All devices in pixel circuit 200 need to be prepared in same substrate, and therefore, the embodiment of the present invention the first transistor M1 is to adopt
The deep trap transistor being prepared with deep trap technique, further, the deep trap transistor can make the OLED pixel electricity
Road 200 has good noiseproof feature.
When the substrate is P type substrate, the first transistor M1 can be used deep N-well technique and be prepared;When described
When substrate is N-type substrate, the first transistor M1 can be used deep p-well technique and be prepared.Unless otherwise specified, herein
Substrate is P type substrate.
Referring to fig. 4, in specific implementation, the first transistor M1 can be N-type MOS transistor, the first crystal
Pipe M1 can have grid end (Gate) n1, source (Source) n2, drain terminal (Drain) n3, body end (Bulk) n4, deep trap end
(Deep Well) n5 and substrate terminal (Substrate) n6.
With continued reference to Fig. 2 and Fig. 3, the grid end of the first transistor M1 accesses the second scanning voltage SCAN2, source
End and body end access the resetting voltage VREF, and drain terminal couples the anode of the OLED element D1, and deep trap end n5 accesses institute
State second source voltage VDD, substrate terminal n6 ground connection.Herein, to put it more simply, only individually denoting the first transistor M1's
Deep trap end n5 and substrate terminal n6.
Furthermore, in the OLED pixel circuit 200, the driving circuit 10 may include driving transistor
DM, third switch SW3 and voltage holding circuit 101.
Wherein, the control terminal of the driving transistor DM couples the control terminal of the driving circuit 10, the driving crystal
The second end of pipe DM couples the output end of the driving circuit 10.One end of the third switch SW3 couples the driving crystal
The second end of the first end of pipe DM, the third switch SW3 accesses the second source voltage VDD, in response to light emitting control electricity
EMIT, the third switch SW3 is pressed to be suitable for transmitting the second source voltage VDD to the driving transistor DM, wherein described
Light-emission control voltage EMIT shines for controlling the OLED element D1.The voltage holding circuit 101 is suitable for maintaining the drive
The voltage of the control terminal of dynamic transistor DM, so that the size of the driving current Id is stablized, to guarantee the OLED element D1's
Luminous intensity is stablized.
In specific implementation, the voltage holding circuit 101 may include capacitor C1, and institute is accessed in one end of the capacitor C1
Second source voltage VDD is stated, the other end of the capacitor C1 couples the control terminal of the driving transistor DM.
It should be noted that the capacitor C1 be equivalent capacity, can be a capacitor, be also possible to multiple capacitors or
Appearance type impedance carries out what series and parallel obtained.
In specific implementation, the third switch SW3 may include third transistor M3, and control terminal access is described to shine
Voltage EMIT is controlled, first end accesses the second source voltage VDD, and second end couples the driving transistor DM.
In specific implementation, the first switch SW1 includes second transistor M2, control terminal access first scanning
Voltage SCAN1, first end access described image data voltage DATA, and second end couples the control of the driving transistor DM
End.
In embodiments of the present invention, the first transistor M1 and second transistor M2 can be N-type MOS crystal
Pipe, the third transistor M3 and driving transistor DM can be N-type MOS transistor, wherein the first transistor M1 is
Deep trap transistor, and the second transistor M2, the third transistor M3 and driving transistor DM can use deep trap technique
Common process in addition is prepared.
It should be noted that aforementioned four transistor is not limited to the above-mentioned type, for example, the third transistor M3 and driving
Transistor DM can also be N-type MOS transistor, and the first transistor M1 and the second transistor M2 can also be p-type
MOS transistor.In in actual implementation, specific preparation process can be determined according to the working condition of each transistor, it can be with
It suitably uses deep trap technique to be prepared through wherein some or certain several transistors, has both guaranteed the OLED pixel circuit
200 wider power supply voltage ranges, but all transistors for making it internal are prepared in same substrate.
In embodiments of the present invention, the OLED pixel circuit 200 at least controlled can work in reseting stage, data are write
Enter stage and light emitting phase.
Specifically, when the OLED pixel circuit 200 works in reseting stage, the first scanning voltage SCAN1 can
To control the first switch SW1 shutdown, the light-emission control voltage EMIT can control the third switch SW3 shutdown, institute
Stating the second scanning voltage SCAN2 can control the second switch SW2 conducting.For example, the first scanning voltage SCAN1 is to patrol
Low level is collected, the light-emission control voltage EMIT is logic high, and the second scanning voltage SCAN2 is logic high,
So that described image data voltage DATA can not be transferred to the driving transistor DM, the driving current can not be generated
Id。
Specifically, when the OLED pixel circuit 200 works in data write phase, the light-emission control voltage EMIT
Can control the third switch SW3 shutdown, the second scanning voltage SCAN2 can control the second switch SW2 shutdown,
The first scanning voltage SCAN1 can control the first switch SW1 conducting.For example, the light-emission control voltage EMIT is
Logic high, the second scanning voltage SCAN2 are logic low, and the first scanning voltage SCAN1 is logically high electricity
It is flat, so that described image data voltage DATA is transferred to the driving transistor DM.
Specifically, when the OLED pixel circuit 200 works in light emitting phase, the second scanning voltage SCAN2 can
To control the second switch SW2 shutdown, the first scanning voltage SCAN1 can control the first switch SW1 shutdown, institute
Stating light-emission control voltage EMIT can control the third switch SW3 conducting.For example, the second scanning voltage SCAN2 is to patrol
Low level is collected, the first scanning voltage SCAN1 is logic low, and the light-emission control voltage EMIT is logic low,
The driving transistor DM is worked, the driving current Id is generated according to described image data voltage DATA.
Furthermore, in embodiments of the present invention, the first transistor M1, second transistor M2, third transistor
M3 and driving transistor DM are prepared in same substrate, it is preferable that the second transistor M2, third transistor M3 and driving crystal
Pipe DM can be the deep trap transistor being prepared using deep trap technique.
Because if the only described the first transistor M1 is deep trap transistor, in semiconductor processing, independent deep trap device
Part will form isolated island, and when connecting with other transistors, will cause excessive metal aperture and line, so that layout design and technique
It becomes difficult, and is unfavorable for the high PPI design of image display device, it therefore, can be by all crystalline substances in order to avoid this phenomenon
Body pipe is prepared using deep trap technique, to improve the degree of integration of pixel of image display device, is more conducive to high PPI high score
The realization of resolution.
Referring to Fig. 5, herein only with the device profile of a N-type MOS transistor and a N-type MOS transistor shown in Fig. 5
The preparation process of the transistor in the present embodiment is illustrated for figure.It in specific implementation, can be in P type substrate P-sub
Middle progress heavy doping to form deep trap N-well-1, be connected with N deep trap N-well-1 be N-type MOS transistor deep trap
N5 is held, acceptor ion is deposited on the deep trap and forms P deep trap P-well, being connected with P deep trap P-well is N-type MOS
The body end n4 of transistor, the heavy doping donor ion N+ in the P deep trap P-well, to be respectively formed the source of N-type MOS transistor
Hold n2 and drain terminal n3, wherein n1 is the grid end of N-type MOS transistor.N-type MOS transistor is also prepared in the P type substrate P-sub
In, donor ion is deposited in deep trap N-well-1 and forms deep trap N-well-2, and being connected with N deep trap N-well-2 is P
The body end p4 of type MOS transistor deposits acceptor ion P+, in the deep trap N-well-2 to be respectively formed PMOS transistor
Source p2 and drain terminal p3.Wherein, the substrate terminal of N-type MOS transistor and the substrate terminal of N-type MOS transistor are all connected with P type substrate
(P-sub)。
Fig. 6 shows the third transistor M3, the third transistor M3 that are prepared in the way of shown in Fig. 5 can be with
With grid end p1, source p2, drain terminal p3, body end p4 and substrate terminal p5.Due to the structure and described the of the driving transistor DM
Three transistor M3 are similar, and the structure of the second transistor M2 is similar with the first transistor M1 shown in Fig. 4, to put it more simply, this
Place no longer repeats one by one.
A kind of OLED pixel circuit 300 is shown referring to Fig. 7, Fig. 7 referring to fig. 2 together, wherein all transistors are depth
Trap transistor.OLED pixel circuit 300 is similar with OLED pixel circuit 200 hereinbefore, and the main distinction is, and described
The grid end of two-transistor M2 accesses the first scanning voltage SCAN1, and source accesses described image data voltage DATA, leakage
The control terminal of the end coupling driving transistor DM, body end ground connection, deep trap end n5 access the second source voltage VDD,
Its substrate terminal n6 ground connection.The grid end of the third transistor M3 accesses the light-emission control voltage EMIT, described in source access
Second source voltage VDD, drain terminal couple the source of the driving transistor DM, and body end accesses the second source voltage
VDD, substrate terminal p5 ground connection.The grid end of the driving transistor DM couples the control terminal of the driving circuit 10, drain terminal coupling
The output end of the driving circuit 10 is connect, body end accesses the second source voltage VDD, substrate terminal p5 ground connection.Wherein, institute
The deep trap end n5 for stating the first transistor M1 and second transistor M2 accesses the second source voltage VDD, body end and substrate terminal n6
It is grounded, can prevent the PN junction inside the two N-type MOS transistors from leaking electricity.Herein, to put it more simply, only individually denoting N-type
The deep trap end n5 and substrate terminal n6 of MOS transistor and the substrate terminal p5 of N-type MOS transistor.
It should be noted that " logic high " and " logic low " herein is opposite logic level.Wherein,
" logic high " refers to can be identified as that the level range of digital signal " 1 ", " logic low " refer to be identified
For the level range of digital signal " 0 ", specific level range is simultaneously not particularly limited.
The embodiment of the invention also discloses a kind of image display device, which may include above-mentioned Fig. 1 institute
OLED pixel circuit 100, OLED pixel circuit shown in Fig. 2 200, OLED pixel circuit shown in Fig. 3 200 or the Fig. 7 shown
Shown in OLED pixel circuit 300.
Although present disclosure is as above, present invention is not limited to this.Anyone skilled in the art are not departing from this
It in the spirit and scope of invention, can make various changes or modifications, therefore protection scope of the present invention should be with claim institute
Subject to the range of restriction.