CN108920840A - A kind of circuit board product configuration tree and graphical Fusion Modeling Method - Google Patents
A kind of circuit board product configuration tree and graphical Fusion Modeling Method Download PDFInfo
- Publication number
- CN108920840A CN108920840A CN201810727040.4A CN201810727040A CN108920840A CN 108920840 A CN108920840 A CN 108920840A CN 201810727040 A CN201810727040 A CN 201810727040A CN 108920840 A CN108920840 A CN 108920840A
- Authority
- CN
- China
- Prior art keywords
- circuit board
- configuration tree
- board product
- graphical
- node
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/39—Circuit design at the physical level
- G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/36—Circuit design at the analogue level
- G06F30/367—Design verification, e.g. using simulation, simulation program with integrated circuit emphasis [SPICE], direct methods or relaxation methods
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structure Of Printed Boards (AREA)
Abstract
A kind of circuit board product configuration tree includes the following steps with graphical Fusion Modeling Method:(1) circuit board product configuration tree-model is constructed, the composition and hierarchical relationship of circuit board product configuration tree-model is specified, specifies the root node and leaf node of circuit board product configuration tree;(2) structured circuit panel products configuration tree and graphical Fusion Model are established, is blended by nodal community parameter set and the graphical parameter set of node and completes circuit board product parameter model, each node of configuration tree is graphically mapped one by one with it;(3) root node of circuit board product configuration tree and the attribute information parameter set suitable parameters of each of which leaf node are determined;(4) the graphical parameter set suitable parameters of each leaf node in circuit board product configuration tree are determined;(5) principle of allocated circuit panel products configuration tree building;(6) according to analyzed circuit board product self structure, fast parameter modeling is carried out to circuit board to be analyzed, constructs graphical model.
Description
(1) technical field:
The present invention provides a kind of circuit board product configuration tree and graphical Fusion Modeling Method, establishes the production of structured circuit plate
Product configuration tree and graphical Fusion Model, for each device and the graphical information of its own in circuit board product configuration tree
Mapping corresponds to one by one, and circuit board product configuration tree is parameterized and is graphically blended.Using the method for the present invention, circuit is being realized
While panel products Multiscale modelling, realization fast parameterization modeling improves the interactivity and visuality of circuit board product modeling,
It realizes that the real-time graph of " finding is to be built " is shown, greatly improves the efficiency of circuit board product modeling, reduce to complicated electricity
The difficulty of road panel products modeling.Belong to reliability and system engineering field.
(2) background technique:
Currently, circuit board product shows with the rapid development of electronic technology, new product and new technology continue to bring out
It complicates, diversified development trend.Simultaneously as people, to highly reliable, the demand of long-life electron equipment, circuit board heat is imitative
True analysis, vibration Simulation Analysis and failure/Reliability Simulation Analysis etc. need to carry out in Design Stage, to ensure circuit
The reliability of panel products.Correct test result is obtained in order to preferably carry out l-G simulation test, to quickly scheming by different level for product
Shapeization modeling is particularly important.However, complicated circuit board product is faced, the hardware based on circuit board product composition component
Tree modeling method, since it does not form the graphical of each node, modeling process is abstract, lacks visual and human-computer interaction
Property, the inevitable difficulty for increasing modeling reduces the correctness of modeling.
In consideration of it, it is necessary to provide one kind to be directed to labyrinth circuit board product, a kind of circuit board product configuration tree with
Graphical Fusion Modeling Method establishes circuit board product structure tree and graphically maps corresponding relationship one by one, possesses good man-machine
Interactivity and visuality realize the Multiscale modelling method of fast parameterization modeling, to improve the efficiency of circuit board product modeling,
And possibility is provided for the multiplex roles of model calling, realize the transmitting and succession of modeling information.
(3) summary of the invention:
In view of the above-mentioned problems, the invention proposes a kind of circuit board product configuration trees and the modeling method that graphically merges.
Realization is directed to the multi-level of labyrinth circuit board product, fast parameter models, the graphical integration modeling of " finding is to be built "
Method.
A kind of circuit board product configuration tree of the present invention and graphical Fusion Modeling Method, it includes the following steps:
Step 1:Circuit board product configuration tree-model is constructed, the composition and level for specifying circuit board product configuration tree-model close
System, specifies the root node and leaf node of circuit board product configuration tree;
Wherein, circuit board product configuration tree-model by:Equipment, circuit board, wiring board, component (front), component are (anti-
Face), totally 7 parts form for through-hole and insert, three layers can be divided into, separately included:
(1) top layer:Equipment
(2) middle layer:Circuit board
(3) bottom:Wiring board, component (front), component (reverse side), through-hole, insert
Wherein, it is specified that equipment is root node, the engineering pair to be analyzed for one in circuit board product configuration tree-model
As, generally off-the-shelf hardware (complete unit is manufactured), one and only one engineering equipment node;Provide each component part of bottom
For leaf node, including:Wiring board, component (front), component (reverse side), through-hole, insert.
Step 2:Structured circuit panel products configuration tree and graphical Fusion Model are established, by nodal community parameter set and section
Dot pattern parameter set, which blends, completes circuit board product parameter model, and each node of configuration tree is graphically mapped one by one with it.
Nodal community parameter set includes:Identification information parameter set, details parameter set and functional information parameter set;Node
Graphically parameter set includes:Parameter set is arranged in view information parameter set, layout information parameter set and plate layer.
(1) identification information parameter set is the coding and title of definition node, the unique identification information as node;
(2) details parameter set is that the attribute of different type node is described, and is joined including, for example, dielectric material etc.
Number;
(3) functional information parameter set is the detailed description to specific nodal function;
(4) view information parameter set is to the visualized graphs parameter set such as node definition shape, size, position, color
It closes;
(5) layout type of layout information parameter set definition node on circuit boards;
(6) plate layer setting parameter set is that definition node starts plate layer and terminates plate layer.
Wherein, identification information parameter set and view information parameter set are the required items of all kinds of nodes, both is for each
Specific node all uniquely determines, and is reflected one by one with the graphical information that this establishes each node of circuit board product configuration tree and itself
Penetrate relationship, by configuration tree with graphically blend.
Step 3:Determine the root node of circuit board product configuration tree and the sets of attribute parameters suitable parameters of all kinds of leaf nodes;
Wherein, each node for establishing node attribute information suitable parameters is respectively:
(1) circuit plate node (4) component node
(2) route plate node (5) insert node
(3) through-hole node
Step 4:Determine the graphical parameter set suitable parameters of each leaf node in circuit board product configuration tree;It is saved by setting
Position coordinate parameters, form parameter, dimensional parameters and the color value of point form the node overview information, realize 3-D graphic
Visual modeling;
Step 5:The principle of allocated circuit panel products configuration tree building;
(a) equipment can add multiple circuit plate nodes;
(b) a plate layer is added under assist side node, a wiring board can add multiple plate layers;
(c) 5 class nodes, i.e. wiring board, plated-through-hole, component, through-hole and insertion are automatically created under circuit plate node
Object;
(d) through-hole is added in through-hole node, multiple through-holes can be added;
(e) insert is added under insert node, multiple inserts can be added;
(f) 2 sub- class nodes are automatically created under component node, i.e. front, aspect;
(g) component is added under " component-front/reverse side " node, multiple components can be added under a node.
Step 6:Based on circuit board product configuration tree and graphical Fusion Model, with the method for the present invention, according to being analyzed
Circuit board product self structure, each nodal community parameter of input circuit panel products and its graphical parameter carry out circuit board product
Mathematics library by different level.
A kind of circuit board product configuration tree of the present invention and graphical Fusion Modeling Method, advantage and effect are:Building
A kind of circuit board product configuration tree establishes the graphical parameter model of structured circuit panel products, for circuit board product configuration tree
In each device mapped one by one with the graphical information of its device itself it is corresponding, by circuit board product configuration tree and graphical phase
Fusion.While realizing circuit board product Multiscale modelling, fast parameterization modeling is realized, improve circuit board product modeling
Interactivity and visuality realize the Dynamic graphic display of " finding is to be built ", greatly improve the effect of circuit board product modeling
Rate reduces the difficulty to complex circuit board Modeling in Product.
(4) Detailed description of the invention:
Implementation steps flow diagram Fig. 1 of the invention.
Fig. 2 circuit board product configuration tree schematic diagram.
Fig. 3 circuit board product configuration tree and graphical Fusion Model schematic diagram.
Fig. 4 " strain testing instrument circuit board " configuration tree and graphical mapping schematic diagram.
Fig. 5 circuit board product configuration Pterostyrax property information parameter model schematic.
The graphical information parameter model schematic of Fig. 6 circuit board product configuration tree.
(5) specific embodiment:
Case is modeled below in conjunction with Fig. 1 and strain testing instrument circuit board heat analysis, the present invention is made further detailed
Explanation.
It as shown in Figure 1, is the implementation steps flow diagram of the method for the present invention, for strain testing instrument circuit board modeling case
Example carries out circuit board product configuration tree and graphical integration modeling.
(1) circuit board product configuration tree-model is constructed, the composition and hierarchical relationship of circuit board product configuration tree-model are specified,
The root node and leaf node of circuit board product configuration tree are specified, specific structure is as shown in Figure 2;
Wherein, circuit board product configuration tree-model by:Equipment, circuit board, wiring board, component (front), component are (anti-
Face), totally 7 parts form for through-hole and insert, three layers can be divided into, separately included:
(a) top layer:Equipment
(b) middle layer:Circuit board
(c) bottom:Wiring board, component (front), component (reverse side), through-hole, insert
Wherein, it is specified that equipment is root node, the engineering pair to be analyzed for one in circuit board product configuration tree-model
As, generally off-the-shelf hardware (complete unit is manufactured), one and only one engineering equipment node;Provide each component part of bottom
For leaf node, including:Wiring board, component (front), component (reverse side), through-hole, insert.
Strain testing instrument circuit board is steady by resistance, capacitor, operational amplifier, voltage regulator, analog-digital chip, three ends
The part such as IC chip, output interface is pressed to form, therefore, strain testing instrument circuit panel configuration tree shares 61 component leaves
Node.
(2) structured circuit panel products configuration tree and graphical Fusion Model are established, structure is as shown in Figure 3.The model by
Nodal community parameter set and the graphical parameter set of node blend complete circuit board product parameter model, by each node of configuration tree with
It is graphically mapped one by one.
Nodal community parameter set includes:Identification information parameter set, details parameter set and functional information parameter set;Node
Graphically parameter set includes:Parameter set is arranged in view information parameter set, layout information parameter set and plate layer.
(a) identification information parameter set is the coding and title of definition node, the unique identification information as node;
(b) details parameter set is that the attribute of different type node is described, and is joined including, for example, dielectric material etc.
Number;
(c) functional information parameter set is the detailed description to specific nodal function;
(d) view information parameter set is to the visualized graphs parameter set such as node definition shape, size, position, color
It closes;
(e) layout type of layout information parameter set definition node on circuit boards;
(f) plate layer setting parameter set is that definition node starts plate layer and terminates plate layer.
Wherein, identification information parameter set and view information parameter set are the required items of all kinds of nodes, both is for each
Specific node all uniquely determines, and establishes each node of circuit board product configuration tree and patterned mapping relations one by one with this,
By configuration tree with graphically blend.
" strain testing instrument circuit board " is modeled with graphical Fusion Model by configuration tree, forms its circuit board structure
The each node attribute information of type tree and graphical information mapping relations one by one, as shown in Figure 4.
(3) root node of circuit board product configuration tree and the sets of attribute parameters suitable parameters of all kinds of leaf nodes, such as Fig. 5 are determined
It is shown;
Wherein, each node for establishing attribute information suitable parameters is respectively:
(a) circuit plate node (d) component node
(b) route plate node (e) insert node
(c) through-hole node
The suitable parameters of specific each node attribute information are described as follows:
(a) circuit plate node
The suitable parameters of circuit board node attribute information are described as follows shown in table:
(b) route plate node
Route plate node self attributes emphasis is facility information, will be illustrated in step (4) below, at this to route
The attribute suitable parameters of plate plate layer attribute information are determined, as shown in the table:
(c) through-hole node
The suitable parameters of circuit board node attribute information are described as follows shown in table:
(e) component node
The suitable parameters of component node attribute information are described as follows shown in table:
(f) insert node
The suitable parameters of insert node attribute information are described as follows shown in table:
Serial number | Parameter name | Data type | It must fill out | Input mode | Input constraint | Remarks |
1 | Insert title | Character type | Y | It directly inputs | Max number of characters 40 | |
2 | Insert coding | Character type | Y | It directly inputs | Max number of characters 40 |
(4) the graphical parameter set suitable parameters of each leaf node in circuit board product configuration tree are determined;By the way that node is arranged
Position coordinate parameters, form parameter, dimensional parameters and color value form the node overview information, realize that 3-D graphicization can
Depending on modeling, circuit board product configuration tree Image information parameter model such as Fig. 6;
(5) principle of allocated circuit panel products configuration tree building:
(a) equipment can add multiple circuit plate nodes;
(b) a plate layer is added under assist side node, a wiring board can add multiple plate layers;
(c) 5 class nodes, i.e. wiring board, plated-through-hole, component, through-hole and insertion are automatically created under circuit plate node
Object;
(d) through-hole is added in through-hole node, multiple through-holes can be added;
(e) insert is added under insert node, multiple inserts can be added;
(f) 2 sub- class nodes are automatically created under component node, i.e. front, aspect;
(g) component is added under " component-front/reverse side " node, multiple components can be added under a node.
Wherein, in the modeling of strain testing instrument circuit board heat analysis, building together, vertical " wiring board, plated-through-hole, component are (just
Face), component (reverse side), through-hole and insert " 6 class nodes;1 plate layer (B1) is added under assist side node;In component
(front) node adds 8 components (U1-U8);2 through-holes (H1-H2) are added under through-hole node;According to strain testing instrument
Circuit board practical structures do not add respective configuration tree node at " component (reverse side) " and " insert ".
(6) based on circuit board product configuration tree and graphical Fusion Model, with the method for the present invention, according to analyzed circuit
Panel products self structure, each nodal community parameter of input circuit panel products and its graphical parameter carry out circuit board product layering
Secondary mathematics library.
Claims (4)
1. a kind of circuit board product configuration tree and graphical Fusion Modeling Method, it is characterised in that:It includes the following steps:
(1) circuit board product configuration tree-model is constructed;
(2) building circuit board product configuration tree and graphical Fusion Model;
(3) root node of circuit board product configuration tree and the attribute information parameter set suitable parameters of each of which leaf node are determined;
(4) the graphical parameter set suitable parameters of each leaf node in circuit board product configuration tree are determined;
(5) principle of allocated circuit panel products configuration tree building;
(6) according to analyzed circuit board product self structure, each nodal community parameter of input circuit panel products and its graphical ginseng
Number carries out circuit board product mathematics library by different level.
2. a kind of circuit board product configuration tree according to claim 1 and graphical Fusion Modeling Method, it is characterised in that:
It is suitable for the circuit board product configuration tree of graphical display described in step (1), respectively by equipment, circuit board, wiring board, first device
Totally 7 parts form for part (front), component (reverse side), through-hole and insert, and wherein equipment is root node, wiring board, component
(front), component (reverse side), through-hole, insert are leaf node.Three layers can be divided into:
(1) top layer:Equipment
(2) middle layer:Circuit board
(3) bottom:Wiring board, component (front), component (reverse side), through-hole, insert.
3. a kind of circuit board product configuration tree according to claim 1 and graphical Fusion Modeling Method, it is characterised in that:
The structured circuit panel products configuration tree described in step (2) and graphical Fusion Model, by nodal community parameter set and node
Graphical parameter set, which blends, completes circuit board product parameter model, and each node of configuration tree is graphically mapped one by one with it.
4. a kind of circuit board product configuration tree according to claim 1 and graphical Fusion Modeling Method, it is characterised in that:
Step (3), step (4) choose the parameter of circuit board product configuration Pterostyrax property information parameter collection and graphical information parameter set.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810727040.4A CN108920840A (en) | 2018-07-05 | 2018-07-05 | A kind of circuit board product configuration tree and graphical Fusion Modeling Method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201810727040.4A CN108920840A (en) | 2018-07-05 | 2018-07-05 | A kind of circuit board product configuration tree and graphical Fusion Modeling Method |
Publications (1)
Publication Number | Publication Date |
---|---|
CN108920840A true CN108920840A (en) | 2018-11-30 |
Family
ID=64425205
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CN201810727040.4A Pending CN108920840A (en) | 2018-07-05 | 2018-07-05 | A kind of circuit board product configuration tree and graphical Fusion Modeling Method |
Country Status (1)
Country | Link |
---|---|
CN (1) | CN108920840A (en) |
Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1448870A (en) * | 2003-05-14 | 2003-10-15 | 西安交通大学 | Computer-aided technique planning method for silicon micro-component |
CN101526972A (en) * | 2009-04-21 | 2009-09-09 | 上海闻泰电子科技有限公司 | Setting device of circuit board and method thereof |
CN101901287A (en) * | 2010-07-16 | 2010-12-01 | 中国人民解放军信息工程大学 | Geometry and behavior integrated three-dimensional modeling method for spacecraft |
US7877724B2 (en) * | 2008-05-09 | 2011-01-25 | Lsi Corporation | Decision tree representation of a function |
CN104268338A (en) * | 2014-09-26 | 2015-01-07 | 北京航空航天大学 | Complex product failure effect transfer relation model as well as analysis and evaluation method thereof |
CN104899207A (en) * | 2014-03-05 | 2015-09-09 | 中国移动通信集团福建有限公司 | Visualized structured query language (SQL) condition tree establishing method and device |
CN105389169A (en) * | 2015-11-14 | 2016-03-09 | 深圳市参数领航科技有限公司 | Method and system for establishing technology tree |
CN107590319A (en) * | 2017-08-23 | 2018-01-16 | 南京理工大学 | A kind of knowledge modeling method and system for engineering goods scheme Computer Aided Design |
CN107644114A (en) * | 2016-07-20 | 2018-01-30 | 达索系统公司 | For designing the computer implemented method of clothes or upholstery by defining the sequence of assembling task |
-
2018
- 2018-07-05 CN CN201810727040.4A patent/CN108920840A/en active Pending
Patent Citations (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1448870A (en) * | 2003-05-14 | 2003-10-15 | 西安交通大学 | Computer-aided technique planning method for silicon micro-component |
US7877724B2 (en) * | 2008-05-09 | 2011-01-25 | Lsi Corporation | Decision tree representation of a function |
CN101526972A (en) * | 2009-04-21 | 2009-09-09 | 上海闻泰电子科技有限公司 | Setting device of circuit board and method thereof |
CN101901287A (en) * | 2010-07-16 | 2010-12-01 | 中国人民解放军信息工程大学 | Geometry and behavior integrated three-dimensional modeling method for spacecraft |
CN104899207A (en) * | 2014-03-05 | 2015-09-09 | 中国移动通信集团福建有限公司 | Visualized structured query language (SQL) condition tree establishing method and device |
CN104268338A (en) * | 2014-09-26 | 2015-01-07 | 北京航空航天大学 | Complex product failure effect transfer relation model as well as analysis and evaluation method thereof |
CN105389169A (en) * | 2015-11-14 | 2016-03-09 | 深圳市参数领航科技有限公司 | Method and system for establishing technology tree |
CN107644114A (en) * | 2016-07-20 | 2018-01-30 | 达索系统公司 | For designing the computer implemented method of clothes or upholstery by defining the sequence of assembling task |
CN107590319A (en) * | 2017-08-23 | 2018-01-16 | 南京理工大学 | A kind of knowledge modeling method and system for engineering goods scheme Computer Aided Design |
Non-Patent Citations (2)
Title |
---|
冯强 等: "产品综合设计过程建模方法与实现", 《计算机集成制造系统》 * |
康锐主编: "《RMS型号可靠性维修性保障性技术规范 第1册》", 30 November 2010, 国防工业出版社 * |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
CN100541502C (en) | A kind of PCB analogue system and its implementation with error detection function | |
US5946218A (en) | System and method for changing the connected behavior of a circuit design schematic | |
US6381563B1 (en) | System and method for simulating circuits using inline subcircuits | |
DE10137574B4 (en) | Method, computer program and data processing system for processing network topologies | |
CN105117835A (en) | A power grid information machine room three-dimensional visualized management platform based on a B/S framework | |
CN110175363A (en) | The generation method of the production drawing of Distributed Control System | |
CN101192247A (en) | Circuit connection calibration system and method | |
WO2007121435A2 (en) | Electromagnetic coupled basis functions for an electronic circuit | |
CN113705143B (en) | Automatic simulation system and automatic simulation method | |
US20140178845A1 (en) | System And Method For Electrical Theory Simulator | |
Martin | Cadence design environment | |
CN105824995B (en) | A kind of three-dimensional electromagnetic field simulation type generation method based on physical layout | |
CN109271701B (en) | Water supply and drainage BIM forward design method based on reach system | |
EP0742527B1 (en) | Method and system for producing a technology-independent integrated circuit design | |
Danković et al. | An electromechanical approach to a printed circuit board design course | |
CN108920840A (en) | A kind of circuit board product configuration tree and graphical Fusion Modeling Method | |
US20050251377A1 (en) | Circuit and electromagnetic simulator system and method | |
US20160125109A1 (en) | Polymorphic Circuit Simulation System | |
CN102682629B (en) | Line connection matching method and device for electronic whiteboard | |
CN106777565A (en) | A kind of satellite truss quick three-dimensional mask method | |
CN105446883A (en) | Model verification analysis method based on data configuration tool | |
CN109858155A (en) | Emulation mode and relevant apparatus | |
CN106407534A (en) | Electromagnetic transient simulation data processing method and device | |
CN106651142A (en) | Transformer station main equipment type selection method based on three-dimensional design platform | |
Li | A Web-based virtual laboratory for distance education |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PB01 | Publication | ||
PB01 | Publication | ||
SE01 | Entry into force of request for substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
WD01 | Invention patent application deemed withdrawn after publication |
Application publication date: 20181130 |
|
WD01 | Invention patent application deemed withdrawn after publication |