CN108880584B - Thousand-node MBUS host receiving circuit and control method - Google Patents
Thousand-node MBUS host receiving circuit and control method Download PDFInfo
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/10—Means associated with receiver for limiting or suppressing noise or interference
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L12/40006—Architecture of a communication node
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/28—Data switching networks characterised by path configuration, e.g. LAN [Local Area Networks] or WAN [Wide Area Networks]
- H04L12/40—Bus networks
- H04L2012/40208—Bus networks characterized by the use of a particular bus standard
- H04L2012/40228—Modbus
Abstract
The invention discloses a thousand-node MBUS host receiving circuit and a control method, which belong to the technical field of control and comprise the following steps: the device comprises a sampling resistor, a front-stage common-mode rejection differential amplifying circuit, an electronic switching circuit, a rear-stage common-mode rejection differential amplifying circuit, a comparator and a reference voltage circuit; the two ends of the sampling resistor are connected in series on the MBUS bus, the two ends of the sampling resistor are connected with the input end of the front-stage common mode rejection differential amplification circuit, the output end of the front-stage common mode rejection differential amplification circuit is connected with the input end of the rear-stage common mode rejection differential amplification circuit, and the output end of the rear-stage common mode rejection differential amplification circuit is connected with the comparator; the input end of the electronic switching circuit is respectively connected with the receiving and transmitting control signal of the MBUS and the front-stage common-mode rejection differential amplifying circuit, the output end of the electronic switching circuit is connected with the input end of the rear-stage common-mode rejection differential amplifying circuit, the output end of the reference voltage circuit is connected with the comparator, and the output end of the comparator is connected with the host receiving end MCU_RX.
Description
Technical Field
The invention relates to the technical field of control, in particular to a kilonode MBUS host receiving circuit and a control method.
Background
MBUS is a bus protocol specially designed for remote data transmission of heat meters, is an important technology for data transmission digitization of measuring meters, and has been widely applied to data acquisition occasions of passive contact water, electricity, gas, heat meters and the like.
The principle of the current commonly used MBUS receiving circuit is shown in figure 1, when a slave sends a signal, 20mA of current is consumed from an MBUS bus, the MBUS bus current converts a voltage signal through a sampling resistor with ten ohms, in-phase amplification is carried out by an amplifying device for 10 times, capacitance coupling is carried out, reference voltage enters the cathode of a comparator, and the comparator outputs a receiving signal MCU_RX. The defects of the method are as follows: poor anti-interference capability, less networking nodes, slow communication response time, influence on meter reading success rate from node quantity change and the like, so that on-site maintenance and installation are very difficult and the like.
Disclosure of Invention
The invention aims to provide a thousand-node MBUS host receiving circuit and a control method thereof so as to improve the anti-interference capability of the MBUS receiving circuit.
To achieve the above object, the present invention employs a kilonode MBUS host receiving circuit, comprising: the device comprises a sampling resistor, a front-stage common-mode rejection differential amplifying circuit, an electronic switching circuit, a rear-stage common-mode rejection differential amplifying circuit, a comparator and a reference voltage circuit;
the two ends of the sampling resistor are connected in series on the MBUS bus, the two ends of the sampling resistor are connected with the input end of the front-stage common mode rejection differential amplification circuit, the output end of the front-stage common mode rejection differential amplification circuit is connected with the input end of the rear-stage common mode rejection differential amplification circuit, and the output end of the rear-stage common mode rejection differential amplification circuit is connected with the comparator;
the input end of the electronic switching circuit is respectively connected with the receiving and transmitting control signal of the MBUS and the front-stage common-mode rejection differential amplifying circuit, the output end of the electronic switching circuit is connected with the input end of the rear-stage common-mode rejection differential amplifying circuit, the output end of the reference voltage circuit is connected with the comparator, and the output end of the comparator is connected with the host receiving end MCU_RX.
Further, the front-stage common mode rejection differential amplifying circuit comprises a first operational amplifier, a second operational amplifier and a third operational amplifier;
one end of the sampling resistor is connected with one end of the resistor R10, the other end of the resistor R10 is connected with one end of the resistor R37 and then connected with the normal phase input end of the first operational amplifier through the resistor R1, the other end of the sampling resistor is connected with one end of the resistor R21 and then connected with the normal phase input end of the second operational amplifier through the resistor R40, one end of the resistor R7 is connected with one end of the resistor R16 and then connected with the reverse input end of the first operational amplifier, the other end of the resistor R16 is connected with the other end of the resistor R24 and then connected with the reverse input end of the second operational amplifier, the other end of the resistor R7 is connected with one end of the resistor R4 and then connected with the output end of the first operational amplifier, and one end of the resistor R24 is connected with one end of the resistor R33 and then connected with the output end of the second operational amplifier;
the other end of the resistor R4 is respectively connected with one end of the resistor R5 and the non-inverting input end of the third operational amplifier, the other end of the resistor R5 is grounded, the other end of the resistor R33 is respectively connected with the inverting input end of the third operational amplifier and one end of the resistor R34, and the other end of the resistor R34 is respectively connected with the output end of the third operational amplifier and the input end of the electronic switching circuit.
Further, the rear-stage common mode rejection differential amplifying circuit includes a fourth operational amplifier, a fifth operational amplifier, and a sixth operational amplifier;
the positive input end of the fourth operational amplifier is connected with the output end of the third operational amplifier, one end of the resistor R22 is connected with one end of the resistor R27 and then connected with the reverse input end of the fourth operational amplifier, the other end of the resistor R27 is connected with one end of the resistor R47 and then connected with the reverse input end of the fifth operational amplifier, the positive input end of the fifth operational amplifier is connected with the output end of the electronic switching circuit, the other end of the resistor R22 is connected with one end of the resistor R17 and then connected with the output end of the fourth operational amplifier, and the other end of the resistor R47 is connected with one end of the resistor R49 and then connected with the output end of the fifth operational amplifier;
the other end of the resistor R17 is connected with one end of the resistor R18 and the non-inverting input end of the sixth operational amplifier respectively, the other end of the resistor R49 is connected with one end of the resistor R48 and the inverting input end of the sixth operational amplifier respectively, and the other end of the resistor R48 is connected with the output end of the sixth operational amplifier.
Further, the electronic switching circuit comprises a MOS tube Q8, a MOS tube Q9 and a MOS tube Q10;
the other end of the resistor R34 is connected with the drain electrode of the MOS tube Q8, the source electrode of the MOS tube Q8 is connected with the source electrode of the MOS tube Q9, the drain electrode of the MOS tube Q9 is respectively connected with the positive electrode of the capacitor C4 and the positive input end of the fifth operational amplifier, the grid electrode of the MOS tube Q8 is sequentially connected with the grid electrode of the MOS tube Q9 and one end of the capacitor C31, the other end of the capacitor C31 is connected with one end of the resistor R64 and then grounded, the other end of the resistor R64 is connected with one end of the resistor R63 and then connected with the grid electrode of the MOS tube Q8, and the other end of the resistor R63 is connected with the MBUS_30V voltage output end;
the grid electrode of the MOS tube Q8 is connected to the drain electrode of the MOS tube Q10 after passing through the connection point of the resistor R63 and the resistor R64, the source electrode of the MOS tube Q10 is grounded, and the grid electrode of the MOS tube Q10 is connected to the MBUS-CON signal output end after passing through the resistor R65.
Further, the comparator includes a seventh operational amplifier, an output end of the sixth operational amplifier is connected to an inverting input end of the seventh operational amplifier, a voltage output end of the reference voltage circuit is connected to a non-inverting input end of the seventh operational amplifier, an output end of the seventh operational amplifier is connected to one end of a resistor R13, the other end of the resistor R13 is connected to one end of a resistor R9 and then connected to a host receiving end mcu_rx, and the other end of the resistor R9 is grounded.
Further, the resistance value of the sampling resistor is smaller than 0.5 omega.
On the other hand, a control method of a thousand-node MBUS host receiving circuit is provided, which comprises the following steps:
when the MBUS host is in an idle state, an MBUS bus sending signal MBUS_TX is high, a receiving signal MBUS_RX is high, and a receiving and transmitting control signal MBUS_CON is low, so that an electronic switch circuit conducts capacitor charging and provides a reference level for a rear-stage common mode rejection differential amplifying circuit of the receiving signal;
when the MBUS bus transmits a signal, the transmitting mbus_tx transmits a frame of data, the receiving signal mbus_rx is high, and the transmitting and receiving control signal mbus_con is high to turn off the electronic switching circuit;
when the receiving signal mbus_rx receives a frame of data, the transmitting signal mbus_tx is high, the receiving and transmitting control signal mbus_con continues to be high, and the electronic switch circuit is continuously turned off.
When the receiving signal mbus_rx is received, the receiving and transmitting control signal mbus_con is immediately set low to open the electronic switch circuit to charge the capacitor C31 for the next receiving signal.
Compared with the prior art, the invention has the following technical effects: the invention uses a high-precision high-power sampling resistor with low resistance less than 0.5 omega to be connected in series with an MBUS bus, when a slave sends data, 11-20mA current is consumed from the bus, the current is converted into a voltage signal through the sampling resistor, and the voltage less than 9mv is amplified by 15 times through a front-stage common-mode rejection differential amplification circuit. The front-stage common-mode rejection differential amplification circuit has the characteristics of balanced differential input impedance, low output impedance, isolation of closed loop gain from the signal input end of the circuit by using an internal feedback resistor network and the like, greatly improves the rejection ratio of common-mode signals, and enables 9mv voltage signals to be effectively extracted and amplified in noise, thereby ensuring the stability and anti-interference of received signals.
Drawings
The following detailed description of specific embodiments of the invention refers to the accompanying drawings, in which:
FIG. 1 is a schematic diagram of a thousands of nodes MBUS host receiving circuit;
FIG. 2 is a topology diagram of a thousand node MBUS host receive circuit;
fig. 3 is a timing control diagram.
Detailed Description
For a further description of the features of the present invention, refer to the following detailed description of the invention and the accompanying drawings. The drawings are for reference and illustration purposes only and are not intended to limit the scope of the present invention.
As shown in fig. 1, the present embodiment discloses a kilonode MBUS host receiving circuit, which includes: a sampling resistor 1, a front-stage common-mode rejection differential amplifying circuit 2, an electronic switching circuit 4, a rear-stage common-mode rejection differential amplifying circuit 3, a comparator 5 and a reference voltage circuit 6;
the two ends of the sampling resistor 1 are connected in series on an MBUS bus, the two ends of the sampling resistor 1 are connected with the input end of the front-stage common mode rejection differential amplification circuit 2, the output end of the front-stage common mode rejection differential amplification circuit 2 is connected with the input end of the rear-stage common mode rejection differential amplification circuit 3, and the output end of the rear-stage common mode rejection differential amplification circuit 3 is connected with the comparator 5;
the input end of the electronic switching circuit 4 is respectively connected with the receiving and transmitting control signal of the MBUS and the front-stage common-mode rejection differential amplification circuit 2, the output end of the electronic switching circuit 4 is connected with the input end of the rear-stage common-mode rejection differential amplification circuit 3, the output end of the reference voltage circuit 6 is connected with the comparator 5, and the output end of the comparator 5 is connected with the host receiving end MCU_RX.
Specifically, the high-precision high-power low-resistance sampling resistor with the resistance less than 0.5 omega is connected in series with the MBUS bus, and when the slave sends data, 11-20mA current is consumed from the bus, and the current is converted into a voltage signal through the sampling resistor.
As shown in fig. 2, the front-stage common-mode rejection differential amplifying circuit 2 includes: a first operational amplifier U1A, a second operational amplifier U1B, and a third operational amplifier U2A;
one end of the sampling resistor is connected with one end of the resistor R10, the other end of the resistor R10 is connected with one end of the resistor R37 and then connected with the normal phase input end of the first operational amplifier U1A through the resistor R1, the other end of the sampling resistor is connected with one end of the resistor R21 and then connected with one end of the resistor R38 and then connected with the normal phase input end of the second operational amplifier U1B through the resistor R40, one end of the resistor R7 is connected with one end of the resistor R16 and then connected with the reverse input end of the first operational amplifier U1A, the other end of the resistor R16 is connected with the other end of the resistor R24 and then connected with the reverse input end of the second operational amplifier U1B, the other end of the resistor R7 is connected with one end of the resistor R4 and then connected with the output end of the first operational amplifier U1A, and one end of the resistor R24 is connected with one end of the resistor R33 and then connected with the output end of the second operational amplifier U1B;
the other end of the resistor R4 is respectively connected with one end of the resistor R5 and the positive input end of the third operational amplifier U2A, the other end of the resistor R5 is grounded, the other end of the resistor R33 is respectively connected with the reverse input end of the third operational amplifier U2A and one end of the resistor R34, and the other end of the resistor R34 is respectively connected with the output end of the third operational amplifier U2A and the input end of the electronic switching circuit.
In this embodiment, the current signal is converted into the voltage signal, and then the voltage of less than 9mv is amplified 15 times by the front-stage common mode rejection differential amplification circuit 2. The circuit has the characteristics of balanced differential input impedance, low output impedance, isolation of closed loop gain from the signal input end by using an internal feedback resistor network and the like, greatly improves the rejection ratio of common mode signals, and ensures that 9mv voltage signals can be effectively extracted and amplified in noise, thereby ensuring the stability and anti-interference of received signals. The existing receiving circuit adopts a single operational amplifier, the closed loop gain adopted by differential amplification is determined by an external resistor, the input end signal and the feedback resistor network are not isolated, the impedance of the in-phase input end and the opposite-phase input end is very low and unequal, if the impedance matching value difference is 0.1%, the common mode rejection CMR is reduced to 66db, the source impedance value difference is 100 omega, and the common mode rejection CMR is reduced to 6db, so that the difference of the input end gains can directly influence the rejection of common mode noise, and the interference of output signals is caused.
Further, as shown in fig. 2, the post-stage common mode rejection differential amplifying circuit 3 includes a fourth operational amplifier U3A, a fifth operational amplifier U3B, and a sixth operational amplifier U4A;
the positive input end of the fourth operational amplifier U3A is connected with the output end of the third operational amplifier U2A, one end of the resistor R22 is connected with one end of the resistor R27 and then connected with the reverse input end of the fourth operational amplifier U3A, the other end of the resistor R27 is connected with one end of the resistor R47 and then connected with the reverse input end of the fifth operational amplifier U3B, the positive input end of the fifth operational amplifier U3B is connected with the output end of the electronic switch circuit 4, the other end of the resistor R22 is connected with one end of the resistor R17 and then connected with the output end of the fourth operational amplifier U3A, and the other end of the resistor R47 is connected with one end of the resistor R49 and then connected with the output end of the fifth operational amplifier U3B;
the other end of the resistor R17 is connected with one end of the resistor R18 and the non-inverting input end of the sixth operational amplifier U4A respectively, the other end of the resistor R49 is connected with one end of the resistor R48 and the inverting input end of the sixth operational amplifier U4A respectively, and the other end of the resistor R48 is connected with the output end of the sixth operational amplifier U4A.
The voltage signal is amplified by the front-stage common mode rejection differential amplification circuit 2 and then amplified by 66 times after entering the rear-stage common mode rejection differential amplification circuit 3; the purpose is to eliminate the DC level generated by the previous stage amplification and to suppress the signal effective by common mode noise amplification again.
Further, as shown in fig. 2, the electronic switching circuit 4 includes a MOS transistor Q8, a MOS transistor Q9, and a MOS transistor Q10;
the other end of the resistor R34 is connected with the drain electrode of the MOS tube Q8, the source electrode of the MOS tube Q8 is connected with the source electrode of the MOS tube Q9, the drain electrode of the MOS tube Q9 is respectively connected with the positive electrode of the capacitor C4 and the positive input end of the fifth operational amplifier U3B, the grid electrode of the MOS tube Q8 is sequentially connected with the grid electrode of the MOS tube Q9 and one end of the capacitor C31, the other end of the capacitor C31 is connected with one end of the resistor R64 and then grounded, the other end of the resistor R64 is connected with one end of the resistor R63 and then connected with the grid electrode of the MOS tube Q8, and the other end of the resistor R63 is connected with the MBUS_30V voltage output end;
the grid electrode of the MOS tube Q8 is connected to the drain electrode of the MOS tube Q10 after passing through the connection point of the resistor R63 and the resistor R64, the source electrode of the MOS tube Q10 is grounded, and the grid electrode of the MOS tube Q10 is connected to the MBUS-CON signal output end after passing through the resistor R65.
Specifically, according to the characteristic that the MOS tube has saturated on zero impedance and off zero impedance, the Q10, Q8 and Q9 combined circuit has the functions of no-voltage-loss output and reverse leakage current protection, when the MBUS-CON signal is low, the Q10 is cut off, and the Q8 and the Q9 are conducted to charge the capacitor to provide reference voltage for the rear-stage common-mode rejection differential amplifying circuit 3; when the MBUS-CON signal is high, Q10 is on, Q8 and Q9 are off, and Q9 has the function of preventing the current voltage value of the reverse leakage current holding capacitor.
Further, as shown in fig. 2, the comparator 5 includes a seventh operational amplifier U5B, an output end of the sixth operational amplifier U4A is connected to an inverting input end of the seventh operational amplifier U5B, a voltage output end of the reference voltage circuit is connected to a non-inverting input end of the seventh operational amplifier U5B, an output end of the seventh operational amplifier U5B is connected to one end of the resistor R13, the other end of the resistor R13 is connected to one end of the resistor R9 and then connected to the host receiving end mcu_rx, and the other end of the resistor R9 is grounded.
The signal amplified by the rear common mode rejection amplifier is connected to the inverting terminal of the seventh operational amplifier U5B, the reference voltage 1.8V is connected to the non-inverting terminal of the seventh operational amplifier U5B, so that the signal level of the inverting terminal is compared with the non-inverting terminal reference voltage, when the signal level of the inverting terminal is greater than the non-inverting terminal, the output of the seventh operational amplifier U5B is low, and when the signal level of the inverting terminal is less than the reference voltage of the non-inverting terminal, the output of the seventh operational amplifier U5B is high, and therefore the signal output by the seventh operational amplifier U5B is the received signal mbus_rx of MBUS.
Specifically, the reference voltage circuit composition includes R61, R62, C19, and R100; the MBUS_30V voltage is respectively connected with the R62, the R100, the C19 and the comparator U5B through the R61, the other ends of the resistors R62 and the R100 are grounded, the other end of the bypass capacitor C19 is grounded, and a voltage division principle is adopted through the resistor to generate a reference voltage of 1.8V.
In the thousand-node MBUS host receiving circuit in the embodiment, the MBUS bus is connected with a sampling resistor with high precision, high power and low resistance value less than 0.5 omega in series, and when the equipment slave transmits data, 10-20mA current is consumed on the bus, so that a current signal on the bus is converted into a voltage signal through the sampling resistor, the 9mv voltage signal is amplified by 15 times through a front-stage common mode rejection differential amplifying circuit 2, and the amplified output signals are respectively connected with the same-phase end of a rear-stage differential amplifying circuit and the opposite end through an electronic switch; the electronic switch is controlled to charge the capacitor through the MBUS_CON signal, the capacitor is turned off after full charge, the capacitor is charged before each time of data receiving, the capacitor is turned off after full charge, the constant refresh is guaranteed, the effective signal is amplified again for 66 times through the rear-stage common-mode rejection differential amplifying circuit 3, common-mode interference is eliminated, and the effective signal enters the seventh operational amplifier U5B to be compared with the reference voltage level to output a receiving signal MBUS_RX.
The circuit has the advantages that the high-power low-resistance sampling resistor and the common-mode rejection differential amplifying circuit are adopted to effectively reject common-mode noise to extract a few millivolts of voltage signals for amplification, so that the number of bus nodes is greatly increased to 2300 nodes; the device slave node changes without affecting the communication of other nodes through the electronic switch and the real-time refreshing; the amplification of the circuit signal does not adopt a capacitive coupling mode, and the response time is fast.
As shown in fig. 3, the present embodiment provides a control method for a receiving circuit of a kilonode MBUS host, including the following steps: the control unit transceiving signals comprise a sending signal MBUS_TX, a receiving signal MBUS_RX and a transceiving control signal MBUS_CON of the MBUS bus.
When the MBUS is in an idle state, the bus transmit signal mbus_tx is high, the receive signal mbus_rx is high, and the transmit-receive control signal mbus_con is low; the electronic switch circuit is used for conducting the capacitor to charge, providing a reference level for amplifying and eliminating static direct current level of the rear-stage common mode rejection differential amplifying circuit of the received signal, and also has the characteristic of detecting the fluctuation of the node load from time to time.
When the MBUS bus transmits a signal, when the MBUS_TX transmits one frame of data, the receiving signal is simultaneously MBUS_RX high, and the receiving and transmitting control signal MBUS_CON is simultaneously high; the function is as follows: the signal MBUS_RX is high, and the receiving and transmitting control signal MBUS_CON is high, so that the electronic switch is turned off, interference to the receiving signal MBUS_RX when the bus transmits data is prevented, and the receiving signal is more stable, so that the influence of the transmitting signal is avoided.
When the receiving signal receives data, the receiving signal mbus_rx receives a frame of data, the transmitting signal mbus_tx is high, and the receiving and transmitting control signal mbus_con continues to be high; the electronic switch is used for restraining interference caused by a transmitted signal and improving the anti-interference capability of a received signal.
When the receiving signal MBUS_RX is received, the receiving and transmitting control signal MBUS_CON is immediately set low, and acts to open the electronic switch to charge the capacitor, so as to prepare for the next receiving signal, namely, provide a reference level for the post-stage common mode rejection differential amplifying circuit, and detect the node variation, so that the node variation does not influence the communication of other nodes.
The foregoing description of the preferred embodiments of the invention is not intended to limit the invention to the precise form disclosed, and any such modifications, equivalents, and alternatives falling within the spirit and scope of the invention are intended to be included within the scope of the invention.
Claims (6)
1. A kilonode MBUS host receiving circuit, comprising: the device comprises a sampling resistor, a front-stage common-mode rejection differential amplifying circuit, an electronic switching circuit, a rear-stage common-mode rejection differential amplifying circuit, a comparator and a reference voltage circuit;
the two ends of the sampling resistor are connected in series on the MBUS bus, the two ends of the sampling resistor are connected with the input end of the front-stage common mode rejection differential amplification circuit, the output end of the front-stage common mode rejection differential amplification circuit is connected with the input end of the rear-stage common mode rejection differential amplification circuit, and the output end of the rear-stage common mode rejection differential amplification circuit is connected with the comparator;
the input end of the electronic switching circuit is respectively connected with the receiving and transmitting control signal of the MBUS and the front-stage common-mode rejection differential amplification circuit, the output end of the electronic switching circuit is connected with the input end of the rear-stage common-mode rejection differential amplification circuit, the output end of the reference voltage circuit is connected with the comparator, and the output end of the comparator is connected with the host receiving end MCU_RX;
the front-stage common mode rejection differential amplification circuit comprises a first operational amplifier, a second operational amplifier and a third operational amplifier;
one end of the sampling resistor is connected with one end of the resistor R10, the other end of the resistor R10 is connected with one end of the resistor R37 and then connected with the normal phase input end of the first operational amplifier through the resistor R1, the other end of the sampling resistor is connected with one end of the resistor R21 and then connected with the normal phase input end of the second operational amplifier through the resistor R40, one end of the resistor R7 is connected with one end of the resistor R16 and then connected with the reverse input end of the first operational amplifier, the other end of the resistor R16 is connected with the other end of the resistor R24 and then connected with the reverse input end of the second operational amplifier, the other end of the resistor R7 is connected with one end of the resistor R4 and then connected with the output end of the first operational amplifier, and one end of the resistor R24 is connected with one end of the resistor R33 and then connected with the output end of the second operational amplifier;
the other end of the resistor R4 is respectively connected with one end of the resistor R5 and the non-inverting input end of the third operational amplifier, the other end of the resistor R5 is grounded, the other end of the resistor R33 is respectively connected with the inverting input end of the third operational amplifier and one end of the resistor R34, and the other end of the resistor R34 is respectively connected with the output end of the third operational amplifier and the input end of the electronic switching circuit.
2. The kilonode MBUS host receiving circuit according to claim 1, characterized in that the post-stage common mode rejection differential amplifying circuit includes a fourth operational amplifier, a fifth operational amplifier, and a sixth operational amplifier;
the positive input end of the fourth operational amplifier is connected with the output end of the third operational amplifier, one end of the resistor R22 is connected with one end of the resistor R27 and then connected with the reverse input end of the fourth operational amplifier, the other end of the resistor R27 is connected with one end of the resistor R47 and then connected with the reverse input end of the fifth operational amplifier, the positive input end of the fifth operational amplifier is connected with the output end of the electronic switching circuit, the other end of the resistor R22 is connected with one end of the resistor R17 and then connected with the output end of the fourth operational amplifier, and the other end of the resistor R47 is connected with one end of the resistor R49 and then connected with the output end of the fifth operational amplifier;
the other end of the resistor R17 is connected with one end of the resistor R18 and the non-inverting input end of the sixth operational amplifier respectively, the other end of the resistor R49 is connected with one end of the resistor R48 and the inverting input end of the sixth operational amplifier respectively, and the other end of the resistor R48 is connected with the output end of the sixth operational amplifier.
3. The kilonode MBUS host receiving circuit according to claim 2, characterized in that the electronic switching circuit includes a MOS transistor Q8, a MOS transistor Q9, and a MOS transistor Q10;
the other end of the resistor R34 is connected with the drain electrode of the MOS tube Q8, the source electrode of the MOS tube Q8 is connected with the source electrode of the MOS tube Q9, the drain electrode of the MOS tube Q9 is respectively connected with the positive electrode of the capacitor C4 and the positive input end of the fifth operational amplifier, the grid electrode of the MOS tube Q8 is sequentially connected with the grid electrode of the MOS tube Q9 and one end of the capacitor C31, the other end of the capacitor C31 is connected with one end of the resistor R64 and then grounded, the other end of the resistor R64 is connected with one end of the resistor R63 and then connected with the grid electrode of the MOS tube Q8, and the other end of the resistor R63 is connected with the MBUS_30V voltage output end;
the grid electrode of the MOS tube Q8 is connected to the drain electrode of the MOS tube Q10 after passing through the connection point of the resistor R63 and the resistor R64, the source electrode of the MOS tube Q10 is grounded, and the grid electrode of the MOS tube Q10 is connected to the MBUS-CON signal output end after passing through the resistor R65.
4. The kilonode MBUS host receiving circuit according to claim 2, characterized in that the comparator includes a seventh operational amplifier, an output end of the sixth operational amplifier is connected to an inverting input end of the seventh operational amplifier, a voltage output end of the reference voltage circuit is connected to a non-inverting input end of the seventh operational amplifier, an output end of the seventh operational amplifier is connected to one end of a resistor R13, another end of the resistor R13 is connected to one end of a resistor R9 and then connected to the host receiving end mcu_rx, and another end of the resistor R9 is grounded.
5. The kilonode MBUS host receiving circuit according to claim 1, wherein the resistance value of the sampling resistor is less than 0.5 Ω.
6. A control method using the kilonode MBUS host receiving circuit of claim 1, comprising:
when the MBUS host is in an idle state, an MBUS bus sending signal MBUS_TX is high, a receiving signal MBUS_RX is high, and a receiving and transmitting control signal MBUS_CON is low, so that an electronic switch circuit conducts capacitor charging and provides a reference level for a rear-stage common mode rejection differential amplifying circuit of the receiving signal;
when the MBUS bus transmits a signal, the transmitting mbus_tx transmits a frame of data, the receiving signal mbus_rx is high, and the transmitting and receiving control signal mbus_con is high to turn off the electronic switching circuit;
when the receiving signal mbus_rx receives a frame of data, the transmitting signal mbus_tx is high, the receiving and transmitting control signal mbus_con continues to be high, and the electronic switch circuit is continuously turned off;
when the receiving signal mbus_rx is received, the receiving and transmitting control signal mbus_con is immediately set low to open the electronic switch circuit to charge the capacitor C31 for the next receiving signal.
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